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drm/i915: Introduce i915_gem_object_finish_gpu()
... reincarnated from i915_gem_object_flush_gpu(). The semantic difference is that after calling finish_gpu() the object no longer resides in any GPU domain, and so will cause the GPU caches to be invalidated if it is ever used again. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1190,7 +1190,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
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int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
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uint32_t read_domains,
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uint32_t write_domain);
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int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj);
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int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
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int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
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void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
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void i915_gem_do_init(struct drm_device *dev,
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@ -2165,23 +2165,29 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
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return -EINVAL;
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}
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/* blow away mappings if mapped through GTT */
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i915_gem_release_mmap(obj);
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/* Move the object to the CPU domain to ensure that
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* any possible CPU writes while it's not in the GTT
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* are flushed when we go to remap it. This will
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* also ensure that all pending GPU writes are finished
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* before we unbind.
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*/
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ret = i915_gem_object_set_to_cpu_domain(obj, 1);
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ret = i915_gem_object_finish_gpu(obj);
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if (ret == -ERESTARTSYS)
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return ret;
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/* Continue on if we fail due to EIO, the GPU is hung so we
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* should be safe and we need to cleanup or else we might
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* cause memory corruption through use-after-free.
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*/
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/* blow away mappings if mapped through GTT */
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i915_gem_release_mmap(obj);
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/* Move the object to the CPU domain to ensure that
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* any possible CPU writes while it's not in the GTT
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* are flushed when we go to remap it.
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*/
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if (ret == 0)
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ret = i915_gem_object_set_to_cpu_domain(obj, 1);
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if (ret == -ERESTARTSYS)
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return ret;
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if (ret) {
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/* In the event of a disaster, abandon all caches and
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* hope for the best.
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*/
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i915_gem_clflush_object(obj);
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obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
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}
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@ -3045,11 +3051,11 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
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}
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int
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i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
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i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
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{
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int ret;
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if (!obj->active)
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if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
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return 0;
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if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
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@ -3058,6 +3064,9 @@ i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
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return ret;
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}
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/* Ensure that we invalidate the GPU's caches and TLBs. */
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obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
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return i915_gem_object_wait_rendering(obj);
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}
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@ -1971,7 +1971,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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* This should only fail upon a hung GPU, in which case we
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* can safely continue.
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*/
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ret = i915_gem_object_flush_gpu(obj);
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ret = i915_gem_object_finish_gpu(obj);
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(void) ret;
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}
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