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clk: meson: meson8b: add the CPU clock post divider clocks
There are four CPU clock post dividers: - ABP - PERIPH (used for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Each of these clocks consists of two clocks: - a mux to select between "cpu_clk" divided by 2, 3, 4, 5, 6, 7 or 8 - a "_clk_dis" gate. The public S805 datasheet states that this should be set to 1 to disable the clock, the default value is 0. There is also a hint that these are "just in case" bits which only exist in case the corresponding mux implementation does not allow glitch-free parent changes (the muxes are designed in a way that the clock can stay enabled when changing the mux). It's still good practise to describe this clock even if we're not supposed to modify it. Thus this uses the read-only gate ops. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181122214017.25643-5-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl
Neil Armstrong
parent
700ecf7f51
commit
a7d19b05ce
@ -704,6 +704,227 @@ static struct clk_regmap meson8b_nand_clk_gate = {
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},
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};
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static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_div2",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
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.mult = 1,
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.div = 3,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_div3",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
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.mult = 1,
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.div = 4,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_div4",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
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.mult = 1,
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.div = 5,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_div5",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
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.mult = 1,
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.div = 6,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_div6",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
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.mult = 1,
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.div = 7,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_div7",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
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.mult = 1,
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.div = 8,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_div8",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static u32 mux_table_abp[] = { 1, 2, 3, 4, 5, 6, 7 };
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static struct clk_regmap meson8b_abp_clk_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.mask = 0x7,
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.shift = 3,
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.table = mux_table_abp,
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},
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.hw.init = &(struct clk_init_data){
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.name = "abp_clk_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "cpu_clk_div2",
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"cpu_clk_div3",
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"cpu_clk_div4",
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"cpu_clk_div5",
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"cpu_clk_div6",
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"cpu_clk_div7",
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"cpu_clk_div8", },
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.num_parents = 7,
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},
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};
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static struct clk_regmap meson8b_abp_clk_gate = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 16,
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.flags = CLK_GATE_SET_TO_DISABLE,
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},
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.hw.init = &(struct clk_init_data){
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.name = "abp_clk_dis",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "abp_clk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_periph_clk_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.mask = 0x7,
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.shift = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "periph_clk_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "cpu_clk_div2",
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"cpu_clk_div3",
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"cpu_clk_div4",
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"cpu_clk_div5",
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"cpu_clk_div6",
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"cpu_clk_div7",
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"cpu_clk_div8", },
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.num_parents = 7,
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},
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};
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static struct clk_regmap meson8b_periph_clk_gate = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 17,
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.flags = CLK_GATE_SET_TO_DISABLE,
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},
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.hw.init = &(struct clk_init_data){
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.name = "periph_clk_dis",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "periph_clk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
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static struct clk_regmap meson8b_axi_clk_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.mask = 0x7,
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.shift = 9,
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.table = mux_table_axi,
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},
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.hw.init = &(struct clk_init_data){
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.name = "axi_clk_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "cpu_clk_div2",
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"cpu_clk_div3",
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"cpu_clk_div4",
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"cpu_clk_div5",
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"cpu_clk_div6",
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"cpu_clk_div7",
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"cpu_clk_div8", },
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.num_parents = 7,
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},
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};
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static struct clk_regmap meson8b_axi_clk_gate = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 18,
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.flags = CLK_GATE_SET_TO_DISABLE,
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},
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.hw.init = &(struct clk_init_data){
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.name = "axi_clk_dis",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "axi_clk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_l2_dram_clk_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.mask = 0x7,
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.shift = 12,
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},
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.hw.init = &(struct clk_init_data){
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.name = "l2_dram_clk_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "cpu_clk_div2",
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"cpu_clk_div3",
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"cpu_clk_div4",
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"cpu_clk_div5",
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"cpu_clk_div6",
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"cpu_clk_div7",
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"cpu_clk_div8", },
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.num_parents = 7,
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},
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};
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static struct clk_regmap meson8b_l2_dram_clk_gate = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 19,
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.flags = CLK_GATE_SET_TO_DISABLE,
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},
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.hw.init = &(struct clk_init_data){
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.name = "l2_dram_clk_dis",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "l2_dram_clk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
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@ -905,6 +1126,21 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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[CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
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[CLKID_PLL_VID_DCO] = &meson8b_vid_pll_dco.hw,
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[CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
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[CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
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[CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
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[CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
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[CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
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[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
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[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
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[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
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[CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw,
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[CLKID_ABP] = &meson8b_abp_clk_gate.hw,
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[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
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[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
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[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
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[CLKID_AXI] = &meson8b_axi_clk_gate.hw,
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[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
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[CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -1016,6 +1252,14 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
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&meson8b_fixed_pll_dco,
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&meson8b_vid_pll_dco,
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&meson8b_sys_pll_dco,
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&meson8b_abp_clk_sel,
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&meson8b_abp_clk_gate,
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&meson8b_periph_clk_sel,
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&meson8b_periph_clk_gate,
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&meson8b_axi_clk_sel,
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&meson8b_axi_clk_gate,
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&meson8b_l2_dram_clk_sel,
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&meson8b_l2_dram_clk_gate,
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};
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static const struct meson8b_clk_reset_line {
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@ -78,8 +78,19 @@
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#define CLKID_PLL_FIXED_DCO 113
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#define CLKID_PLL_VID_DCO 114
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#define CLKID_PLL_SYS_DCO 115
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#define CLKID_CPU_CLK_DIV2 116
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#define CLKID_CPU_CLK_DIV3 117
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#define CLKID_CPU_CLK_DIV4 118
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#define CLKID_CPU_CLK_DIV5 119
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#define CLKID_CPU_CLK_DIV6 120
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#define CLKID_CPU_CLK_DIV7 121
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#define CLKID_CPU_CLK_DIV8 122
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#define CLKID_ABP_SEL 123
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#define CLKID_PERIPH_SEL 125
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#define CLKID_AXI_SEL 127
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#define CLKID_L2_DRAM_SEL 129
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#define CLK_NR_CLKS 116
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#define CLK_NR_CLKS 131
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/*
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* include the CLKID and RESETID that have
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