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iommu/vt-d: Enhance intel_irq_remapping driver to support DMAR unit hotplug
Implement required callback functions for intel_irq_remapping driver to support DMAR unit hotplug. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Jiang Liu
Joerg Roedel
parent
d35165a955
commit
a7a3dad944
@ -36,7 +36,6 @@ struct hpet_scope {
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static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
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static struct hpet_scope ir_hpet[MAX_HPET_TBS];
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static int ir_ioapic_num, ir_hpet_num;
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/*
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* Lock ordering:
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@ -206,7 +205,7 @@ static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
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int i;
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for (i = 0; i < MAX_HPET_TBS; i++)
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if (ir_hpet[i].id == hpet_id)
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if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
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return ir_hpet[i].iommu;
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return NULL;
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}
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@ -216,7 +215,7 @@ static struct intel_iommu *map_ioapic_to_ir(int apic)
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int i;
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for (i = 0; i < MAX_IO_APICS; i++)
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if (ir_ioapic[i].id == apic)
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if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
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return ir_ioapic[i].iommu;
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return NULL;
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}
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@ -325,7 +324,7 @@ static int set_ioapic_sid(struct irte *irte, int apic)
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down_read(&dmar_global_lock);
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for (i = 0; i < MAX_IO_APICS; i++) {
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if (ir_ioapic[i].id == apic) {
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if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
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sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
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break;
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}
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@ -352,7 +351,7 @@ static int set_hpet_sid(struct irte *irte, u8 id)
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down_read(&dmar_global_lock);
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for (i = 0; i < MAX_HPET_TBS; i++) {
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if (ir_hpet[i].id == id) {
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if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
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sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
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break;
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}
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@ -473,17 +472,17 @@ static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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static int intel_setup_irq_remapping(struct intel_iommu *iommu, int mode)
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static int intel_setup_irq_remapping(struct intel_iommu *iommu)
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{
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struct ir_table *ir_table;
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struct page *pages;
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unsigned long *bitmap;
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ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
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GFP_ATOMIC);
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if (iommu->ir_table)
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return 0;
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if (!iommu->ir_table)
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ir_table = kzalloc(sizeof(struct ir_table), GFP_ATOMIC);
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if (!ir_table)
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return -ENOMEM;
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pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
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@ -492,24 +491,37 @@ static int intel_setup_irq_remapping(struct intel_iommu *iommu, int mode)
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if (!pages) {
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pr_err("IR%d: failed to allocate pages of order %d\n",
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iommu->seq_id, INTR_REMAP_PAGE_ORDER);
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kfree(iommu->ir_table);
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return -ENOMEM;
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goto out_free_table;
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}
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bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
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sizeof(long), GFP_ATOMIC);
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if (bitmap == NULL) {
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pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
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__free_pages(pages, INTR_REMAP_PAGE_ORDER);
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kfree(ir_table);
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return -ENOMEM;
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goto out_free_pages;
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}
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ir_table->base = page_address(pages);
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ir_table->bitmap = bitmap;
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iommu_set_irq_remapping(iommu, mode);
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iommu->ir_table = ir_table;
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return 0;
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out_free_pages:
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__free_pages(pages, INTR_REMAP_PAGE_ORDER);
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out_free_table:
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kfree(ir_table);
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return -ENOMEM;
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}
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static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
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{
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if (iommu && iommu->ir_table) {
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free_pages((unsigned long)iommu->ir_table->base,
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INTR_REMAP_PAGE_ORDER);
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kfree(iommu->ir_table->bitmap);
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kfree(iommu->ir_table);
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iommu->ir_table = NULL;
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}
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}
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/*
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@ -666,9 +678,10 @@ static int __init intel_enable_irq_remapping(void)
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if (!ecap_ir_support(iommu->ecap))
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continue;
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if (intel_setup_irq_remapping(iommu, eim))
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if (intel_setup_irq_remapping(iommu))
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goto error;
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iommu_set_irq_remapping(iommu, eim);
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setup = 1;
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}
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@ -699,12 +712,13 @@ error:
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return -1;
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}
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static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
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struct intel_iommu *iommu)
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static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
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struct intel_iommu *iommu,
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struct acpi_dmar_hardware_unit *drhd)
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{
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struct acpi_dmar_pci_path *path;
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u8 bus;
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int count;
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int count, free = -1;
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bus = scope->bus;
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path = (struct acpi_dmar_pci_path *)(scope + 1);
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@ -720,19 +734,36 @@ static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
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PCI_SECONDARY_BUS);
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path++;
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}
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ir_hpet[ir_hpet_num].bus = bus;
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ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->device, path->function);
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ir_hpet[ir_hpet_num].iommu = iommu;
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ir_hpet[ir_hpet_num].id = scope->enumeration_id;
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ir_hpet_num++;
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for (count = 0; count < MAX_HPET_TBS; count++) {
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if (ir_hpet[count].iommu == iommu &&
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ir_hpet[count].id == scope->enumeration_id)
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return 0;
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else if (ir_hpet[count].iommu == NULL && free == -1)
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free = count;
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}
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if (free == -1) {
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pr_warn("Exceeded Max HPET blocks\n");
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return -ENOSPC;
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}
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ir_hpet[free].iommu = iommu;
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ir_hpet[free].id = scope->enumeration_id;
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ir_hpet[free].bus = bus;
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ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
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pr_info("HPET id %d under DRHD base 0x%Lx\n",
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scope->enumeration_id, drhd->address);
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return 0;
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}
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static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
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struct intel_iommu *iommu)
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static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
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struct intel_iommu *iommu,
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struct acpi_dmar_hardware_unit *drhd)
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{
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struct acpi_dmar_pci_path *path;
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u8 bus;
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int count;
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int count, free = -1;
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bus = scope->bus;
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path = (struct acpi_dmar_pci_path *)(scope + 1);
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@ -749,54 +780,63 @@ static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
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path++;
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}
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ir_ioapic[ir_ioapic_num].bus = bus;
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ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->device, path->function);
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ir_ioapic[ir_ioapic_num].iommu = iommu;
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ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
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ir_ioapic_num++;
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for (count = 0; count < MAX_IO_APICS; count++) {
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if (ir_ioapic[count].iommu == iommu &&
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ir_ioapic[count].id == scope->enumeration_id)
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return 0;
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else if (ir_ioapic[count].iommu == NULL && free == -1)
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free = count;
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}
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if (free == -1) {
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pr_warn("Exceeded Max IO APICS\n");
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return -ENOSPC;
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}
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ir_ioapic[free].bus = bus;
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ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
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ir_ioapic[free].iommu = iommu;
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ir_ioapic[free].id = scope->enumeration_id;
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pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
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scope->enumeration_id, drhd->address, iommu->seq_id);
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return 0;
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}
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static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
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struct intel_iommu *iommu)
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{
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int ret = 0;
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struct acpi_dmar_hardware_unit *drhd;
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struct acpi_dmar_device_scope *scope;
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void *start, *end;
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drhd = (struct acpi_dmar_hardware_unit *)header;
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start = (void *)(drhd + 1);
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end = ((void *)drhd) + header->length;
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while (start < end) {
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while (start < end && ret == 0) {
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scope = start;
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if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
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if (ir_ioapic_num == MAX_IO_APICS) {
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printk(KERN_WARNING "Exceeded Max IO APICS\n");
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return -1;
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}
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printk(KERN_INFO "IOAPIC id %d under DRHD base "
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" 0x%Lx IOMMU %d\n", scope->enumeration_id,
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drhd->address, iommu->seq_id);
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ir_parse_one_ioapic_scope(scope, iommu);
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} else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
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if (ir_hpet_num == MAX_HPET_TBS) {
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printk(KERN_WARNING "Exceeded Max HPET blocks\n");
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return -1;
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}
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printk(KERN_INFO "HPET id %d under DRHD base"
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" 0x%Lx\n", scope->enumeration_id,
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drhd->address);
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ir_parse_one_hpet_scope(scope, iommu);
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}
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if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
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ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
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else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
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ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
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start += scope->length;
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}
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return 0;
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return ret;
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}
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static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
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{
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int i;
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for (i = 0; i < MAX_HPET_TBS; i++)
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if (ir_hpet[i].iommu == iommu)
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ir_hpet[i].iommu = NULL;
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for (i = 0; i < MAX_IO_APICS; i++)
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if (ir_ioapic[i].iommu == iommu)
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ir_ioapic[i].iommu = NULL;
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}
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/*
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@ -1172,7 +1212,85 @@ struct irq_remap_ops intel_irq_remap_ops = {
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.alloc_hpet_msi = intel_alloc_hpet_msi,
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};
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/*
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* Support of Interrupt Remapping Unit Hotplug
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*/
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static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
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{
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int ret;
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int eim = x2apic_enabled();
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if (eim && !ecap_eim_support(iommu->ecap)) {
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pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
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iommu->reg_phys, iommu->ecap);
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return -ENODEV;
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}
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if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
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pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
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iommu->reg_phys);
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return -ENODEV;
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}
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/* TODO: check all IOAPICs are covered by IOMMU */
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/* Setup Interrupt-remapping now. */
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ret = intel_setup_irq_remapping(iommu);
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if (ret) {
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pr_err("DRHD %Lx: failed to allocate resource\n",
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iommu->reg_phys);
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ir_remove_ioapic_hpet_scope(iommu);
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return ret;
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}
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if (!iommu->qi) {
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/* Clear previous faults. */
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dmar_fault(-1, iommu);
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iommu_disable_irq_remapping(iommu);
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dmar_disable_qi(iommu);
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}
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/* Enable queued invalidation */
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ret = dmar_enable_qi(iommu);
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if (!ret) {
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iommu_set_irq_remapping(iommu, eim);
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} else {
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pr_err("DRHD %Lx: failed to enable queued invalidation, ecap %Lx, ret %d\n",
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iommu->reg_phys, iommu->ecap, ret);
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intel_teardown_irq_remapping(iommu);
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ir_remove_ioapic_hpet_scope(iommu);
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}
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return ret;
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}
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int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
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{
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return irq_remapping_enabled ? -ENOSYS : 0;
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int ret = 0;
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struct intel_iommu *iommu = dmaru->iommu;
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if (!irq_remapping_enabled)
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return 0;
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if (iommu == NULL)
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return -EINVAL;
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if (!ecap_ir_support(iommu->ecap))
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return 0;
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if (insert) {
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if (!iommu->ir_table)
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ret = dmar_ir_add(dmaru, iommu);
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} else {
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if (iommu->ir_table) {
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if (!bitmap_empty(iommu->ir_table->bitmap,
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INTR_REMAP_TABLE_ENTRIES)) {
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ret = -EBUSY;
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} else {
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iommu_disable_irq_remapping(iommu);
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intel_teardown_irq_remapping(iommu);
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ir_remove_ioapic_hpet_scope(iommu);
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}
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}
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}
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return ret;
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}
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