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clk: imx: imx93: add mcore_booted module paratemter
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX93, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and LPCG (clock gating) to gate clocks to peripherals. As below: anatop->ccm->lpcg->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for LPCG and CCM, auxiliary core normally only use LPCG hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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@ -222,7 +222,7 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, &clk_mux_ro_ops, div_hw,
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&clk_divider_ro_ops, NULL, NULL, flags);
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} else {
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} else if (!mcore_booted) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto fail;
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@ -238,6 +238,12 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p
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&imx93_clk_composite_divider_ops, gate_hw,
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&imx93_clk_composite_gate_ops,
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flags | CLK_SET_RATE_NO_REPARENT);
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} else {
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, &imx93_clk_composite_mux_ops, div_hw,
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&imx93_clk_composite_divider_ops, NULL,
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&imx93_clk_composite_gate_ops,
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flags | CLK_SET_RATE_NO_REPARENT);
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}
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if (IS_ERR(hw))
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@ -352,6 +352,8 @@ static struct platform_driver imx93_clk_driver = {
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},
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};
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module_platform_driver(imx93_clk_driver);
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module_param(mcore_booted, bool, 0444);
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MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
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MODULE_DESCRIPTION("NXP i.MX93 clock driver");
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MODULE_LICENSE("GPL v2");
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