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Merge branch 'net-phy-eee-2'

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Heiner Kallweit says:

====================
net: phy: add support for the EEE 2 registers

This series adds support for the EEE 2 registers. Most relevant and
for now the only supported modes are 2500baseT and 5000baseT.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2024-02-17 18:45:06 +00:00
commit a6e0cb150c
4 changed files with 137 additions and 0 deletions
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69
drivers/net/phy/phy-c45.c
View File

@ -706,6 +706,22 @@ int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv)
changed = 1;
}
if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
val = linkmode_to_mii_eee_cap2_t(adv);
/* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2
* (Register 7.62)
*/
val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
MDIO_AN_EEE_ADV2,
MDIO_EEE_2_5GT | MDIO_EEE_5GT,
val);
if (val < 0)
return val;
if (val > 0)
changed = 1;
}
if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
phydev->supported_eee)) {
val = linkmode_adv_to_mii_10base_t1_t(adv);
@ -745,6 +761,17 @@ int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv)
mii_eee_cap1_mod_linkmode_t(adv, val);
}
if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
/* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2
* (Register 7.62)
*/
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
if (val < 0)
return val;
mii_eee_cap2_mod_linkmode_adv_t(adv, val);
}
if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
phydev->supported_eee)) {
/* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
@ -781,6 +808,17 @@ static int genphy_c45_read_eee_lpa(struct phy_device *phydev,
mii_eee_cap1_mod_linkmode_t(lpa, val);
}
if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
/* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2
* (Register 7.63)
*/
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2);
if (val < 0)
return val;
mii_eee_cap2_mod_linkmode_adv_t(lpa, val);
}
if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
phydev->supported_eee)) {
/* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register
@ -830,6 +868,30 @@ static int genphy_c45_read_eee_cap1(struct phy_device *phydev)
return 0;
}
/**
* genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21
* @phydev: target phy_device struct
*/
static int genphy_c45_read_eee_cap2(struct phy_device *phydev)
{
int val;
/* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2
* (Register 3.21)
*/
val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2);
if (val < 0)
return val;
/* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */
if (val == 0xffff)
return 0;
mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val);
return 0;
}
/**
* genphy_c45_read_eee_abilities - read supported EEE link modes
* @phydev: target phy_device struct
@ -848,6 +910,13 @@ int genphy_c45_read_eee_abilities(struct phy_device *phydev)
return val;
}
/* Same for cap2 (3.21) */
if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) {
val = genphy_c45_read_eee_cap2(phydev);
if (val)
return val;
}
if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
phydev->supported)) {
/* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register

11
drivers/net/phy/phy_device.c
View File

@ -148,6 +148,14 @@ static const int phy_eee_cap1_features_array[] = {
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;
EXPORT_SYMBOL_GPL(phy_eee_cap1_features);
static const int phy_eee_cap2_features_array[] = {
ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
};
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init;
EXPORT_SYMBOL_GPL(phy_eee_cap2_features);
static void features_init(void)
{
/* 10/100 half/full*/
@ -232,6 +240,9 @@ static void features_init(void)
linkmode_set_bit_array(phy_eee_cap1_features_array,
ARRAY_SIZE(phy_eee_cap1_features_array),
phy_eee_cap1_features);
linkmode_set_bit_array(phy_eee_cap2_features_array,
ARRAY_SIZE(phy_eee_cap2_features_array),
phy_eee_cap2_features);
}

55
include/linux/mdio.h
View File

@ -439,6 +439,42 @@ static inline void mii_eee_cap1_mod_linkmode_t(unsigned long *adv, u32 val)
adv, val & MDIO_EEE_10GKR);
}
/**
* mii_eee_cap2_mod_linkmode_sup_t()
* @adv: target the linkmode settings
* @val: register value
*
* A function that translates value of following registers to the linkmode:
* IEEE 802.3-2022 45.2.3.11 "EEE control and capability 2" register (3.21)
*/
static inline void mii_eee_cap2_mod_linkmode_sup_t(unsigned long *adv, u32 val)
{
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
adv, val & MDIO_EEE_2_5GT);
linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
adv, val & MDIO_EEE_5GT);
}
/**
* mii_eee_cap2_mod_linkmode_adv_t()
* @adv: target the linkmode advertisement settings
* @val: register value
*
* A function that translates value of following registers to the linkmode:
* IEEE 802.3-2022 45.2.7.16 "EEE advertisement 2" register (7.62)
* IEEE 802.3-2022 45.2.7.17 "EEE link partner ability 2" register (7.63)
* Note: Currently this function is the same as mii_eee_cap2_mod_linkmode_sup_t.
* For certain, not yet supported, modes however the bits differ.
* Therefore create separate functions already.
*/
static inline void mii_eee_cap2_mod_linkmode_adv_t(unsigned long *adv, u32 val)
{
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
adv, val & MDIO_EEE_2_5GT);
linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
adv, val & MDIO_EEE_5GT);
}
/**
* linkmode_to_mii_eee_cap1_t()
* @adv: the linkmode advertisement settings
@ -466,6 +502,25 @@ static inline u32 linkmode_to_mii_eee_cap1_t(unsigned long *adv)
return result;
}
/**
* linkmode_to_mii_eee_cap2_t()
* @adv: the linkmode advertisement settings
*
* A function that translates linkmode to value for IEEE 802.3-2022 45.2.7.16
* "EEE advertisement 2" register (7.62)
*/
static inline u32 linkmode_to_mii_eee_cap2_t(unsigned long *adv)
{
u32 result = 0;
if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, adv))
result |= MDIO_EEE_2_5GT;
if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, adv))
result |= MDIO_EEE_5GT;
return result;
}
/**
* mii_10base_t1_adv_mod_linkmode_t()
* @adv: linkmode advertisement settings

2
include/linux/phy.h
View File

@ -54,6 +54,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init;
#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
@ -65,6 +66,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;
#define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features)
#define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features)
#define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features)
#define PHY_EEE_CAP2_FEATURES ((unsigned long *)&phy_eee_cap2_features)
extern const int phy_basic_ports_array[3];
extern const int phy_fibre_port_array[1];