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Reset controller changes for v4.12
- make reset drivers with bool Kconfig options explicitly non-modular - fix uniphier non-static symbol warnings - fix socfpga nr_resets property - new drivers for the Arria10 and i.MX7 system reset controllers - fix sunxi 64-bit compilation -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEBsBxhV1FaKwXuCOBUMKIHHCeYOsFAljJUToXHHAuemFiZWxA cGVuZ3V0cm9uaXguZGUACgkQUMKIHHCeYOvFnxAA8ImyPCzDDMtgGo9zMRId4ICH /YbbYrc5Gp3vDJJnJYVD0KCOT4174yinvHxrxpmjiftcZWcQRNH881uFJpgmXUjW zT7SapC0REWMx/DQzcR/Gh0smiehU1hVi+PSosNNqwbpZZrlxOAgGSoFYw87pBtJ gSOwTfUWlSEVMBtsQpTeO7cUzc5HvxuIvu/SMORi3xP1nukv8WIDuSGGFAWv235D OQOe101hQBO64yyW1J2X6+UMH+fHgmVT9qhqT6uJgYfR57pO17vX1aF/GEP9GV9R /vja0Y8hMNyvbc9CcJJQjR6BfXIOjrCYdDs+9nV4znYAcQpLJN5wfB6kDzogpH4S 3vgIsqT0OHYCdcXahuPuzDtE9zJ3oktyZT3MPyOsIkCwxGt5IJKRF9XGEGF3E/Sl 0yRpC45riac+8vuNJHnOe2qjRmx+zkAioyTPmYwPihwb1rLTYUtnqjat3egG1z0q UZvCpOcuQ9X/cAo+IIZW6IhDf6cqWEPks3pGinJ5XZ66qoeW5UMJz8v+i7c2F0oK LFLedERgaergvpAShiSeZTlXFkWQAJvGzDoCbpYTeQHELPV/ZJn88rJGP2DJ4/l1 7Sy5lyjFWtZqvfsBnoMniYc1XG2v5kztzAp9pZFEzBMHEVgCyJla5PxF7rDb+U/k tzeSfwd3DUkT8qtB1K4= =5xmN -----END PGP SIGNATURE----- Merge tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux into next/drivers Reset controller changes for v4.12 - make reset drivers with bool Kconfig options explicitly non-modular - fix uniphier non-static symbol warnings - fix socfpga nr_resets property - new drivers for the Arria10 and i.MX7 system reset controllers - fix sunxi 64-bit compilation * tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux: reset: sunxi: fix for 64-bit compilation reset: Add Altera Arria10 SR Reset Controller dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets reset: Add i.MX7 SRC reset driver reset-socfpga: Fix nr_resets property reset: uniphier: fix non static symbol warnings reset: pistachio: make it explicitly non-modular reset: ath79: make it explicitly non-modular reset: oxnas: make it explicitly non-modular reset: meson: make it explicitly non-modular Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
a618a7349f
47
Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
Normal file
47
Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
Normal file
@ -0,0 +1,47 @@
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Freescale i.MX7 System Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "fsl,imx7-src", "syscon"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain SRC interrupt
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- #reset-cells: 1, see below
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example:
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src: reset-controller@30390000 {
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compatible = "fsl,imx7d-src", "syscon";
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reg = <0x30390000 0x2000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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The system reset controller can be used to reset various set of
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peripherals. Device nodes that need access to reset lines should
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specify them as a reset phandle in their corresponding node as
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specified in reset.txt.
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Example:
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pcie: pcie@33800000 {
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...
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resets = <&src IMX7_RESET_PCIEPHY>,
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<&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
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reset-names = "pciephy", "apps";
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...
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};
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For list of all valid reset indicies see
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<dt-bindings/reset/imx7-reset.h>
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@ -653,7 +653,9 @@ M: Thor Thayer <thor.thayer@linux.intel.com>
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S: Maintained
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F: drivers/gpio/gpio-altera-a10sr.c
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F: drivers/mfd/altera-a10sr.c
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F: drivers/reset/reset-a10sr.c
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F: include/linux/mfd/altera-a10sr.h
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F: include/dt-bindings/reset/altr,rst-mgr-a10sr.h
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ALTERA TRIPLE SPEED ETHERNET DRIVER
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M: Vince Bridgers <vbridger@opensource.altera.com>
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@ -14,6 +14,13 @@ menuconfig RESET_CONTROLLER
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if RESET_CONTROLLER
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config RESET_A10SR
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tristate "Altera Arria10 System Resource Reset"
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depends on MFD_ALTERA_A10SR
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help
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This option enables support for the external reset functions for
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peripheral PHYs on the Altera Arria10 System Resource Chip.
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config RESET_ATH79
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bool "AR71xx Reset Driver" if COMPILE_TEST
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default ATH79
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@ -27,6 +34,13 @@ config RESET_BERLIN
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help
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This enables the reset controller driver for Marvell Berlin SoCs.
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config RESET_IMX7
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bool "i.MX7 Reset Driver" if COMPILE_TEST
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default SOC_IMX7D
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select MFD_SYSCON
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help
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This enables the reset controller driver for i.MX7 SoCs.
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config RESET_LPC18XX
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bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
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default ARCH_LPC18XX
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@ -2,8 +2,10 @@ obj-y += core.o
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obj-y += hisilicon/
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obj-$(CONFIG_ARCH_STI) += sti/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
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obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
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obj-$(CONFIG_RESET_MESON) += reset-meson.o
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obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
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@ -15,3 +17,4 @@ obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o
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obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
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138
drivers/reset/reset-a10sr.c
Normal file
138
drivers/reset/reset-a10sr.c
Normal file
@ -0,0 +1,138 @@
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/*
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* Copyright Intel Corporation (C) 2017. All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Reset driver for Altera Arria10 MAX5 System Resource Chip
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*
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* Adapted from reset-socfpga.c
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*/
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#include <linux/err.h>
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#include <linux/mfd/altera-a10sr.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
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struct a10sr_reset {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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static inline struct a10sr_reset *to_a10sr_rst(struct reset_controller_dev *rc)
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{
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return container_of(rc, struct a10sr_reset, rcdev);
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}
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static inline int a10sr_reset_shift(unsigned long id)
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{
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switch (id) {
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case A10SR_RESET_ENET_HPS:
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return 1;
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case A10SR_RESET_PCIE:
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case A10SR_RESET_FILE:
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case A10SR_RESET_BQSPI:
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case A10SR_RESET_USB:
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return id + 11;
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default:
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return -EINVAL;
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}
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}
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static int a10sr_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct a10sr_reset *a10r = to_a10sr_rst(rcdev);
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int offset = a10sr_reset_shift(id);
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u8 mask = ALTR_A10SR_REG_BIT_MASK(offset);
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int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset);
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return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask);
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}
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static int a10sr_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return a10sr_reset_update(rcdev, id, true);
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}
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static int a10sr_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return a10sr_reset_update(rcdev, id, false);
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}
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static int a10sr_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int ret;
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struct a10sr_reset *a10r = to_a10sr_rst(rcdev);
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int offset = a10sr_reset_shift(id);
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u8 mask = ALTR_A10SR_REG_BIT_MASK(offset);
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int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset);
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unsigned int value;
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ret = regmap_read(a10r->regmap, index, &value);
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if (ret < 0)
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return ret;
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return !!(value & mask);
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}
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static const struct reset_control_ops a10sr_reset_ops = {
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.assert = a10sr_reset_assert,
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.deassert = a10sr_reset_deassert,
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.status = a10sr_reset_status,
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};
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static int a10sr_reset_probe(struct platform_device *pdev)
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{
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struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
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struct a10sr_reset *a10r;
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a10r = devm_kzalloc(&pdev->dev, sizeof(struct a10sr_reset),
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GFP_KERNEL);
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if (!a10r)
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return -ENOMEM;
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a10r->rcdev.owner = THIS_MODULE;
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a10r->rcdev.nr_resets = A10SR_RESET_NUM;
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a10r->rcdev.ops = &a10sr_reset_ops;
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a10r->rcdev.of_node = pdev->dev.of_node;
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a10r->regmap = a10sr->regmap;
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platform_set_drvdata(pdev, a10r);
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return devm_reset_controller_register(&pdev->dev, &a10r->rcdev);
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}
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static const struct of_device_id a10sr_reset_of_match[] = {
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{ .compatible = "altr,a10sr-reset" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, a10sr_reset_of_match);
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static struct platform_driver a10sr_reset_driver = {
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.probe = a10sr_reset_probe,
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.driver = {
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.name = "altr_a10sr_reset",
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},
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};
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module_platform_driver(a10sr_reset_driver);
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MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
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MODULE_DESCRIPTION("Altera Arria10 System Resource Reset Controller Driver");
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MODULE_LICENSE("GPL v2");
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@ -1,4 +1,7 @@
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/*
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* AR71xx Reset Controller Driver
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* Author: Alban Bedel
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*
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* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
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*
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* This program is free software; you can redistribute it and/or modify
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@ -13,7 +16,7 @@
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/reboot.h>
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@ -127,31 +130,17 @@ static int ath79_reset_probe(struct platform_device *pdev)
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return 0;
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}
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static int ath79_reset_remove(struct platform_device *pdev)
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{
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struct ath79_reset *ath79_reset = platform_get_drvdata(pdev);
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unregister_restart_handler(&ath79_reset->restart_nb);
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return 0;
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}
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static const struct of_device_id ath79_reset_dt_ids[] = {
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{ .compatible = "qca,ar7100-reset", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ath79_reset_dt_ids);
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static struct platform_driver ath79_reset_driver = {
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.probe = ath79_reset_probe,
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.remove = ath79_reset_remove,
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.driver = {
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.name = "ath79-reset",
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.of_match_table = ath79_reset_dt_ids,
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.name = "ath79-reset",
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.of_match_table = ath79_reset_dt_ids,
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.suppress_bind_attrs = true,
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},
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};
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module_platform_driver(ath79_reset_driver);
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MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
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MODULE_DESCRIPTION("AR71xx Reset Controller Driver");
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MODULE_LICENSE("GPL");
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builtin_platform_driver(ath79_reset_driver);
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158
drivers/reset/reset-imx7.c
Normal file
158
drivers/reset/reset-imx7.c
Normal file
@ -0,0 +1,158 @@
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/*
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* Copyright (c) 2017, Impinj, Inc.
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*
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* i.MX7 System Reset Controller (SRC) driver
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mfd/syscon.h>
|
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/regmap.h>
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#include <dt-bindings/reset/imx7-reset.h>
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|
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struct imx7_src {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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enum imx7_src_registers {
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SRC_A7RCR0 = 0x0004,
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SRC_M4RCR = 0x000c,
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SRC_ERCR = 0x0014,
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SRC_HSICPHY_RCR = 0x001c,
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SRC_USBOPHY1_RCR = 0x0020,
|
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SRC_USBOPHY2_RCR = 0x0024,
|
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SRC_MIPIPHY_RCR = 0x0028,
|
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SRC_PCIEPHY_RCR = 0x002c,
|
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SRC_DDRC_RCR = 0x1000,
|
||||
};
|
||||
|
||||
struct imx7_src_signal {
|
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unsigned int offset, bit;
|
||||
};
|
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|
||||
static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
|
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[IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
|
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[IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
|
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[IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
|
||||
[IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
|
||||
[IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
|
||||
[IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
|
||||
[IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
|
||||
[IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
|
||||
[IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
|
||||
[IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
|
||||
[IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
|
||||
[IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
|
||||
[IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
|
||||
[IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
|
||||
[IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
|
||||
[IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
|
||||
[IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
|
||||
[IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
|
||||
[IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
|
||||
[IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
|
||||
[IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
|
||||
[IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
|
||||
[IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
|
||||
[IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
|
||||
[IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
|
||||
};
|
||||
|
||||
static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev)
|
||||
{
|
||||
return container_of(rcdev, struct imx7_src, rcdev);
|
||||
}
|
||||
|
||||
static int imx7_reset_set(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
struct imx7_src *imx7src = to_imx7_src(rcdev);
|
||||
const struct imx7_src_signal *signal = &imx7_src_signals[id];
|
||||
unsigned int value = 0;
|
||||
|
||||
switch (id) {
|
||||
case IMX7_RESET_PCIEPHY:
|
||||
/*
|
||||
* wait for more than 10us to release phy g_rst and
|
||||
* btnrst
|
||||
*/
|
||||
if (!assert)
|
||||
udelay(10);
|
||||
break;
|
||||
|
||||
case IMX7_RESET_PCIE_CTRL_APPS_EN:
|
||||
value = (assert) ? 0 : signal->bit;
|
||||
break;
|
||||
}
|
||||
|
||||
return regmap_update_bits(imx7src->regmap,
|
||||
signal->offset, signal->bit, value);
|
||||
}
|
||||
|
||||
static int imx7_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return imx7_reset_set(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return imx7_reset_set(rcdev, id, false);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops imx7_reset_ops = {
|
||||
.assert = imx7_reset_assert,
|
||||
.deassert = imx7_reset_deassert,
|
||||
};
|
||||
|
||||
static int imx7_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct imx7_src *imx7src;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct regmap_config config = { .name = "src" };
|
||||
|
||||
imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
|
||||
if (!imx7src)
|
||||
return -ENOMEM;
|
||||
|
||||
imx7src->regmap = syscon_node_to_regmap(dev->of_node);
|
||||
if (IS_ERR(imx7src->regmap)) {
|
||||
dev_err(dev, "Unable to get imx7-src regmap");
|
||||
return PTR_ERR(imx7src->regmap);
|
||||
}
|
||||
regmap_attach_dev(dev, imx7src->regmap, &config);
|
||||
|
||||
imx7src->rcdev.owner = THIS_MODULE;
|
||||
imx7src->rcdev.nr_resets = IMX7_RESET_NUM;
|
||||
imx7src->rcdev.ops = &imx7_reset_ops;
|
||||
imx7src->rcdev.of_node = dev->of_node;
|
||||
|
||||
return devm_reset_controller_register(dev, &imx7src->rcdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id imx7_reset_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx7d-src", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct platform_driver imx7_reset_driver = {
|
||||
.probe = imx7_reset_probe,
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.of_match_table = imx7_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(imx7_reset_driver);
|
||||
@ -1,4 +1,6 @@
|
||||
/*
|
||||
* Amlogic Meson Reset Controller driver
|
||||
*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
@ -53,7 +55,7 @@
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -95,7 +97,6 @@ static const struct of_device_id meson_reset_dt_ids[] = {
|
||||
{ .compatible = "amlogic,meson-gxbb-reset", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
|
||||
|
||||
static int meson_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
@ -128,9 +129,4 @@ static struct platform_driver meson_reset_driver = {
|
||||
.of_match_table = meson_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(meson_reset_driver);
|
||||
|
||||
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
||||
MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
builtin_platform_driver(meson_reset_driver);
|
||||
|
||||
@ -18,7 +18,7 @@
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
@ -83,7 +83,6 @@ static const struct of_device_id oxnas_reset_dt_ids[] = {
|
||||
{ .compatible = "oxsemi,ox820-reset", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, oxnas_reset_dt_ids);
|
||||
|
||||
static int oxnas_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
@ -123,5 +122,4 @@ static struct platform_driver oxnas_reset_driver = {
|
||||
.of_match_table = oxnas_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(oxnas_reset_driver);
|
||||
builtin_platform_driver(oxnas_reset_driver);
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
@ -128,7 +128,6 @@ static const struct of_device_id pistachio_reset_dt_ids[] = {
|
||||
{ .compatible = "img,pistachio-reset", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, pistachio_reset_dt_ids);
|
||||
|
||||
static struct platform_driver pistachio_reset_driver = {
|
||||
.probe = pistachio_reset_probe,
|
||||
@ -137,8 +136,4 @@ static struct platform_driver pistachio_reset_driver = {
|
||||
.of_match_table = pistachio_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(pistachio_reset_driver);
|
||||
|
||||
MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
|
||||
MODULE_DESCRIPTION("Pistacho Reset Controller Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
builtin_platform_driver(pistachio_reset_driver);
|
||||
|
||||
@ -25,7 +25,8 @@
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define NR_BANKS 4
|
||||
#define BANK_INCREMENT 4
|
||||
#define NR_BANKS 8
|
||||
|
||||
struct socfpga_reset_data {
|
||||
spinlock_t lock;
|
||||
@ -46,8 +47,8 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * NR_BANKS));
|
||||
writel(reg | BIT(offset), data->membase + (bank * NR_BANKS));
|
||||
reg = readl(data->membase + (bank * BANK_INCREMENT));
|
||||
writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
@ -67,8 +68,8 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * NR_BANKS));
|
||||
writel(reg & ~BIT(offset), data->membase + (bank * NR_BANKS));
|
||||
reg = readl(data->membase + (bank * BANK_INCREMENT));
|
||||
writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
@ -84,7 +85,7 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
|
||||
int offset = id % BITS_PER_LONG;
|
||||
u32 reg;
|
||||
|
||||
reg = readl(data->membase + (bank * NR_BANKS));
|
||||
reg = readl(data->membase + (bank * BANK_INCREMENT));
|
||||
|
||||
return !(reg & BIT(offset));
|
||||
}
|
||||
|
||||
@ -34,15 +34,16 @@ static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
|
||||
struct sunxi_reset_data *data = container_of(rcdev,
|
||||
struct sunxi_reset_data,
|
||||
rcdev);
|
||||
int bank = id / BITS_PER_LONG;
|
||||
int offset = id % BITS_PER_LONG;
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * 4));
|
||||
writel(reg & ~BIT(offset), data->membase + (bank * 4));
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
writel(reg & ~BIT(offset), data->membase + (bank * reg_width));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
@ -55,15 +56,16 @@ static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
struct sunxi_reset_data *data = container_of(rcdev,
|
||||
struct sunxi_reset_data,
|
||||
rcdev);
|
||||
int bank = id / BITS_PER_LONG;
|
||||
int offset = id % BITS_PER_LONG;
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * 4));
|
||||
writel(reg | BIT(offset), data->membase + (bank * 4));
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
writel(reg | BIT(offset), data->membase + (bank * reg_width));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
|
||||
@ -65,12 +65,12 @@ struct uniphier_reset_data {
|
||||
#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
|
||||
UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
|
||||
|
||||
const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
|
||||
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
|
||||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
|
||||
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
|
||||
UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
|
||||
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
|
||||
@ -78,7 +78,7 @@ const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
|
||||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
|
||||
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
|
||||
UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
|
||||
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
|
||||
@ -86,7 +86,7 @@ const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
|
||||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
|
||||
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
|
||||
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
|
||||
UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
|
||||
@ -100,12 +100,12 @@ const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
|
||||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
|
||||
UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
|
||||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
|
||||
UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
|
||||
UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
|
||||
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
|
||||
@ -134,7 +134,7 @@ const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
|
||||
#define UNIPHIER_MIO_RESET_DMAC(id) \
|
||||
UNIPHIER_RESETX((id), 0x110, 17)
|
||||
|
||||
const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
|
||||
UNIPHIER_MIO_RESET_SD(0, 0),
|
||||
UNIPHIER_MIO_RESET_SD(1, 1),
|
||||
UNIPHIER_MIO_RESET_SD(2, 2),
|
||||
@ -154,7 +154,7 @@ const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
|
||||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
|
||||
UNIPHIER_MIO_RESET_SD(0, 0),
|
||||
UNIPHIER_MIO_RESET_SD(1, 1),
|
||||
UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
|
||||
@ -171,7 +171,7 @@ const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
|
||||
#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
|
||||
UNIPHIER_RESETX((id), 0x114, 24 + (ch))
|
||||
|
||||
const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
|
||||
UNIPHIER_PERI_RESET_UART(0, 0),
|
||||
UNIPHIER_PERI_RESET_UART(1, 1),
|
||||
UNIPHIER_PERI_RESET_UART(2, 2),
|
||||
@ -184,7 +184,7 @@ const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
|
||||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
|
||||
static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
|
||||
UNIPHIER_PERI_RESET_UART(0, 0),
|
||||
UNIPHIER_PERI_RESET_UART(1, 1),
|
||||
UNIPHIER_PERI_RESET_UART(2, 2),
|
||||
|
||||
33
include/dt-bindings/reset/altr,rst-mgr-a10sr.h
Normal file
33
include/dt-bindings/reset/altr,rst-mgr-a10sr.h
Normal file
@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright Intel Corporation (C) 2017. All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Reset binding definitions for Altera Arria10 MAX5 System Resource Chip
|
||||
*
|
||||
* Adapted from altr,rst-mgr-a10.h
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
|
||||
#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
|
||||
|
||||
/* Peripheral PHY resets */
|
||||
#define A10SR_RESET_ENET_HPS 0
|
||||
#define A10SR_RESET_PCIE 1
|
||||
#define A10SR_RESET_FILE 2
|
||||
#define A10SR_RESET_BQSPI 3
|
||||
#define A10SR_RESET_USB 4
|
||||
|
||||
#define A10SR_RESET_NUM 5
|
||||
|
||||
#endif
|
||||
62
include/dt-bindings/reset/imx7-reset.h
Normal file
62
include/dt-bindings/reset/imx7-reset.h
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Impinj, Inc.
|
||||
*
|
||||
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDING_RESET_IMX7_H
|
||||
#define DT_BINDING_RESET_IMX7_H
|
||||
|
||||
#define IMX7_RESET_A7_CORE_POR_RESET0 0
|
||||
#define IMX7_RESET_A7_CORE_POR_RESET1 1
|
||||
#define IMX7_RESET_A7_CORE_RESET0 2
|
||||
#define IMX7_RESET_A7_CORE_RESET1 3
|
||||
#define IMX7_RESET_A7_DBG_RESET0 4
|
||||
#define IMX7_RESET_A7_DBG_RESET1 5
|
||||
#define IMX7_RESET_A7_ETM_RESET0 6
|
||||
#define IMX7_RESET_A7_ETM_RESET1 7
|
||||
#define IMX7_RESET_A7_SOC_DBG_RESET 8
|
||||
#define IMX7_RESET_A7_L2RESET 9
|
||||
#define IMX7_RESET_SW_M4C_RST 10
|
||||
#define IMX7_RESET_SW_M4P_RST 11
|
||||
#define IMX7_RESET_EIM_RST 12
|
||||
#define IMX7_RESET_HSICPHY_PORT_RST 13
|
||||
#define IMX7_RESET_USBPHY1_POR 14
|
||||
#define IMX7_RESET_USBPHY1_PORT_RST 15
|
||||
#define IMX7_RESET_USBPHY2_POR 16
|
||||
#define IMX7_RESET_USBPHY2_PORT_RST 17
|
||||
#define IMX7_RESET_MIPI_PHY_MRST 18
|
||||
#define IMX7_RESET_MIPI_PHY_SRST 19
|
||||
|
||||
/*
|
||||
* IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
|
||||
* and PCIEPHY_G_RST
|
||||
*/
|
||||
#define IMX7_RESET_PCIEPHY 20
|
||||
#define IMX7_RESET_PCIEPHY_PERST 21
|
||||
|
||||
/*
|
||||
* IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
|
||||
* can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
|
||||
* of as one
|
||||
*/
|
||||
#define IMX7_RESET_PCIE_CTRL_APPS_EN 22
|
||||
#define IMX7_RESET_DDRC_PRST 23
|
||||
#define IMX7_RESET_DDRC_CORE_RST 24
|
||||
|
||||
#define IMX7_RESET_NUM 25
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user