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https://mirrors.bfsu.edu.cn/git/linux.git
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ARC: [plat-hsdk] initial port for HSDK board
This initial port adds support of ARC HS Development Kit board with some basic features such serial port, USB, SD/MMC and Ethernet. Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and heavily use IO Coherency for speeding-up DMA-aware peripherals. Note as opposed to other ARC boards we link Linux kernel to 0x9000_0000 intentionally because cores 1 and 3 configured with DCCM situated at our more usual link base 0x8000_0000. We still can use memory region starting at 0x8000_0000 as we reallocate DCCM in our platform code. Note that PAE remapping for DMA clients does not work due to an RTL bug, so CREG_PAE register must be programmed to all zeroes, otherwise it will cause problems with DMA to/from peripherals even if PAE40 is not used. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Alexey Brodkin
Vineet Gupta
parent
9ed68785f7
commit
a518d63777
7
Documentation/devicetree/bindings/arc/hsdk.txt
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7
Documentation/devicetree/bindings/arc/hsdk.txt
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@ -0,0 +1,7 @@
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Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
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---------------------------------------------------------------------------
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ARC HSDK Board with quad-core ARC HS38x4 in silicon.
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Required root node properties:
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- compatible = "snps,hsdk";
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@ -100,6 +100,7 @@ source "arch/arc/plat-tb10x/Kconfig"
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source "arch/arc/plat-axs10x/Kconfig"
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#New platform adds here
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source "arch/arc/plat-eznps/Kconfig"
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source "arch/arc/plat-hsdk/Kconfig"
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endmenu
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@ -111,6 +111,7 @@ core-y += arch/arc/plat-sim/
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core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
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core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
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core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/
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core-$(CONFIG_ARC_SOC_HSDK) += arch/arc/plat-hsdk/
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ifdef CONFIG_ARC_PLAT_EZNPS
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KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include
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189
arch/arc/boot/dts/hsdk.dts
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189
arch/arc/boot/dts/hsdk.dts
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@ -0,0 +1,189 @@
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/*
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* Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Device Tree for ARC HS Development Kit
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*/
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/dts-v1/;
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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model = "snps,hsdk";
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compatible = "snps,hsdk";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <0>;
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clocks = <&core_clk>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <1>;
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clocks = <&core_clk>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <2>;
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clocks = <&core_clk>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <3>;
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clocks = <&core_clk>;
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};
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};
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core_clk: core-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <500000000>;
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};
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cpu_intc: cpu-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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};
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arcpct: pct {
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compatible = "snps,archs-pct";
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};
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/* TIMER0 with interrupt for clockevent */
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timer {
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compatible = "snps,arc-timer";
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interrupts = <16>;
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interrupt-parent = <&cpu_intc>;
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clocks = <&core_clk>;
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};
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/* 64-bit Global Free Running Counter */
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gfrc {
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compatible = "snps,archs-timer-gfrc";
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clocks = <&core_clk>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&idu_intc>;
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ranges = <0x00000000 0xf0000000 0x10000000>;
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serial: serial@5000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x5000 0x100>;
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clock-frequency = <33330000>;
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interrupts = <6>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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gmacclk: gmacclk {
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compatible = "fixed-clock";
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clock-frequency = <400000000>;
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#clock-cells = <0>;
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};
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mmcclk_ciu: mmcclk-ciu {
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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#clock-cells = <0>;
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};
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mmcclk_biu: mmcclk-biu {
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compatible = "fixed-clock";
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clock-frequency = <400000000>;
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#clock-cells = <0>;
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};
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ethernet@8000 {
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#interrupt-cells = <1>;
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compatible = "snps,dwmac";
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reg = <0x8000 0x2000>;
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interrupts = <10>;
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interrupt-names = "macirq";
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phy-mode = "rgmii";
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snps,pbl = <32>;
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clocks = <&gmacclk>;
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clock-names = "stmmaceth";
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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};
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ohci@60000 {
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compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
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reg = <0x60000 0x100>;
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interrupts = <15>;
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};
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ehci@40000 {
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compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
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reg = <0x40000 0x100>;
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interrupts = <15>;
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};
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mmc@a000 {
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compatible = "altr,socfpga-dw-mshc";
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reg = <0xa000 0x400>;
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num-slots = <1>;
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fifo-depth = <16>;
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card-detect-delay = <200>;
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clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
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clock-names = "biu", "ciu";
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interrupts = <12>;
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bus-width = <4>;
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};
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};
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memory@80000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "memory";
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reg = <0x80000000 0x40000000>; /* 1 GiB */
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};
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};
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80
arch/arc/configs/hsdk_defconfig
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80
arch/arc/configs/hsdk_defconfig
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@ -0,0 +1,80 @@
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CONFIG_DEFAULT_HOSTNAME="ARCLinux"
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CONFIG_SYSVIPC=y
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# CONFIG_CROSS_MEMORY_ATTACH is not set
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CONFIG_NO_HZ_IDLE=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_NAMESPACES=y
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# CONFIG_UTS_NS is not set
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# CONFIG_PID_NS is not set
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/"
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CONFIG_EMBEDDED=y
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CONFIG_PERF_EVENTS=y
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# CONFIG_VM_EVENT_COUNTERS is not set
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# CONFIG_COMPAT_BRK is not set
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CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_ARC_SOC_HSDK=y
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CONFIG_ISA_ARCV2=y
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CONFIG_SMP=y
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CONFIG_LINUX_LINK_BASE=0x90000000
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CONFIG_LINUX_RAM_BASE=0x80000000
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CONFIG_ARC_BUILTIN_DTB_NAME="hsdk"
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CONFIG_PREEMPT=y
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# CONFIG_COMPACTION is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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CONFIG_DEVTMPFS=y
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# CONFIG_STANDALONE is not set
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# CONFIG_PREVENT_FIRMWARE_BUILD is not set
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# CONFIG_FIRMWARE_IN_KERNEL is not set
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_NETDEVICES=y
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CONFIG_STMMAC_ETH=y
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CONFIG_MICREL_PHY=y
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CONFIG_INPUT_EVDEV=y
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_DW=y
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CONFIG_SERIAL_OF_PLATFORM=y
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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CONFIG_FB=y
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CONFIG_FB_UDL=y
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CONFIG_FRAMEBUFFER_CONSOLE=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_HCD_PLATFORM=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_HCD_PLATFORM=y
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CONFIG_USB_STORAGE=y
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CONFIG_MMC=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MMC_DW=y
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# CONFIG_IOMMU_SUPPORT is not set
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CONFIG_EXT3_FS=y
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CONFIG_VFAT_FS=y
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CONFIG_TMPFS=y
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CONFIG_NFS_FS=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ISO8859_1=y
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# CONFIG_ENABLE_WARN_DEPRECATED is not set
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# CONFIG_ENABLE_MUST_CHECK is not set
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CONFIG_STRIP_ASM_SYMS=y
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CONFIG_LOCKUP_DETECTOR=y
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CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
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# CONFIG_SCHED_DEBUG is not set
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# CONFIG_DEBUG_PREEMPT is not set
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# CONFIG_FTRACE is not set
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CONFIG_CRYPTO_ECHAINIV=y
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@ -29,8 +29,9 @@ static void __init arc_set_early_base_baud(unsigned long dt_root)
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{
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if (of_flat_dt_is_compatible(dt_root, "abilis,arc-tb10x"))
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arc_base_baud = 166666666; /* Fixed 166.6MHz clk (TB10x) */
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else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp"))
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arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x) */
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else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp") ||
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of_flat_dt_is_compatible(dt_root, "snps,hsdk"))
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arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x & HSDK) */
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else if (of_flat_dt_is_compatible(dt_root, "ezchip,arc-nps"))
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arc_base_baud = 800000000; /* Fixed 800MHz clk (NPS) */
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else
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9
arch/arc/plat-hsdk/Kconfig
Normal file
9
arch/arc/plat-hsdk/Kconfig
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@ -0,0 +1,9 @@
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# Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 as
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# published by the Free Software Foundation.
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#
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menuconfig ARC_SOC_HSDK
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bool "ARC HS Development Kit SOC"
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9
arch/arc/plat-hsdk/Makefile
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9
arch/arc/plat-hsdk/Makefile
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@ -0,0 +1,9 @@
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#
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# Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 as
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# published by the Free Software Foundation.
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#
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obj-y := platform.o
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66
arch/arc/plat-hsdk/platform.c
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66
arch/arc/plat-hsdk/platform.c
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@ -0,0 +1,66 @@
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/*
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* ARC HSDK Platform support code
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*
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* Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/arcregs.h>
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#include <asm/io.h>
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#include <asm/mach_desc.h>
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#define ARC_CCM_UNUSED_ADDR 0x60000000
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static void __init hsdk_init_per_cpu(unsigned int cpu)
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{
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/*
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* By default ICCM is mapped to 0x7z while this area is used for
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* kernel virtual mappings, so move it to currently unused area.
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*/
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if (cpuinfo_arc700[cpu].iccm.sz)
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write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
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/*
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* By default DCCM is mapped to 0x8z while this area is used by kernel,
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* so move it to currently unused area.
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*/
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if (cpuinfo_arc700[cpu].dccm.sz)
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write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
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}
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#define ARC_PERIPHERAL_BASE 0xf0000000
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#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
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#define CREG_PAE (CREG_BASE + 0x180)
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#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
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static void __init hsdk_init_early(void)
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{
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/*
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* PAE remapping for DMA clients does not work due to an RTL bug, so
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* CREG_PAE register must be programmed to all zeroes, otherwise it
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* will cause problems with DMA to/from peripherals even if PAE40 is
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* not used.
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*/
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/* Default is 1, which means "PAE offset = 4GByte" */
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writel_relaxed(0, (void __iomem *) CREG_PAE);
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/* Really apply settings made above */
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writel(1, (void __iomem *) CREG_PAE_UPDATE);
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}
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static const char *hsdk_compat[] __initconst = {
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"snps,hsdk",
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NULL,
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};
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MACHINE_START(SIMULATION, "hsdk")
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.dt_compat = hsdk_compat,
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.init_early = hsdk_init_early,
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.init_per_cpu = hsdk_init_per_cpu,
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MACHINE_END
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