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net: ethernet: aquantia: PCI operations
Add functions that handle the PCI bus interface. Signed-off-by: Alexander Loktionov <Alexander.Loktionov@aquantia.com> Signed-off-by: Dmitrii Tarakanov <Dmitrii.Tarakanov@aquantia.com> Signed-off-by: Pavel Belous <Pavel.Belous@aquantia.com> Signed-off-by: Dmitry Bezrukov <Dmitry.Bezrukov@aquantia.com> Signed-off-by: David M. VomLehn <vomlehn@texas.net> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
970a2e9864
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345
drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
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345
drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
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@ -0,0 +1,345 @@
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/*
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* aQuantia Corporation Network Driver
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* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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/* File aq_pci_func.c: Definition of PCI functions. */
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#include "aq_pci_func.h"
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#include "aq_nic.h"
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#include "aq_vec.h"
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#include "aq_hw.h"
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#include <linux/interrupt.h>
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struct aq_pci_func_s {
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struct pci_dev *pdev;
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struct aq_nic_s *port[AQ_CFG_PCI_FUNC_PORTS];
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void __iomem *mmio;
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void *aq_vec[AQ_CFG_PCI_FUNC_MSIX_IRQS];
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resource_size_t mmio_pa;
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unsigned int msix_entry_mask;
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unsigned int irq_type;
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unsigned int ports;
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bool is_pci_enabled;
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bool is_regions;
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bool is_pci_using_dac;
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struct aq_hw_caps_s aq_hw_caps;
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struct msix_entry msix_entry[AQ_CFG_PCI_FUNC_MSIX_IRQS];
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};
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struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *aq_hw_ops,
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struct pci_dev *pdev,
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const struct net_device_ops *ndev_ops,
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const struct ethtool_ops *eth_ops)
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{
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struct aq_pci_func_s *self = NULL;
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int err = 0;
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unsigned int port = 0U;
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if (!aq_hw_ops) {
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err = -EFAULT;
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goto err_exit;
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}
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self = kzalloc(sizeof(*self), GFP_KERNEL);
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if (!self) {
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err = -ENOMEM;
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goto err_exit;
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}
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pci_set_drvdata(pdev, self);
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self->pdev = pdev;
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err = aq_hw_ops->get_hw_caps(NULL, &self->aq_hw_caps);
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if (err < 0)
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goto err_exit;
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self->ports = self->aq_hw_caps.ports;
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for (port = 0; port < self->ports; ++port) {
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struct aq_nic_s *aq_nic = aq_nic_alloc_cold(ndev_ops, eth_ops,
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&pdev->dev, self,
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port, aq_hw_ops);
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if (!aq_nic) {
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err = -ENOMEM;
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goto err_exit;
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}
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self->port[port] = aq_nic;
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}
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err_exit:
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if (err < 0) {
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if (self)
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aq_pci_func_free(self);
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self = NULL;
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}
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(void)err;
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return self;
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}
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int aq_pci_func_init(struct aq_pci_func_s *self)
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{
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int err = 0;
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unsigned int bar = 0U;
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unsigned int port = 0U;
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unsigned int i = 0U;
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err = pci_enable_device(self->pdev);
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if (err < 0)
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goto err_exit;
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self->is_pci_enabled = true;
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err = pci_set_dma_mask(self->pdev, DMA_BIT_MASK(64));
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if (!err) {
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err = pci_set_consistent_dma_mask(self->pdev, DMA_BIT_MASK(64));
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self->is_pci_using_dac = 1;
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}
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if (err) {
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err = pci_set_dma_mask(self->pdev, DMA_BIT_MASK(32));
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if (!err)
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err = pci_set_consistent_dma_mask(self->pdev,
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DMA_BIT_MASK(32));
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self->is_pci_using_dac = 0;
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}
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if (err != 0) {
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err = -ENOSR;
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goto err_exit;
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}
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err = pci_request_regions(self->pdev, AQ_CFG_DRV_NAME "_mmio");
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if (err < 0)
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goto err_exit;
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self->is_regions = true;
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pci_set_master(self->pdev);
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for (bar = 0; bar < 4; ++bar) {
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if (IORESOURCE_MEM & pci_resource_flags(self->pdev, bar)) {
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resource_size_t reg_sz;
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self->mmio_pa = pci_resource_start(self->pdev, bar);
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if (self->mmio_pa == 0U) {
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err = -EIO;
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goto err_exit;
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}
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reg_sz = pci_resource_len(self->pdev, bar);
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if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
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err = -EIO;
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goto err_exit;
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}
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self->mmio = ioremap_nocache(self->mmio_pa, reg_sz);
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if (!self->mmio) {
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err = -EIO;
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goto err_exit;
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}
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break;
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}
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}
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if (err < 0)
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goto err_exit;
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for (i = 0; i < self->aq_hw_caps.msix_irqs; i++)
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self->msix_entry[i].entry = i;
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/*enable interrupts */
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#if AQ_CFG_FORCE_LEGACY_INT
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self->irq_type = AQ_HW_IRQ_LEGACY;
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#else
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err = pci_enable_msix(self->pdev, self->msix_entry,
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self->aq_hw_caps.msix_irqs);
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if (err >= 0) {
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self->irq_type = AQ_HW_IRQ_MSIX;
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} else {
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err = pci_enable_msi(self->pdev);
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if (err >= 0) {
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self->irq_type = AQ_HW_IRQ_MSI;
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} else {
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self->irq_type = AQ_HW_IRQ_LEGACY;
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err = 0;
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}
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}
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#endif
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/* net device init */
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for (port = 0; port < self->ports; ++port) {
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if (!self->port[port])
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continue;
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err = aq_nic_cfg_start(self->port[port]);
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if (err < 0)
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goto err_exit;
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err = aq_nic_ndev_init(self->port[port]);
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if (err < 0)
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goto err_exit;
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err = aq_nic_ndev_register(self->port[port]);
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if (err < 0)
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goto err_exit;
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}
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err_exit:
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if (err < 0)
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aq_pci_func_deinit(self);
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return err;
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}
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int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
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char *name, void *aq_vec, cpumask_t *affinity_mask)
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{
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int err = 0;
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switch (self->irq_type) {
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case AQ_HW_IRQ_MSIX:
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err = request_irq(self->msix_entry[i].vector, aq_vec_isr, 0,
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name, aq_vec);
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break;
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case AQ_HW_IRQ_MSI:
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err = request_irq(self->pdev->irq, aq_vec_isr, 0, name, aq_vec);
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break;
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case AQ_HW_IRQ_LEGACY:
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err = request_irq(self->pdev->irq, aq_vec_isr_legacy,
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IRQF_SHARED, name, aq_vec);
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break;
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default:
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err = -EFAULT;
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break;
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}
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if (err >= 0) {
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self->msix_entry_mask |= (1 << i);
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self->aq_vec[i] = aq_vec;
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if (self->irq_type == AQ_HW_IRQ_MSIX)
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irq_set_affinity_hint(self->msix_entry[i].vector,
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affinity_mask);
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}
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return err;
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}
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void aq_pci_func_free_irqs(struct aq_pci_func_s *self)
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{
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unsigned int i = 0U;
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for (i = 32U; i--;) {
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if (!((1U << i) & self->msix_entry_mask))
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continue;
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switch (self->irq_type) {
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case AQ_HW_IRQ_MSIX:
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irq_set_affinity_hint(self->msix_entry[i].vector, NULL);
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free_irq(self->msix_entry[i].vector, self->aq_vec[i]);
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break;
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case AQ_HW_IRQ_MSI:
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free_irq(self->pdev->irq, self->aq_vec[i]);
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break;
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case AQ_HW_IRQ_LEGACY:
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free_irq(self->pdev->irq, self->aq_vec[i]);
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break;
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default:
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break;
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}
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self->msix_entry_mask &= ~(1U << i);
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}
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}
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void __iomem *aq_pci_func_get_mmio(struct aq_pci_func_s *self)
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{
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return self->mmio;
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}
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unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self)
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{
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return self->irq_type;
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}
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void aq_pci_func_deinit(struct aq_pci_func_s *self)
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{
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if (!self)
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goto err_exit;
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aq_pci_func_free_irqs(self);
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switch (self->irq_type) {
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case AQ_HW_IRQ_MSI:
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pci_disable_msi(self->pdev);
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break;
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case AQ_HW_IRQ_MSIX:
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pci_disable_msix(self->pdev);
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break;
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case AQ_HW_IRQ_LEGACY:
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break;
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default:
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break;
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}
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if (self->is_regions)
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pci_release_regions(self->pdev);
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if (self->is_pci_enabled)
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pci_disable_device(self->pdev);
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err_exit:;
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}
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void aq_pci_func_free(struct aq_pci_func_s *self)
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{
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unsigned int port = 0U;
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if (!self)
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goto err_exit;
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for (port = 0; port < self->ports; ++port) {
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if (!self->port[port])
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continue;
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aq_nic_ndev_free(self->port[port]);
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}
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kfree(self);
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err_exit:;
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}
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int aq_pci_func_change_pm_state(struct aq_pci_func_s *self,
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pm_message_t *pm_msg)
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{
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int err = 0;
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unsigned int port = 0U;
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if (!self) {
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err = -EFAULT;
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goto err_exit;
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}
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for (port = 0; port < self->ports; ++port) {
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if (!self->port[port])
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continue;
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(void)aq_nic_change_pm_state(self->port[port], pm_msg);
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}
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err_exit:
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return err;
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}
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34
drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
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34
drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
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@ -0,0 +1,34 @@
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/*
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* aQuantia Corporation Network Driver
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* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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/* File aq_pci_func.h: Declaration of PCI functions. */
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#ifndef AQ_PCI_FUNC_H
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#define AQ_PCI_FUNC_H
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#include "aq_common.h"
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struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *hw_ops,
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struct pci_dev *pdev,
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const struct net_device_ops *ndev_ops,
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const struct ethtool_ops *eth_ops);
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int aq_pci_func_init(struct aq_pci_func_s *self);
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int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
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char *name, void *aq_vec,
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cpumask_t *affinity_mask);
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void aq_pci_func_free_irqs(struct aq_pci_func_s *self);
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int aq_pci_func_start(struct aq_pci_func_s *self);
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void __iomem *aq_pci_func_get_mmio(struct aq_pci_func_s *self);
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unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self);
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void aq_pci_func_deinit(struct aq_pci_func_s *self);
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void aq_pci_func_free(struct aq_pci_func_s *self);
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int aq_pci_func_change_pm_state(struct aq_pci_func_s *self,
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pm_message_t *pm_msg);
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#endif /* AQ_PCI_FUNC_H */
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