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staging/atomisp: Add support for the Intel IPU v2

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This patch adds support for the Intel IPU v2 as found on Android and IoT
Baytrail-T and Baytrail-CR platforms (those with the IPU PCI mapped). You
will also need the firmware files from your device (Android usually puts
them into /etc) - or you can find them in the downloadable restore/upgrade
kits if you blew them away for some reason.

It may be possible to extend the driver to handle the BYT/T windows
platforms such as the ASUS T100TA. These platforms don't expose the IPU via
the PCI interface but via ACPI buried in the GPU description and with the
camera information somewhere unknown so would need a platform driver
interface adding to the codebase *IFF* the firmware works on such devices.

To get good results you also need a suitable support library such as
libxcam. The camera is intended to be driven from Android so it has a lot of
features that many desktop apps don't fully spport.

In theory all the pieces are there to build it with -DISP2401 and some
differing files to get CherryTrail/T support, but unifying the drivers
properlly is a work in progress.

The IPU driver represents the work of a lot of people within Intel over many
years. It's historical goal was portability rather than Linux upstream. Any
queries about the upstream aimed driver should be sent to me not to the
original authors.

Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alan Cox 2017-02-17 16:55:17 +00:00 committed by Greg Kroah-Hartman
parent 372499b589
commit a49d25364d
920 changed files with 204645 additions and 0 deletions
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1
drivers/staging/media/Kconfig
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@ -34,4 +34,5 @@ source "drivers/staging/media/lirc/Kconfig"
source "drivers/staging/media/st-cec/Kconfig"
source "drivers/staging/media/atomisp/Kconfig"
endif

1
drivers/staging/media/Makefile
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@ -5,3 +5,4 @@ obj-$(CONFIG_LIRC_STAGING) += lirc/
obj-$(CONFIG_VIDEO_DM365_VPFE) += davinci_vpfe/
obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
obj-$(CONFIG_VIDEO_STI_HDMI_CEC) += st-cec/
obj-$(CONFIG_INTEL_ATOMISP) += atomisp/

11
drivers/staging/media/atomisp/Kconfig Normal file
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@ -0,0 +1,11 @@
menuconfig INTEL_ATOMISP
bool "Enable support to Intel MIPI camera drivers"
depends on X86
help
Enable support for the Intel ISP2 camera interfaces and MIPI
sensor drivers.
if INTEL_ATOMISP
source "drivers/staging/media/atomisp/pci/Kconfig"
source "drivers/staging/media/atomisp/i2c/Kconfig"
endif

8
drivers/staging/media/atomisp/Makefile Normal file
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@ -0,0 +1,8 @@
#
# Makefile for camera drivers.
#
obj-$(CONFIG_INTEL_ATOMISP) += pci/
obj-$(CONFIG_INTEL_ATOMISP) += i2c/
obj-$(CONFIG_INTEL_ATOMISP) += platform/
LINUXINCLUDE += -I drivers/staging/media/atomisp/include/

64
drivers/staging/media/atomisp/TODO Normal file
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@ -0,0 +1,64 @@
1. A single AtomISP driver needs to be implemented to support both BYT and
CHT platforms. The current driver is a mechanical and hand combined merge
of the two using an ifdef ISP2401 to select the CHT version, which at the
moment is not enabled. Eventually this should become a runtime if check,
but there are some quite tricky things that need sorting out before that
will be possible.
2. The file structure needs to get tidied up to resemble a normal Linux
driver.
3. Lots of the midlayer glue. unused code and abstraction needs removing.
3. The sensor drivers read MIPI settings from EFI variables or default to the
settings hard-coded in the platform data file for different platforms.
This isn't ideal but may be hard to improve as this is how existing
platforms work.
4. The sensor drivers use the regulator framework API. In the ideal world it
would be using ACPI but that's not how the existing devices work.
5. The AtomISP driver includes some special IOCTLS (ATOMISP_IOC_XXXX_XXXX)
that may need some cleaning up.
6. Correct Coding Style. Please don't send coding style patches for this
driver until the other work is done.
7. The ISP code depends on the exact FW version. The version defined in
BYT:
drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.c
static const char *release_version = STR(irci_stable_candrpv_0415_20150521_0458);
CHT:
drivers/staging/media/atomisp/pci/atomisp2/css/sh_css_firmware.c
static const char *release_version = STR(irci_ecr-master_20150911_0724);
At some point we may need to round up a few driver versions and see if
there are any specific things that can be done to fold in support for
multiple firmware versions.
Limitations:
1. Currently the patch only support some camera sensors
gc2235/gc0310/0v2680/ov2722/ov5693/mt9m114...
2. To test the patches, you also need the ISP firmware
for BYT:/lib/firmware/shisp_2400b0_v21.bin
for CHT:/lib/firmware/shisp_2401a0_v21.bin
The firmware files will usually be found in /etc/firmware on an Android
device but can also be extracted from the upgrade kit if you've managed
to lose them somehow.
3. Without a 3A libary the capture behaviour is not very good. To take a good
picture, you need tune ISP parameters by IOCTL functions or use a 3A libary
such as libxcam.
4. The driver is intended to drive the PCI exposed versions of the device.
It will not detect those devices enumerated via ACPI as a field of the
i915 GPU driver.
5. The driver supports only v2 of the IPU/Camera. It will not work with the
versions of the hardware in other SoCs.

105
drivers/staging/media/atomisp/i2c/Kconfig Normal file
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@ -0,0 +1,105 @@
#
# Kconfig for sensor drivers
#
source "drivers/staging/media/atomisp/i2c/ov5693/Kconfig"
source "drivers/staging/media/atomisp/i2c/imx/Kconfig"
config VIDEO_OV2722
tristate "OVT ov2722 sensor support"
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the OVT
OV2722 raw camera.
OVT is a 2M raw sensor.
It currently only works with the atomisp driver.
config VIDEO_GC2235
tristate "Galaxy gc2235 sensor support"
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the OVT
GC2235 raw camera.
GC2235 is a 2M raw sensor.
It currently only works with the atomisp driver.
config VIDEO_OV8858
tristate "Omnivision ov8858 sensor support"
depends on I2C && VIDEO_V4L2 && VIDEO_ATOMISP
---help---
This is a Video4Linux2 sensor-level driver for the Omnivision
ov8858 RAW sensor.
OV8858 is a 8M raw sensor.
It currently only works with the atomisp driver.
config VIDEO_MSRLIST_HELPER
tristate "Helper library to load, parse and apply large register lists."
depends on I2C
---help---
This is a helper library to be used from a sensor driver to load, parse
and apply large register lists.
To compile this driver as a module, choose M here: the
module will be called libmsrlisthelper.
config VIDEO_MT9M114
tristate "Aptina mt9m114 sensor support"
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the Micron
mt9m114 1.3 Mpixel camera.
mt9m114 is video camera sensor.
It currently only works with the atomisp driver.
config VIDEO_AP1302
tristate "AP1302 external ISP support"
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the external
ISP AP1302.
AP1302 is an exteral ISP.
It currently only works with the atomisp driver.
config VIDEO_GC0310
tristate "GC0310 sensor support"
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the Galaxycore
GC0310 0.3MP sensor.
config VIDEO_OV2680
tristate "Omnivision OV2680 sensor support"
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the Omnivision
OV2680 raw camera.
ov2680 is a 2M raw sensor.
It currently only works with the atomisp driver.
#
# Kconfig for flash drivers
#
config VIDEO_LM3554
tristate "LM3554 flash light driver"
depends on VIDEO_V4L2 && I2C
---help---
This is a Video4Linux2 sub-dev driver for the LM3554
flash light driver.
To compile this driver as a module, choose M here: the
module will be called lm3554

23
drivers/staging/media/atomisp/i2c/Makefile Normal file
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@ -0,0 +1,23 @@
#
# Makefile for sensor drivers
#
obj-$(CONFIG_VIDEO_IMX) += imx/
obj-$(CONFIG_VIDEO_OV5693) += ov5693/
obj-$(CONFIG_VIDEO_MT9M114) += mt9m114.o
obj-$(CONFIG_VIDEO_GC2235) += gc2235.o
obj-$(CONFIG_VIDEO_OV2722) += ov2722.o
obj-$(CONFIG_VIDEO_OV2680) += ov2680.o
obj-$(CONFIG_VIDEO_GC0310) += gc0310.o
obj-$(CONFIG_VIDEO_MSRLIST_HELPER) += libmsrlisthelper.o
obj-$(CONFIG_VIDEO_AP1302) += ap1302.o
# Makefile for flash drivers
#
obj-$(CONFIG_VIDEO_LM3554) += lm3554.o
ccflags-y += -Werror

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drivers/staging/media/atomisp/i2c/ap1302.c Normal file
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198
drivers/staging/media/atomisp/i2c/ap1302.h Normal file
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@ -0,0 +1,198 @@
/*
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __AP1302_H__
#define __AP1302_H__
#include <linux/atomisp_platform.h>
#include <linux/regmap.h>
#include <linux/types.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
#define AP1302_NAME "ap1302"
#define AP1302_CHIP_ID 0x265
#define AP1302_I2C_MAX_LEN 65534
#define AP1302_FW_WINDOW_OFFSET 0x8000
#define AP1302_FW_WINDOW_SIZE 0x2000
#define AP1302_REG16 2
#define AP1302_REG32 4
#define REG_CHIP_VERSION 0x0000
#define REG_CHIP_REV 0x0050
#define REG_MF_ID 0x0004
#define REG_ERROR 0x0006
#define REG_CTRL 0x1000
#define REG_DZ_TGT_FCT 0x1010
#define REG_SFX_MODE 0x1016
#define REG_SS_HEAD_PT0 0x1174
#define REG_AE_BV_OFF 0x5014
#define REG_AE_BV_BIAS 0x5016
#define REG_AWB_CTRL 0x5100
#define REG_FLICK_CTRL 0x5440
#define REG_SCENE_CTRL 0x5454
#define REG_BOOTDATA_STAGE 0x6002
#define REG_SENSOR_SELECT 0x600C
#define REG_SYS_START 0x601A
#define REG_SIP_CRC 0xF052
#define REG_PREVIEW_BASE 0x2000
#define REG_SNAPSHOT_BASE 0x3000
#define REG_VIDEO_BASE 0x4000
#define CNTX_WIDTH 0x00
#define CNTX_HEIGHT 0x02
#define CNTX_ROI_X0 0x04
#define CNTX_ROI_Y0 0x06
#define CNTX_ROI_X1 0x08
#define CNTX_ROI_Y1 0x0A
#define CNTX_ASPECT 0x0C
#define CNTX_LOCK 0x0E
#define CNTX_ENABLE 0x10
#define CNTX_OUT_FMT 0x12
#define CNTX_SENSOR_MODE 0x14
#define CNTX_MIPI_CTRL 0x16
#define CNTX_MIPI_II_CTRL 0x18
#define CNTX_LINE_TIME 0x1C
#define CNTX_MAX_FPS 0x20
#define CNTX_AE_USG 0x22
#define CNTX_AE_UPPER_ET 0x24
#define CNTX_AE_MAX_ET 0x28
#define CNTX_SS 0x2C
#define CNTX_S1_SENSOR_MODE 0x2E
#define CNTX_HINF_CTRL 0x30
#define CTRL_CNTX_MASK 0x03
#define CTRL_CNTX_OFFSET 0x00
#define HINF_CTRL_LANE_MASK 0x07
#define HINF_CTRL_LANE_OFFSET 0x00
#define MIPI_CTRL_IMGVC_MASK 0xC0
#define MIPI_CTRL_IMGVC_OFFSET 0x06
#define MIPI_CTRL_IMGTYPE_AUTO 0x3F
#define MIPI_CTRL_SSVC_MASK 0xC000
#define MIPI_CTRL_SSVC_OFFSET 0x0E
#define MIPI_CTRL_SSTYPE_MASK 0x3F00
#define MIPI_CTRL_SSTYPE_OFFSET 0x08
#define OUT_FMT_IIS_MASK 0x30
#define OUT_FMT_IIS_OFFSET 0x08
#define OUT_FMT_SS_MASK 0x1000
#define OUT_FMT_SS_OFFSET 0x12
#define OUT_FMT_TYPE_MASK 0xFF
#define SENSOR_SELECT_MASK 0x03
#define SENSOR_SELECT_OFFSET 0x00
#define AWB_CTRL_MODE_MASK 0x0F
#define AWB_CTRL_MODE_OFFSET 0x00
#define AWB_CTRL_FLASH_MASK 0x100
#define AP1302_FMT_UYVY422 0x50
#define AP1302_SYS_ACTIVATE 0x8010
#define AP1302_SYS_SWITCH 0x8140
#define AP1302_SENSOR_PRI 0x01
#define AP1302_SENSOR_SEC 0x02
#define AP1302_SS_CTRL 0x31
#define AP1302_MAX_RATIO_MISMATCH 10 /* Unit in percentage */
#define AP1302_MAX_EV 2
#define AP1302_MIN_EV -2
enum ap1302_contexts {
CONTEXT_PREVIEW = 0,
CONTEXT_SNAPSHOT,
CONTEXT_VIDEO,
CONTEXT_NUM
};
/* The context registers are defined according to preview/video registers.
Preview and video context have the same register definition.
But snapshot context does not have register S1_SENSOR_MODE.
When setting snapshot registers, if the offset exceeds
S1_SENSOR_MODE, the actual offset needs to minus 2. */
struct ap1302_context_config {
u16 width;
u16 height;
u16 roi_x0;
u16 roi_y0;
u16 roi_x1;
u16 roi_y1;
u16 aspect_factor;
u16 lock;
u16 enable;
u16 out_fmt;
u16 sensor_mode;
u16 mipi_ctrl;
u16 mipi_ii_ctrl;
u16 padding;
u32 line_time;
u16 max_fps;
u16 ae_usg;
u32 ae_upper_et;
u32 ae_max_et;
u16 ss;
u16 s1_sensor_mode;
u16 hinf_ctrl;
u32 reserved;
};
struct ap1302_res_struct {
u16 width;
u16 height;
u16 fps;
};
struct ap1302_context_res {
s32 res_num;
s32 cur_res;
struct ap1302_res_struct *res_table;
};
struct ap1302_device {
struct v4l2_subdev sd;
struct media_pad pad;
struct camera_sensor_platform_data *platform_data;
const struct firmware *fw;
struct mutex input_lock; /* serialize sensor's ioctl */
struct v4l2_mbus_framefmt format;
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_ctrl *run_mode;
struct ap1302_context_config cntx_config[CONTEXT_NUM];
struct ap1302_context_res cntx_res[CONTEXT_NUM];
enum ap1302_contexts cur_context;
unsigned int num_lanes;
struct regmap *regmap16;
struct regmap *regmap32;
bool sys_activated;
bool power_on;
};
struct ap1302_firmware {
u32 crc;
u32 pll_init_size;
u32 total_size;
u32 reserved;
};
struct ap1302_context_info {
u16 offset;
u16 len;
char *name;
};
#endif

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drivers/staging/media/atomisp/i2c/gc0310.c Normal file
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459
drivers/staging/media/atomisp/i2c/gc0310.h Normal file
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/*
* Support for GalaxyCore GC0310 VGA camera sensor.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __GC0310_H__
#define __GC0310_H__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/spinlock.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <linux/v4l2-mediabus.h>
#include <media/media-entity.h>
#include <linux/atomisp_platform.h>
#define GC0310_NAME "gc0310"
/* Defines for register writes and register array processing */
#define I2C_MSG_LENGTH 1
#define I2C_RETRY_COUNT 5
#define GC0310_FOCAL_LENGTH_NUM 278 /*2.78mm*/
#define GC0310_FOCAL_LENGTH_DEM 100
#define GC0310_F_NUMBER_DEFAULT_NUM 26
#define GC0310_F_NUMBER_DEM 10
#define MAX_FMTS 1
/*
* focal length bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define GC0310_FOCAL_LENGTH_DEFAULT 0x1160064
/*
* current f-number bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define GC0310_F_NUMBER_DEFAULT 0x1a000a
/*
* f-number range bits definition:
* bits 31-24: max f-number numerator
* bits 23-16: max f-number denominator
* bits 15-8: min f-number numerator
* bits 7-0: min f-number denominator
*/
#define GC0310_F_NUMBER_RANGE 0x1a0a1a0a
#define GC0310_ID 0xa310
#define GC0310_RESET_RELATED 0xFE
#define GC0310_REGISTER_PAGE_0 0x0
#define GC0310_REGISTER_PAGE_3 0x3
#define GC0310_FINE_INTG_TIME_MIN 0
#define GC0310_FINE_INTG_TIME_MAX_MARGIN 0
#define GC0310_COARSE_INTG_TIME_MIN 1
#define GC0310_COARSE_INTG_TIME_MAX_MARGIN 6
/*
* GC0310 System control registers
*/
#define GC0310_SW_STREAM 0x10
#define GC0310_SC_CMMN_CHIP_ID_H 0xf0
#define GC0310_SC_CMMN_CHIP_ID_L 0xf1
#define GC0310_AEC_PK_EXPO_H 0x03
#define GC0310_AEC_PK_EXPO_L 0x04
#define GC0310_AGC_ADJ 0x48
#define GC0310_DGC_ADJ 0x71
#if 0
#define GC0310_GROUP_ACCESS 0x3208
#endif
#define GC0310_H_CROP_START_H 0x09
#define GC0310_H_CROP_START_L 0x0A
#define GC0310_V_CROP_START_H 0x0B
#define GC0310_V_CROP_START_L 0x0C
#define GC0310_H_OUTSIZE_H 0x0F
#define GC0310_H_OUTSIZE_L 0x10
#define GC0310_V_OUTSIZE_H 0x0D
#define GC0310_V_OUTSIZE_L 0x0E
#define GC0310_H_BLANKING_H 0x05
#define GC0310_H_BLANKING_L 0x06
#define GC0310_V_BLANKING_H 0x07
#define GC0310_V_BLANKING_L 0x08
#define GC0310_SH_DELAY 0x11
#define GC0310_START_STREAMING 0x94 /* 8-bit enable */
#define GC0310_STOP_STREAMING 0x0 /* 8-bit disable */
#define GC0310_BIN_FACTOR_MAX 3
struct regval_list {
u16 reg_num;
u8 value;
};
struct gc0310_resolution {
u8 *desc;
const struct gc0310_reg *regs;
int res;
int width;
int height;
int fps;
int pix_clk_freq;
u32 skip_frames;
u16 pixels_per_line;
u16 lines_per_frame;
u8 bin_factor_x;
u8 bin_factor_y;
u8 bin_mode;
bool used;
};
struct gc0310_format {
u8 *desc;
u32 pixelformat;
struct gc0310_reg *regs;
};
/*
* gc0310 device structure.
*/
struct gc0310_device {
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_mbus_framefmt format;
struct mutex input_lock;
struct v4l2_ctrl_handler ctrl_handler;
struct camera_sensor_platform_data *platform_data;
int vt_pix_clk_freq_mhz;
int fmt_idx;
int run_mode;
u8 res;
u8 type;
};
enum gc0310_tok_type {
GC0310_8BIT = 0x0001,
GC0310_TOK_TERM = 0xf000, /* terminating token for reg list */
GC0310_TOK_DELAY = 0xfe00, /* delay token for reg list */
GC0310_TOK_MASK = 0xfff0
};
/**
* struct gc0310_reg - MI sensor register format
* @type: type of the register
* @reg: 16-bit offset to register
* @val: 8/16/32-bit register value
*
* Define a structure for sensor register initialization values
*/
struct gc0310_reg {
enum gc0310_tok_type type;
u8 reg;
u8 val; /* @set value for read/mod/write, @mask */
};
#define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd)
#define GC0310_MAX_WRITE_BUF_SIZE 30
struct gc0310_write_buffer {
u8 addr;
u8 data[GC0310_MAX_WRITE_BUF_SIZE];
};
struct gc0310_write_ctrl {
int index;
struct gc0310_write_buffer buffer;
};
static const struct i2c_device_id gc0310_id[] = {
{GC0310_NAME, 0},
{}
};
/*
* Register settings for various resolution
*/
static const struct gc0310_reg gc0310_reset_register[] = {
/////////////////////////////////////////////////
///////////////// system reg /////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0xfe, 0xf0},
{GC0310_8BIT, 0xfe, 0xf0},
{GC0310_8BIT, 0xfe, 0x00},
{GC0310_8BIT, 0xfc, 0x0e}, //4e
{GC0310_8BIT, 0xfc, 0x0e}, //16//4e // [0]apwd [6]regf_clk_gate
{GC0310_8BIT, 0xf2, 0x80}, //sync output
{GC0310_8BIT, 0xf3, 0x00}, //1f//01 data output
{GC0310_8BIT, 0xf7, 0x33}, //f9
{GC0310_8BIT, 0xf8, 0x05}, //00
{GC0310_8BIT, 0xf9, 0x0e}, // 0x8e //0f
{GC0310_8BIT, 0xfa, 0x11},
/////////////////////////////////////////////////
/////////////////// MIPI ////////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0xfe, 0x03},
{GC0310_8BIT, 0x01, 0x03}, ///mipi 1lane
{GC0310_8BIT, 0x02, 0x22}, // 0x33
{GC0310_8BIT, 0x03, 0x94},
{GC0310_8BIT, 0x04, 0x01}, // fifo_prog
{GC0310_8BIT, 0x05, 0x00}, //fifo_prog
{GC0310_8BIT, 0x06, 0x80}, //b0 //YUV ISP data
{GC0310_8BIT, 0x11, 0x2a},//1e //LDI set YUV422
{GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] //
{GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
{GC0310_8BIT, 0x15, 0x12}, // 0x10 //DPHYY_MODE read_ready
{GC0310_8BIT, 0x17, 0x01},
{GC0310_8BIT, 0x40, 0x08},
{GC0310_8BIT, 0x41, 0x00},
{GC0310_8BIT, 0x42, 0x00},
{GC0310_8BIT, 0x43, 0x00},
{GC0310_8BIT, 0x21, 0x02}, // 0x01
{GC0310_8BIT, 0x22, 0x02}, // 0x01
{GC0310_8BIT, 0x23, 0x01}, // 0x05 //Nor:0x05 DOU:0x06
{GC0310_8BIT, 0x29, 0x00},
{GC0310_8BIT, 0x2A, 0x25}, // 0x05 //data zero 0x7a de
{GC0310_8BIT, 0x2B, 0x02},
{GC0310_8BIT, 0xfe, 0x00},
/////////////////////////////////////////////////
///////////////// CISCTL reg /////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0x00, 0x2f}, //2f//0f//02//01
{GC0310_8BIT, 0x01, 0x0f}, //06
{GC0310_8BIT, 0x02, 0x04},
{GC0310_8BIT, 0x4f, 0x00}, //AEC 0FF
{GC0310_8BIT, 0x03, 0x01}, // 0x03 //04
{GC0310_8BIT, 0x04, 0xc0}, // 0xe8 //58
{GC0310_8BIT, 0x05, 0x00},
{GC0310_8BIT, 0x06, 0xb2}, // 0x0a //HB
{GC0310_8BIT, 0x07, 0x00},
{GC0310_8BIT, 0x08, 0x0c}, // 0x89 //VB
{GC0310_8BIT, 0x09, 0x00}, //row start
{GC0310_8BIT, 0x0a, 0x00}, //
{GC0310_8BIT, 0x0b, 0x00}, //col start
{GC0310_8BIT, 0x0c, 0x00},
{GC0310_8BIT, 0x0d, 0x01}, //height
{GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
{GC0310_8BIT, 0x0f, 0x02}, //width
{GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
{GC0310_8BIT, 0x17, 0x14},
{GC0310_8BIT, 0x18, 0x1a}, //0a//[4]double reset
{GC0310_8BIT, 0x19, 0x14}, //AD pipeline
{GC0310_8BIT, 0x1b, 0x48},
{GC0310_8BIT, 0x1e, 0x6b}, //3b//col bias
{GC0310_8BIT, 0x1f, 0x28}, //20//00//08//txlow
{GC0310_8BIT, 0x20, 0x89}, //88//0c//[3:2]DA15
{GC0310_8BIT, 0x21, 0x49}, //48//[3] txhigh
{GC0310_8BIT, 0x22, 0xb0},
{GC0310_8BIT, 0x23, 0x04}, //[1:0]vcm_r
{GC0310_8BIT, 0x24, 0x16}, //15
{GC0310_8BIT, 0x34, 0x20}, //[6:4] rsg high//range
/////////////////////////////////////////////////
//////////////////// BLK ////////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0x26, 0x23}, //[1]dark_current_en [0]offset_en
{GC0310_8BIT, 0x28, 0xff}, //BLK_limie_value
{GC0310_8BIT, 0x29, 0x00}, //global offset
{GC0310_8BIT, 0x33, 0x18}, //offset_ratio
{GC0310_8BIT, 0x37, 0x20}, //dark_current_ratio
{GC0310_8BIT, 0x2a, 0x00},
{GC0310_8BIT, 0x2b, 0x00},
{GC0310_8BIT, 0x2c, 0x00},
{GC0310_8BIT, 0x2d, 0x00},
{GC0310_8BIT, 0x2e, 0x00},
{GC0310_8BIT, 0x2f, 0x00},
{GC0310_8BIT, 0x30, 0x00},
{GC0310_8BIT, 0x31, 0x00},
{GC0310_8BIT, 0x47, 0x80}, //a7
{GC0310_8BIT, 0x4e, 0x66}, //select_row
{GC0310_8BIT, 0xa8, 0x02}, //win_width_dark, same with crop_win_width
{GC0310_8BIT, 0xa9, 0x80},
/////////////////////////////////////////////////
////////////////// ISP reg ///////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0x40, 0x06}, // 0xff //ff //48
{GC0310_8BIT, 0x41, 0x00}, // 0x21 //00//[0]curve_en
{GC0310_8BIT, 0x42, 0x04}, // 0xcf //0a//[1]awn_en
{GC0310_8BIT, 0x44, 0x18}, // 0x18 //02
{GC0310_8BIT, 0x46, 0x02}, // 0x03 //sync
{GC0310_8BIT, 0x49, 0x03},
{GC0310_8BIT, 0x4c, 0x20}, //00[5]pretect exp
{GC0310_8BIT, 0x50, 0x01}, //crop enable
{GC0310_8BIT, 0x51, 0x00},
{GC0310_8BIT, 0x52, 0x00},
{GC0310_8BIT, 0x53, 0x00},
{GC0310_8BIT, 0x54, 0x01},
{GC0310_8BIT, 0x55, 0x01}, //crop window height
{GC0310_8BIT, 0x56, 0xf0},
{GC0310_8BIT, 0x57, 0x02}, //crop window width
{GC0310_8BIT, 0x58, 0x90},
/////////////////////////////////////////////////
/////////////////// GAIN ////////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0x70, 0x70}, //70 //80//global gain
{GC0310_8BIT, 0x71, 0x20}, // pregain gain
{GC0310_8BIT, 0x72, 0x40}, // post gain
{GC0310_8BIT, 0x5a, 0x84}, //84//analog gain 0
{GC0310_8BIT, 0x5b, 0xc9}, //c9
{GC0310_8BIT, 0x5c, 0xed}, //ed//not use pga gain highest level
{GC0310_8BIT, 0x77, 0x40}, // R gain 0x74 //awb gain
{GC0310_8BIT, 0x78, 0x40}, // G gain
{GC0310_8BIT, 0x79, 0x40}, // B gain 0x5f
{GC0310_8BIT, 0x48, 0x00},
{GC0310_8BIT, 0xfe, 0x01},
{GC0310_8BIT, 0x0a, 0x45}, //[7]col gain mode
{GC0310_8BIT, 0x3e, 0x40},
{GC0310_8BIT, 0x3f, 0x5c},
{GC0310_8BIT, 0x40, 0x7b},
{GC0310_8BIT, 0x41, 0xbd},
{GC0310_8BIT, 0x42, 0xf6},
{GC0310_8BIT, 0x43, 0x63},
{GC0310_8BIT, 0x03, 0x60},
{GC0310_8BIT, 0x44, 0x03},
/////////////////////////////////////////////////
///////////////// dark sun //////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0xfe, 0x01},
{GC0310_8BIT, 0x45, 0xa4}, // 0xf7
{GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun vaule th
{GC0310_8BIT, 0x48, 0x03}, //sun mode
{GC0310_8BIT, 0x4f, 0x60}, //sun_clamp
{GC0310_8BIT, 0xfe, 0x00},
{GC0310_TOK_TERM, 0, 0},
};
static struct gc0310_reg const gc0310_VGA_30fps[] = {
{GC0310_8BIT, 0xfe, 0x00},
{GC0310_8BIT, 0x0d, 0x01}, //height
{GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
{GC0310_8BIT, 0x0f, 0x02}, //width
{GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
{GC0310_8BIT, 0x50, 0x01}, //crop enable
{GC0310_8BIT, 0x51, 0x00},
{GC0310_8BIT, 0x52, 0x00},
{GC0310_8BIT, 0x53, 0x00},
{GC0310_8BIT, 0x54, 0x01},
{GC0310_8BIT, 0x55, 0x01}, //crop window height
{GC0310_8BIT, 0x56, 0xf0},
{GC0310_8BIT, 0x57, 0x02}, //crop window width
{GC0310_8BIT, 0x58, 0x90},
{GC0310_8BIT, 0xfe, 0x03},
{GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] //
{GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
{GC0310_8BIT, 0xfe, 0x00},
{GC0310_TOK_TERM, 0, 0},
};
struct gc0310_resolution gc0310_res_preview[] = {
{
.desc = "gc0310_VGA_30fps",
.width = 656, // 648,
.height = 496, // 488,
.fps = 30,
//.pix_clk_freq = 73,
.used = 0,
#if 0
.pixels_per_line = 0x0314,
.lines_per_frame = 0x0213,
#endif
.bin_factor_x = 1,
.bin_factor_y = 1,
.bin_mode = 0,
.skip_frames = 2,
.regs = gc0310_VGA_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview))
struct gc0310_resolution gc0310_res_still[] = {
{
.desc = "gc0310_VGA_30fps",
.width = 656, // 648,
.height = 496, // 488,
.fps = 30,
//.pix_clk_freq = 73,
.used = 0,
#if 0
.pixels_per_line = 0x0314,
.lines_per_frame = 0x0213,
#endif
.bin_factor_x = 1,
.bin_factor_y = 1,
.bin_mode = 0,
.skip_frames = 2,
.regs = gc0310_VGA_30fps,
},
};
#define N_RES_STILL (ARRAY_SIZE(gc0310_res_still))
struct gc0310_resolution gc0310_res_video[] = {
{
.desc = "gc0310_VGA_30fps",
.width = 656, // 648,
.height = 496, // 488,
.fps = 30,
//.pix_clk_freq = 73,
.used = 0,
#if 0
.pixels_per_line = 0x0314,
.lines_per_frame = 0x0213,
#endif
.bin_factor_x = 1,
.bin_factor_y = 1,
.bin_mode = 0,
.skip_frames = 2,
.regs = gc0310_VGA_30fps,
},
};
#define N_RES_VIDEO (ARRAY_SIZE(gc0310_res_video))
static struct gc0310_resolution *gc0310_res = gc0310_res_preview;
static int N_RES = N_RES_PREVIEW;
#endif

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/*
* Support for GalaxyCore GC2235 2M camera sensor.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program.
*
*/
#ifndef __GC2235_H__
#define __GC2235_H__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/spinlock.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <linux/v4l2-mediabus.h>
#include <media/media-entity.h>
#include <linux/atomisp_platform.h>
#define GC2235_NAME "gc2235"
/* Defines for register writes and register array processing */
#define I2C_MSG_LENGTH 0x2
#define I2C_RETRY_COUNT 5
#define GC2235_FOCAL_LENGTH_NUM 278 /*2.78mm*/
#define GC2235_FOCAL_LENGTH_DEM 100
#define GC2235_F_NUMBER_DEFAULT_NUM 26
#define GC2235_F_NUMBER_DEM 10
#define MAX_FMTS 1
/*
* focal length bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define GC2235_FOCAL_LENGTH_DEFAULT 0x1160064
/*
* current f-number bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define GC2235_F_NUMBER_DEFAULT 0x1a000a
/*
* f-number range bits definition:
* bits 31-24: max f-number numerator
* bits 23-16: max f-number denominator
* bits 15-8: min f-number numerator
* bits 7-0: min f-number denominator
*/
#define GC2235_F_NUMBER_RANGE 0x1a0a1a0a
#define GC2235_ID 0x2235
#define GC2235_FINE_INTG_TIME_MIN 0
#define GC2235_FINE_INTG_TIME_MAX_MARGIN 0
#define GC2235_COARSE_INTG_TIME_MIN 1
#define GC2235_COARSE_INTG_TIME_MAX_MARGIN 6
/*
* GC2235 System control registers
*/
/*
* GC2235 System control registers
*/
#define GC2235_SENSOR_ID_H 0xF0
#define GC2235_SENSOR_ID_L 0xF1
#define GC2235_RESET_RELATED 0xFE
#define GC2235_SW_RESET 0x8
#define GC2235_MIPI_RESET 0x3
#define GC2235_RESET_BIT 0x4
#define GC2235_REGISTER_PAGE_0 0x0
#define GC2235_REGISTER_PAGE_3 0x3
#define GC2235_V_CROP_START_H 0x91
#define GC2235_V_CROP_START_L 0x92
#define GC2235_H_CROP_START_H 0x93
#define GC2235_H_CROP_START_L 0x94
#define GC2235_V_OUTSIZE_H 0x95
#define GC2235_V_OUTSIZE_L 0x96
#define GC2235_H_OUTSIZE_H 0x97
#define GC2235_H_OUTSIZE_L 0x98
#define GC2235_HB_H 0x5
#define GC2235_HB_L 0x6
#define GC2235_VB_H 0x7
#define GC2235_VB_L 0x8
#define GC2235_SH_DELAY_H 0x11
#define GC2235_SH_DELAY_L 0x12
#define GC2235_CSI2_MODE 0x10
#define GC2235_EXPOSURE_H 0x3
#define GC2235_EXPOSURE_L 0x4
#define GC2235_GLOBAL_GAIN 0xB0
#define GC2235_PRE_GAIN 0xB1
#define GC2235_AWB_R_GAIN 0xB3
#define GC2235_AWB_G_GAIN 0xB4
#define GC2235_AWB_B_GAIN 0xB5
#define GC2235_START_STREAMING 0x91
#define GC2235_STOP_STREAMING 0x0
struct regval_list {
u16 reg_num;
u8 value;
};
struct gc2235_resolution {
u8 *desc;
const struct gc2235_reg *regs;
int res;
int width;
int height;
int fps;
int pix_clk_freq;
u32 skip_frames;
u16 pixels_per_line;
u16 lines_per_frame;
u8 bin_factor_x;
u8 bin_factor_y;
u8 bin_mode;
bool used;
};
struct gc2235_format {
u8 *desc;
u32 pixelformat;
struct gc2235_reg *regs;
};
/*
* gc2235 device structure.
*/
struct gc2235_device {
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_mbus_framefmt format;
struct mutex input_lock;
struct v4l2_ctrl_handler ctrl_handler;
struct camera_sensor_platform_data *platform_data;
int vt_pix_clk_freq_mhz;
int fmt_idx;
int run_mode;
u8 res;
u8 type;
};
enum gc2235_tok_type {
GC2235_8BIT = 0x0001,
GC2235_16BIT = 0x0002,
GC2235_32BIT = 0x0004,
GC2235_TOK_TERM = 0xf000, /* terminating token for reg list */
GC2235_TOK_DELAY = 0xfe00, /* delay token for reg list */
GC2235_TOK_MASK = 0xfff0
};
/**
* struct gc2235_reg - MI sensor register format
* @type: type of the register
* @reg: 8-bit offset to register
* @val: 8/16/32-bit register value
*
* Define a structure for sensor register initialization values
*/
struct gc2235_reg {
enum gc2235_tok_type type;
u8 reg;
u32 val; /* @set value for read/mod/write, @mask */
};
#define to_gc2235_sensor(x) container_of(x, struct gc2235_device, sd)
#define GC2235_MAX_WRITE_BUF_SIZE 30
struct gc2235_write_buffer {
u8 addr;
u8 data[GC2235_MAX_WRITE_BUF_SIZE];
};
struct gc2235_write_ctrl {
int index;
struct gc2235_write_buffer buffer;
};
static const struct i2c_device_id gc2235_id[] = {
{GC2235_NAME, 0},
{}
};
static struct gc2235_reg const gc2235_stream_on[] = {
{ GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */
{ GC2235_8BIT, 0x10, 0x91}, /* start mipi */
{ GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_stream_off[] = {
{ GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */
{ GC2235_8BIT, 0x10, 0x01}, /* stop mipi */
{ GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_init_settings[] = {
/* Sysytem */
{ GC2235_8BIT, 0xfe, 0x80 },
{ GC2235_8BIT, 0xfe, 0x80 },
{ GC2235_8BIT, 0xfe, 0x80 },
{ GC2235_8BIT, 0xf2, 0x00 },
{ GC2235_8BIT, 0xf6, 0x00 },
{ GC2235_8BIT, 0xfc, 0x06 },
{ GC2235_8BIT, 0xf7, 0x15 },
{ GC2235_8BIT, 0xf8, 0x84 },
{ GC2235_8BIT, 0xf9, 0xfe },
{ GC2235_8BIT, 0xfa, 0x00 },
{ GC2235_8BIT, 0xfe, 0x00 },
/* Analog & cisctl */
{ GC2235_8BIT, 0x03, 0x04 },
{ GC2235_8BIT, 0x04, 0x9E },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x06, 0xfd },
{ GC2235_8BIT, 0x07, 0x00 },
{ GC2235_8BIT, 0x08, 0x14 },
{ GC2235_8BIT, 0x0a, 0x02 }, /* row start */
{ GC2235_8BIT, 0x0c, 0x00 }, /* col start */
{ GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */
{ GC2235_8BIT, 0x0e, 0xd0 },
{ GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */
{ GC2235_8BIT, 0x10, 0x60 },
{ GC2235_8BIT, 0x17, 0x15 }, /* mirror flip */
{ GC2235_8BIT, 0x18, 0x1a },
{ GC2235_8BIT, 0x19, 0x06 },
{ GC2235_8BIT, 0x1a, 0x01 },
{ GC2235_8BIT, 0x1b, 0x4d },
{ GC2235_8BIT, 0x1e, 0x88 },
{ GC2235_8BIT, 0x1f, 0x48 },
{ GC2235_8BIT, 0x20, 0x03 },
{ GC2235_8BIT, 0x21, 0x7f },
{ GC2235_8BIT, 0x22, 0x83 },
{ GC2235_8BIT, 0x23, 0x42 },
{ GC2235_8BIT, 0x24, 0x16 },
{ GC2235_8BIT, 0x26, 0x01 }, /*analog gain*/
{ GC2235_8BIT, 0x27, 0x30 },
{ GC2235_8BIT, 0x3f, 0x00 }, /* PRC */
/* blk */
{ GC2235_8BIT, 0x40, 0xa3 },
{ GC2235_8BIT, 0x41, 0x82 },
{ GC2235_8BIT, 0x43, 0x20 },
{ GC2235_8BIT, 0x5e, 0x18 },
{ GC2235_8BIT, 0x5f, 0x18 },
{ GC2235_8BIT, 0x60, 0x18 },
{ GC2235_8BIT, 0x61, 0x18 },
{ GC2235_8BIT, 0x62, 0x18 },
{ GC2235_8BIT, 0x63, 0x18 },
{ GC2235_8BIT, 0x64, 0x18 },
{ GC2235_8BIT, 0x65, 0x18 },
{ GC2235_8BIT, 0x66, 0x20 },
{ GC2235_8BIT, 0x67, 0x20 },
{ GC2235_8BIT, 0x68, 0x20 },
{ GC2235_8BIT, 0x69, 0x20 },
/* Gain */
{ GC2235_8BIT, 0xb2, 0x00 },
{ GC2235_8BIT, 0xb3, 0x40 },
{ GC2235_8BIT, 0xb4, 0x40 },
{ GC2235_8BIT, 0xb5, 0x40 },
/* Dark sun */
{ GC2235_8BIT, 0xbc, 0x00 },
{ GC2235_8BIT, 0xfe, 0x03 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
/*
* Register settings for various resolution
*/
static struct gc2235_reg const gc2235_1296_736_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x07, 0x01 }, /* VBI */
{ GC2235_8BIT, 0x08, 0x44 },
{ GC2235_8BIT, 0x09, 0x00 }, /* row start */
{ GC2235_8BIT, 0x0a, 0xf0 },
{ GC2235_8BIT, 0x0b, 0x00 }, /* col start */
{ GC2235_8BIT, 0x0c, 0xa0 },
{ GC2235_8BIT, 0x0d, 0x02 }, /* win height 736 */
{ GC2235_8BIT, 0x0e, 0xf0 },
{ GC2235_8BIT, 0x0f, 0x05 }, /* win width: 1296 */
{ GC2235_8BIT, 0x10, 0x20 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x08 },
{ GC2235_8BIT, 0x94, 0x08 },
{ GC2235_8BIT, 0x95, 0x02 }, /* crop win height 736 */
{ GC2235_8BIT, 0x96, 0xe0 },
{ GC2235_8BIT, 0x97, 0x05 }, /* crop win width 1296 */
{ GC2235_8BIT, 0x98, 0x10 },
/* mimi init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0x54 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x06 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_960_640_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x07, 0x02 }, /* VBI */
{ GC2235_8BIT, 0x08, 0xA4 },
{ GC2235_8BIT, 0x09, 0x01 }, /* row start */
{ GC2235_8BIT, 0x0a, 0x18 },
{ GC2235_8BIT, 0x0b, 0x01 }, /* col start */
{ GC2235_8BIT, 0x0c, 0x40 },
{ GC2235_8BIT, 0x0d, 0x02 }, /* win height 656 */
{ GC2235_8BIT, 0x0e, 0x90 },
{ GC2235_8BIT, 0x0f, 0x03 }, /* win width: 976 */
{ GC2235_8BIT, 0x10, 0xd0 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x02 },
{ GC2235_8BIT, 0x94, 0x06 },
{ GC2235_8BIT, 0x95, 0x02 }, /* crop win height 640 */
{ GC2235_8BIT, 0x96, 0x80 },
{ GC2235_8BIT, 0x97, 0x03 }, /* crop win width 960 */
{ GC2235_8BIT, 0x98, 0xc0 },
/* mimp init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0xb0 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x04 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_1600_900_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x0d, 0x03 }, /* win height 932 */
{ GC2235_8BIT, 0x0e, 0xa4 },
{ GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1632 */
{ GC2235_8BIT, 0x10, 0x50 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x02 },
{ GC2235_8BIT, 0x94, 0x06 },
{ GC2235_8BIT, 0x95, 0x03 }, /* crop win height 900 */
{ GC2235_8BIT, 0x96, 0x84 },
{ GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1600 */
{ GC2235_8BIT, 0x98, 0x40 },
/* mimi init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0xd0 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_1616_1082_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */
{ GC2235_8BIT, 0x0e, 0xd0 },
{ GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */
{ GC2235_8BIT, 0x10, 0x50 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x4a },
{ GC2235_8BIT, 0x94, 0x00 },
{ GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1082 */
{ GC2235_8BIT, 0x96, 0x3a },
{ GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */
{ GC2235_8BIT, 0x98, 0x50 },
/* mimp init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_1616_1216_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */
{ GC2235_8BIT, 0x0e, 0xd0 },
{ GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */
{ GC2235_8BIT, 0x10, 0x50 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x02 },
{ GC2235_8BIT, 0x94, 0x00 },
{ GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1216 */
{ GC2235_8BIT, 0x96, 0xc0 },
{ GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */
{ GC2235_8BIT, 0x98, 0x50 },
/* mimi init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
struct gc2235_resolution gc2235_res_preview[] = {
{
.desc = "gc2235_1600_900_30fps",
.width = 1600,
.height = 900,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1068,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1600_900_30fps,
},
{
.desc = "gc2235_1600_1066_30fps",
.width = 1616,
.height = 1082,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1368,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1616_1082_30fps,
},
{
.desc = "gc2235_1600_1200_30fps",
.width = 1616,
.height = 1216,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1368,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1616_1216_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(gc2235_res_preview))
struct gc2235_resolution gc2235_res_still[] = {
{
.desc = "gc2235_1600_900_30fps",
.width = 1600,
.height = 900,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1068,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1600_900_30fps,
},
{
.desc = "gc2235_1600_1066_30fps",
.width = 1616,
.height = 1082,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1368,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1616_1082_30fps,
},
{
.desc = "gc2235_1600_1200_30fps",
.width = 1616,
.height = 1216,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1368,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1616_1216_30fps,
},
};
#define N_RES_STILL (ARRAY_SIZE(gc2235_res_still))
struct gc2235_resolution gc2235_res_video[] = {
{
.desc = "gc2235_1296_736_30fps",
.width = 1296,
.height = 736,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 1828,
.lines_per_frame = 888,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1296_736_30fps,
},
{
.desc = "gc2235_960_640_30fps",
.width = 960,
.height = 640,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 1492,
.lines_per_frame = 792,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_960_640_30fps,
},
};
#define N_RES_VIDEO (ARRAY_SIZE(gc2235_res_video))
static struct gc2235_resolution *gc2235_res = gc2235_res_preview;
static int N_RES = N_RES_PREVIEW;
#endif

9
drivers/staging/media/atomisp/i2c/imx/Kconfig Normal file
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config VIDEO_IMX
tristate "sony imx sensor support"
depends on I2C && VIDEO_V4L2 && VIDEO_MSRLIST_HELPER && m
---help---
This is a Video4Linux2 sensor-level driver for the Sony
IMX RAW sensor.
It currently depends on internal V4L2 extensions defined in
atomisp driver.

8
drivers/staging/media/atomisp/i2c/imx/Makefile Normal file
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obj-$(CONFIG_VIDEO_IMX) += imx1x5.o
imx1x5-objs := imx.o drv201.o ad5816g.o dw9714.o dw9719.o dw9718.o vcm.o otp.o otp_imx.o otp_brcc064_e2prom.o otp_e2prom.o
ov8858_driver-objs := ../ov8858.o dw9718.o vcm.o
obj-$(CONFIG_VIDEO_OV8858) += ov8858_driver.o
ccflags-y += -Werror

225
drivers/staging/media/atomisp/i2c/imx/ad5816g.c Normal file
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#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/kmod.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include "ad5816g.h"
struct ad5816g_device ad5816g_dev;
static int ad5816g_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val)
{
struct i2c_msg msg[2];
u8 buf[2];
buf[0] = reg;
buf[1] = 0;
msg[0].addr = AD5816G_VCM_ADDR;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = &buf[0];
msg[1].addr = AD5816G_VCM_ADDR;
msg[1].flags = I2C_M_RD;
msg[1].len = 1;
msg[1].buf = &buf[1];
*val = 0;
if (i2c_transfer(client->adapter, msg, 2) != 2)
return -EIO;
*val = buf[1];
return 0;
}
static int ad5816g_i2c_wr8(struct i2c_client *client, u8 reg, u8 val)
{
struct i2c_msg msg;
u8 buf[2];
buf[0] = reg;
buf[1] = val;
msg.addr = AD5816G_VCM_ADDR;
msg.flags = 0;
msg.len = 2;
msg.buf = &buf[0];
if (i2c_transfer(client->adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
static int ad5816g_i2c_wr16(struct i2c_client *client, u8 reg, u16 val)
{
struct i2c_msg msg;
u8 buf[3];
buf[0] = reg;
buf[1] = (u8)(val >> 8);
buf[2] = (u8)(val & 0xff);
msg.addr = AD5816G_VCM_ADDR;
msg.flags = 0;
msg.len = 3;
msg.buf = &buf[0];
if (i2c_transfer(client->adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
static int ad5816g_set_arc_mode(struct i2c_client *client)
{
int ret;
ret = ad5816g_i2c_wr8(client, AD5816G_CONTROL, AD5816G_ARC_EN);
if (ret)
return ret;
ret = ad5816g_i2c_wr8(client, AD5816G_MODE,
AD5816G_MODE_2_5M_SWITCH_CLOCK);
if (ret)
return ret;
ret = ad5816g_i2c_wr8(client, AD5816G_VCM_FREQ, AD5816G_DEF_FREQ);
return ret;
}
int ad5816g_vcm_power_up(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
u8 ad5816g_id;
/* Enable power */
ret = ad5816g_dev.platform_data->power_ctrl(sd, 1);
if (ret)
return ret;
/* waiting time AD5816G(vcm) - t1 + t2
* t1(1ms) -Time from VDD high to first i2c cmd
* t2(100us) - exit power-down mode time
*/
usleep_range(1100, 2200);
/* Detect device */
ret = ad5816g_i2c_rd8(client, AD5816G_IC_INFO, &ad5816g_id);
if (ret < 0)
goto fail_powerdown;
if (ad5816g_id != AD5816G_ID) {
ret = -ENXIO;
goto fail_powerdown;
}
ret = ad5816g_set_arc_mode(client);
if (ret)
return ret;
/* set the VCM_THRESHOLD */
ret = ad5816g_i2c_wr8(client, AD5816G_VCM_THRESHOLD,
AD5816G_DEF_THRESHOLD);
return ret;
fail_powerdown:
ad5816g_dev.platform_data->power_ctrl(sd, 0);
return ret;
}
int ad5816g_vcm_power_down(struct v4l2_subdev *sd)
{
return ad5816g_dev.platform_data->power_ctrl(sd, 0);
}
int ad5816g_t_focus_vcm(struct v4l2_subdev *sd, u16 val)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
u16 data = val & VCM_CODE_MASK;
return ad5816g_i2c_wr16(client, AD5816G_VCM_CODE_MSB, data);
}
int ad5816g_t_focus_abs(struct v4l2_subdev *sd, s32 value)
{
int ret;
value = clamp(value, 0, AD5816G_MAX_FOCUS_POS);
ret = ad5816g_t_focus_vcm(sd, value);
if (ret == 0) {
ad5816g_dev.number_of_steps = value - ad5816g_dev.focus;
ad5816g_dev.focus = value;
getnstimeofday(&(ad5816g_dev.timestamp_t_focus_abs));
}
return ret;
}
int ad5816g_t_focus_rel(struct v4l2_subdev *sd, s32 value)
{
return ad5816g_t_focus_abs(sd, ad5816g_dev.focus + value);
}
int ad5816g_q_focus_status(struct v4l2_subdev *sd, s32 *value)
{
u32 status = 0;
struct timespec temptime;
const struct timespec timedelay = {
0,
min_t(u32, abs(ad5816g_dev.number_of_steps) * DELAY_PER_STEP_NS,
DELAY_MAX_PER_STEP_NS),
};
ktime_get_ts(&temptime);
temptime = timespec_sub(temptime, (ad5816g_dev.timestamp_t_focus_abs));
if (timespec_compare(&temptime, &timedelay) <= 0) {
status |= ATOMISP_FOCUS_STATUS_MOVING;
status |= ATOMISP_FOCUS_HP_IN_PROGRESS;
} else {
status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE;
status |= ATOMISP_FOCUS_HP_COMPLETE;
}
*value = status;
return 0;
}
int ad5816g_q_focus_abs(struct v4l2_subdev *sd, s32 *value)
{
s32 val;
ad5816g_q_focus_status(sd, &val);
if (val & ATOMISP_FOCUS_STATUS_MOVING)
*value = ad5816g_dev.focus - ad5816g_dev.number_of_steps;
else
*value = ad5816g_dev.focus;
return 0;
}
int ad5816g_t_vcm_slew(struct v4l2_subdev *sd, s32 value)
{
return 0;
}
int ad5816g_t_vcm_timing(struct v4l2_subdev *sd, s32 value)
{
return 0;
}
int ad5816g_vcm_init(struct v4l2_subdev *sd)
{
ad5816g_dev.platform_data = camera_get_af_platform_data();
return (NULL == ad5816g_dev.platform_data) ? -ENODEV : 0;
}

49
drivers/staging/media/atomisp/i2c/imx/ad5816g.h Normal file
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#ifndef __AD5816G_H__
#define __AD5816G_H__
#include <linux/atomisp_platform.h>
#include <linux/types.h>
#include <linux/time.h>
#define AD5816G_VCM_ADDR 0x0e
/* ad5816g device structure */
struct ad5816g_device {
const struct camera_af_platform_data *platform_data;
struct timespec timestamp_t_focus_abs;
struct timespec focus_time; /* Time when focus was last time set */
s32 focus; /* Current focus value */
s16 number_of_steps;
};
#define AD5816G_INVALID_CONFIG 0xffffffff
#define AD5816G_MAX_FOCUS_POS 1023
#define DELAY_PER_STEP_NS 1000000
#define DELAY_MAX_PER_STEP_NS (1000000 * 1023)
/* Register Definitions */
#define AD5816G_IC_INFO 0x00
#define AD5816G_IC_VERSION 0x01
#define AD5816G_CONTROL 0x02
#define AD5816G_VCM_CODE_MSB 0x03
#define AD5816G_VCM_CODE_LSB 0x04
#define AD5816G_STATUS 0x05
#define AD5816G_MODE 0x06
#define AD5816G_VCM_FREQ 0x07
#define AD5816G_VCM_THRESHOLD 0x08
/* ARC MODE ENABLE */
#define AD5816G_ARC_EN 0x02
/* ARC RES2 MODE */
#define AD5816G_ARC_RES2 0x01
/* ARC VCM FREQ - 78.1Hz */
#define AD5816G_DEF_FREQ 0x7a
/* ARC VCM THRESHOLD - 0x08 << 1 */
#define AD5816G_DEF_THRESHOLD 0x64
#define AD5816G_ID 0x24
#define VCM_CODE_MASK 0x03ff
#define AD5816G_MODE_2_5M_SWITCH_CLOCK 0x14
#endif

65
drivers/staging/media/atomisp/i2c/imx/common.h Normal file
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#ifndef __COMMON_H__
#define __COMMON_H__
#define MAX_FPS_OPTIONS_SUPPORTED 3
#define I2C_MSG_LENGTH 0x2
#define E2PROM_2ADDR 0x80000000
#define E2PROM_ADDR_MASK 0x7fffffff
/* Defines for register writes and register array processing */
#define IMX_BYTE_MAX 32
#define IMX_SHORT_MAX 16
#define I2C_RETRY_COUNT 5
#define IMX_TOK_MASK 0xfff0
enum imx_tok_type {
IMX_8BIT = 0x0001,
IMX_16BIT = 0x0002,
IMX_TOK_TERM = 0xf000, /* terminating token for reg list */
IMX_TOK_DELAY = 0xfe00 /* delay token for reg list */
};
/**
* struct imx_reg - MI sensor register format
* @type: type of the register
* @reg: 16-bit offset to register
* @val: 8/16/32-bit register value
*
* Define a structure for sensor register initialization values
*/
struct imx_reg {
enum imx_tok_type type;
u16 sreg;
u32 val; /* @set value for read/mod/write, @mask */
};
struct imx_fps_setting {
int fps;
unsigned short pixels_per_line;
unsigned short lines_per_frame;
int mipi_freq; /* MIPI lane frequency in kHz */
const struct imx_reg *regs; /* regs that the fps setting needs */
};
struct imx_resolution {
const struct imx_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED];
u8 *desc;
const struct imx_reg *regs;
int res;
int width;
int height;
int fps;
unsigned short pixels_per_line;
unsigned short lines_per_frame;
int mipi_freq; /* MIPI lane frequency in kHz */
unsigned short skip_frames;
u8 bin_factor_x;
u8 bin_factor_y;
bool used;
};
#define GROUPED_PARAMETER_HOLD_ENABLE {IMX_8BIT, 0x0104, 0x1}
#define GROUPED_PARAMETER_HOLD_DISABLE {IMX_8BIT, 0x0104, 0x0}
int imx_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val);
#endif

218
drivers/staging/media/atomisp/i2c/imx/drv201.c Normal file
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#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/kmod.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include <asm/intel-mid.h>
#include "drv201.h"
static struct drv201_device drv201_dev;
static int drv201_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val)
{
struct i2c_msg msg[2];
u8 buf[2];
buf[0] = reg;
buf[1] = 0;
msg[0].addr = DRV201_VCM_ADDR;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = &buf[0];
msg[1].addr = DRV201_VCM_ADDR;
msg[1].flags = I2C_M_RD;
msg[1].len = 1;
msg[1].buf = &buf[1];
*val = 0;
if (i2c_transfer(client->adapter, msg, 2) != 2)
return -EIO;
*val = buf[1];
return 0;
}
static int drv201_i2c_wr8(struct i2c_client *client, u8 reg, u8 val)
{
struct i2c_msg msg;
u8 buf[2];
buf[0] = reg;
buf[1] = val;
msg.addr = DRV201_VCM_ADDR;
msg.flags = 0;
msg.len = 2;
msg.buf = &buf[0];
if (i2c_transfer(client->adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
static int drv201_i2c_wr16(struct i2c_client *client, u8 reg, u16 val)
{
struct i2c_msg msg;
u8 buf[3];
buf[0] = reg;
buf[1] = (u8)(val >> 8);
buf[2] = (u8)(val & 0xff);
msg.addr = DRV201_VCM_ADDR;
msg.flags = 0;
msg.len = 3;
msg.buf = &buf[0];
if (i2c_transfer(client->adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
int drv201_vcm_power_up(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
u8 value;
/* Enable power */
ret = drv201_dev.platform_data->power_ctrl(sd, 1);
if (ret)
return ret;
/* Wait for VBAT to stabilize */
udelay(1);
/*
* Jiggle SCL pin to wake up device.
* Drv201 expect SCL from low to high to wake device up.
* So the 1st access to i2c would fail.
* Using following function to wake device up.
*/
drv201_i2c_wr8(client, DRV201_CONTROL, DRV201_RESET);
/* Need 100us to transit from SHUTDOWN to STANDBY*/
usleep_range(WAKEUP_DELAY_US, WAKEUP_DELAY_US * 10);
/* Reset device */
ret = drv201_i2c_wr8(client, DRV201_CONTROL, DRV201_RESET);
if (ret < 0)
goto fail_powerdown;
/* Detect device */
ret = drv201_i2c_rd8(client, DRV201_CONTROL, &value);
if (ret < 0)
goto fail_powerdown;
if (value != DEFAULT_CONTROL_VAL) {
ret = -ENXIO;
goto fail_powerdown;
}
drv201_dev.focus = DRV201_MAX_FOCUS_POS;
drv201_dev.initialized = true;
return 0;
fail_powerdown:
drv201_dev.platform_data->power_ctrl(sd, 0);
return ret;
}
int drv201_vcm_power_down(struct v4l2_subdev *sd)
{
return drv201_dev.platform_data->power_ctrl(sd, 0);
}
int drv201_t_focus_vcm(struct v4l2_subdev *sd, u16 val)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
u16 data = val & VCM_CODE_MASK;
if (!drv201_dev.initialized)
return -ENODEV;
return drv201_i2c_wr16(client, DRV201_VCM_CURRENT, data);
}
int drv201_t_focus_abs(struct v4l2_subdev *sd, s32 value)
{
int ret;
value = clamp(value, 0, DRV201_MAX_FOCUS_POS);
ret = drv201_t_focus_vcm(sd, value);
if (ret == 0) {
drv201_dev.number_of_steps = value - drv201_dev.focus;
drv201_dev.focus = value;
getnstimeofday(&(drv201_dev.timestamp_t_focus_abs));
}
return ret;
}
int drv201_t_focus_rel(struct v4l2_subdev *sd, s32 value)
{
return drv201_t_focus_abs(sd, drv201_dev.focus + value);
}
int drv201_q_focus_status(struct v4l2_subdev *sd, s32 *value)
{
u32 status = 0;
struct timespec temptime;
const struct timespec timedelay = {
0,
min_t(u32, abs(drv201_dev.number_of_steps)*DELAY_PER_STEP_NS,
DELAY_MAX_PER_STEP_NS),
};
ktime_get_ts(&temptime);
temptime = timespec_sub(temptime, (drv201_dev.timestamp_t_focus_abs));
if (timespec_compare(&temptime, &timedelay) <= 0) {
status |= ATOMISP_FOCUS_STATUS_MOVING;
status |= ATOMISP_FOCUS_HP_IN_PROGRESS;
} else {
status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE;
status |= ATOMISP_FOCUS_HP_COMPLETE;
}
*value = status;
return 0;
}
int drv201_q_focus_abs(struct v4l2_subdev *sd, s32 *value)
{
s32 val;
drv201_q_focus_status(sd, &val);
if (val & ATOMISP_FOCUS_STATUS_MOVING)
*value = drv201_dev.focus - drv201_dev.number_of_steps;
else
*value = drv201_dev.focus;
return 0;
}
int drv201_t_vcm_slew(struct v4l2_subdev *sd, s32 value)
{
return 0;
}
int drv201_t_vcm_timing(struct v4l2_subdev *sd, s32 value)
{
return 0;
}
int drv201_vcm_init(struct v4l2_subdev *sd)
{
drv201_dev.platform_data = camera_get_af_platform_data();
return (NULL == drv201_dev.platform_data) ? -ENODEV : 0;
}

38
drivers/staging/media/atomisp/i2c/imx/drv201.h Normal file
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#ifndef __DRV201_H__
#define __DRV201_H__
#include <linux/atomisp_platform.h>
#include <linux/types.h>
#include <linux/time.h>
#define DRV201_VCM_ADDR 0x0e
/* drv201 device structure */
struct drv201_device {
const struct camera_af_platform_data *platform_data;
struct timespec timestamp_t_focus_abs;
struct timespec focus_time; /* Time when focus was last time set */
s32 focus; /* Current focus value */
s16 number_of_steps;
bool initialized; /* true if drv201 is detected */
};
#define DRV201_INVALID_CONFIG 0xffffffff
#define DRV201_MAX_FOCUS_POS 1023
#define DELAY_PER_STEP_NS 1000000
#define DELAY_MAX_PER_STEP_NS (1000000 * 1023)
#define DRV201_CONTROL 2
#define DRV201_VCM_CURRENT 3
#define DRV201_STATUS 5
#define DRV201_MODE 6
#define DRV201_VCM_FREQ 7
#define DEFAULT_CONTROL_VAL 2
#define DRV201_RESET 1
#define WAKEUP_DELAY_US 100
#define VCM_CODE_MASK 0x03ff
#endif

235
drivers/staging/media/atomisp/i2c/imx/dw9714.c Normal file
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#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/kmod.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include <asm/intel-mid.h>
#include "dw9714.h"
static struct dw9714_device dw9714_dev;
static int dw9714_i2c_write(struct i2c_client *client, u16 data)
{
struct i2c_msg msg;
const int num_msg = 1;
int ret;
u16 val;
val = cpu_to_be16(data);
msg.addr = DW9714_VCM_ADDR;
msg.flags = 0;
msg.len = DW9714_16BIT;
msg.buf = (u8 *)&val;
ret = i2c_transfer(client->adapter, &msg, 1);
return ret == num_msg ? 0 : -EIO;
}
int dw9714_vcm_power_up(struct v4l2_subdev *sd)
{
int ret;
/* Enable power */
ret = dw9714_dev.platform_data->power_ctrl(sd, 1);
/* waiting time requested by DW9714A(vcm) */
usleep_range(12000, 12500);
return ret;
}
int dw9714_vcm_power_down(struct v4l2_subdev *sd)
{
return dw9714_dev.platform_data->power_ctrl(sd, 0);
}
int dw9714_t_focus_vcm(struct v4l2_subdev *sd, u16 val)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret = -EINVAL;
u8 mclk = vcm_step_mclk(dw9714_dev.vcm_settings.step_setting);
u8 s = vcm_step_s(dw9714_dev.vcm_settings.step_setting);
/*
* For different mode, VCM_PROTECTION_OFF/ON required by the
* control procedure. For DW9714_DIRECT/DLC mode, slew value is
* VCM_DEFAULT_S(0).
*/
switch (dw9714_dev.vcm_mode) {
case DW9714_DIRECT:
if (dw9714_dev.vcm_settings.update) {
ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF);
if (ret)
return ret;
ret = dw9714_i2c_write(client, DIRECT_VCM);
if (ret)
return ret;
ret = dw9714_i2c_write(client, VCM_PROTECTION_ON);
if (ret)
return ret;
dw9714_dev.vcm_settings.update = false;
}
ret = dw9714_i2c_write(client,
vcm_val(val, VCM_DEFAULT_S));
break;
case DW9714_LSC:
if (dw9714_dev.vcm_settings.update) {
ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF);
if (ret)
return ret;
ret = dw9714_i2c_write(client,
vcm_dlc_mclk(DLC_DISABLE, mclk));
if (ret)
return ret;
ret = dw9714_i2c_write(client,
vcm_tsrc(dw9714_dev.vcm_settings.t_src));
if (ret)
return ret;
ret = dw9714_i2c_write(client, VCM_PROTECTION_ON);
if (ret)
return ret;
dw9714_dev.vcm_settings.update = false;
}
ret = dw9714_i2c_write(client, vcm_val(val, s));
break;
case DW9714_DLC:
if (dw9714_dev.vcm_settings.update) {
ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF);
if (ret)
return ret;
ret = dw9714_i2c_write(client,
vcm_dlc_mclk(DLC_ENABLE, mclk));
if (ret)
return ret;
ret = dw9714_i2c_write(client,
vcm_tsrc(dw9714_dev.vcm_settings.t_src));
if (ret)
return ret;
ret = dw9714_i2c_write(client, VCM_PROTECTION_ON);
if (ret)
return ret;
dw9714_dev.vcm_settings.update = false;
}
ret = dw9714_i2c_write(client,
vcm_val(val, VCM_DEFAULT_S));
break;
}
return ret;
}
int dw9714_t_focus_abs(struct v4l2_subdev *sd, s32 value)
{
int ret;
value = clamp(value, 0, DW9714_MAX_FOCUS_POS);
ret = dw9714_t_focus_vcm(sd, value);
if (ret == 0) {
dw9714_dev.number_of_steps = value - dw9714_dev.focus;
dw9714_dev.focus = value;
getnstimeofday(&(dw9714_dev.timestamp_t_focus_abs));
}
return ret;
}
int dw9714_t_focus_abs_init(struct v4l2_subdev *sd)
{
int ret;
ret = dw9714_t_focus_vcm(sd, DW9714_DEFAULT_FOCUS_POS);
if (ret == 0) {
dw9714_dev.number_of_steps =
DW9714_DEFAULT_FOCUS_POS - dw9714_dev.focus;
dw9714_dev.focus = DW9714_DEFAULT_FOCUS_POS;
getnstimeofday(&(dw9714_dev.timestamp_t_focus_abs));
}
return ret;
}
int dw9714_t_focus_rel(struct v4l2_subdev *sd, s32 value)
{
return dw9714_t_focus_abs(sd, dw9714_dev.focus + value);
}
int dw9714_q_focus_status(struct v4l2_subdev *sd, s32 *value)
{
u32 status = 0;
struct timespec temptime;
const struct timespec timedelay = {
0,
min_t(u32, abs(dw9714_dev.number_of_steps)*DELAY_PER_STEP_NS,
DELAY_MAX_PER_STEP_NS),
};
ktime_get_ts(&temptime);
temptime = timespec_sub(temptime, (dw9714_dev.timestamp_t_focus_abs));
if (timespec_compare(&temptime, &timedelay) <= 0) {
status |= ATOMISP_FOCUS_STATUS_MOVING;
status |= ATOMISP_FOCUS_HP_IN_PROGRESS;
} else {
status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE;
status |= ATOMISP_FOCUS_HP_COMPLETE;
}
*value = status;
return 0;
}
int dw9714_q_focus_abs(struct v4l2_subdev *sd, s32 *value)
{
s32 val;
dw9714_q_focus_status(sd, &val);
if (val & ATOMISP_FOCUS_STATUS_MOVING)
*value = dw9714_dev.focus - dw9714_dev.number_of_steps;
else
*value = dw9714_dev.focus;
return 0;
}
int dw9714_t_vcm_slew(struct v4l2_subdev *sd, s32 value)
{
dw9714_dev.vcm_settings.step_setting = value;
dw9714_dev.vcm_settings.update = true;
return 0;
}
int dw9714_t_vcm_timing(struct v4l2_subdev *sd, s32 value)
{
dw9714_dev.vcm_settings.t_src = value;
dw9714_dev.vcm_settings.update = true;
return 0;
}
int dw9714_vcm_init(struct v4l2_subdev *sd)
{
/* set VCM to home position and vcm mode to direct*/
dw9714_dev.vcm_mode = DW9714_DIRECT;
dw9714_dev.vcm_settings.update = false;
dw9714_dev.platform_data = camera_get_af_platform_data();
return (NULL == dw9714_dev.platform_data) ? -ENODEV : 0;
}

63
drivers/staging/media/atomisp/i2c/imx/dw9714.h Normal file
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#ifndef __DW9714_H__
#define __DW9714_H__
#include <linux/atomisp_platform.h>
#include <linux/types.h>
#define DW9714_VCM_ADDR 0x0c
enum dw9714_tok_type {
DW9714_8BIT = 0x0001,
DW9714_16BIT = 0x0002,
};
struct dw9714_vcm_settings {
u16 code; /* bit[9:0]: Data[9:0] */
u8 t_src; /* bit[4:0]: T_SRC[4:0] */
u8 step_setting; /* bit[3:0]: S[3:0]/bit[5:4]: MCLK[1:0] */
bool update;
};
enum dw9714_vcm_mode {
DW9714_DIRECT = 0x1, /* direct control */
DW9714_LSC = 0x2, /* linear slope control */
DW9714_DLC = 0x3, /* dual level control */
};
/* dw9714 device structure */
struct dw9714_device {
struct dw9714_vcm_settings vcm_settings;
struct timespec timestamp_t_focus_abs;
enum dw9714_vcm_mode vcm_mode;
s16 number_of_steps;
bool initialized; /* true if dw9714 is detected */
s32 focus; /* Current focus value */
struct timespec focus_time; /* Time when focus was last time set */
__u8 buffer[4]; /* Used for i2c transactions */
const struct camera_af_platform_data *platform_data;
};
#define DW9714_INVALID_CONFIG 0xffffffff
#define DW9714_MAX_FOCUS_POS 1023
#define DW9714_DEFAULT_FOCUS_POS 290
/* MCLK[1:0] = 01 T_SRC[4:0] = 00001 S[3:0] = 0111 */
#define DELAY_PER_STEP_NS 1000000
#define DELAY_MAX_PER_STEP_NS (1000000 * 1023)
#define DLC_ENABLE 1
#define DLC_DISABLE 0
#define VCM_PROTECTION_OFF 0xeca3
#define VCM_PROTECTION_ON 0xdc51
#define VCM_DEFAULT_S 0x0
#define vcm_step_s(a) (u8)(a & 0xf)
#define vcm_step_mclk(a) (u8)((a >> 4) & 0x3)
#define vcm_dlc_mclk(dlc, mclk) (u16)((dlc << 3) | mclk | 0xa104)
#define vcm_tsrc(tsrc) (u16)(tsrc << 3 | 0xf200)
#define vcm_val(data, s) (u16)(data << 4 | s)
#define DIRECT_VCM vcm_dlc_mclk(0, 0)
#endif

238
drivers/staging/media/atomisp/i2c/imx/dw9718.c Normal file
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/*
* Support for dw9718 vcm driver.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/delay.h>
#include "dw9718.h"
static struct dw9718_device dw9718_dev;
static int dw9718_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val)
{
struct i2c_msg msg[2];
u8 buf[2] = { reg };
msg[0].addr = DW9718_VCM_ADDR;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = buf;
msg[1].addr = DW9718_VCM_ADDR;
msg[1].flags = I2C_M_RD;
msg[1].len = 1;
msg[1].buf = &buf[1];
*val = 0;
if (i2c_transfer(client->adapter, msg, 2) != 2)
return -EIO;
*val = buf[1];
return 0;
}
static int dw9718_i2c_wr8(struct i2c_client *client, u8 reg, u8 val)
{
struct i2c_msg msg;
u8 buf[2] = { reg, val};
msg.addr = DW9718_VCM_ADDR;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(client->adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
static int dw9718_i2c_wr16(struct i2c_client *client, u8 reg, u16 val)
{
struct i2c_msg msg;
u8 buf[3] = { reg, (u8)(val >> 8), (u8)(val & 0xff)};
msg.addr = DW9718_VCM_ADDR;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(client->adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
value = clamp(value, 0, DW9718_MAX_FOCUS_POS);
ret = dw9718_i2c_wr16(client, DW9718_DATA_M, value);
/*pr_info("%s: value = %d\n", __func__, value);*/
if (ret < 0)
return ret;
getnstimeofday(&dw9718_dev.focus_time);
dw9718_dev.focus = value;
return 0;
}
int dw9718_vcm_power_up(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
u8 value;
if (dw9718_dev.power_on)
return 0;
/* Enable power */
ret = dw9718_dev.platform_data->power_ctrl(sd, 1);
if (ret) {
dev_err(&client->dev, "DW9718_PD power_ctrl failed %d\n", ret);
return ret;
}
/* Wait for VBAT to stabilize */
udelay(100);
/* Detect device */
ret = dw9718_i2c_rd8(client, DW9718_SACT, &value);
if (ret < 0) {
dev_err(&client->dev, "read DW9718_SACT failed %d\n", ret);
goto fail_powerdown;
}
/*
* WORKAROUND: for module P8V12F-203 which are used on
* Cherrytrail Refresh Davis Reef AoB, register SACT is not
* returning default value as spec. But VCM works as expected and
* root cause is still under discussion with vendor.
* workaround here to avoid aborting the power up sequence and just
* give a warning about this error.
*/
if (value != DW9718_SACT_DEFAULT_VAL)
dev_warn(&client->dev, "%s error, incorrect ID\n", __func__);
/* Initialize according to recommended settings */
ret = dw9718_i2c_wr8(client, DW9718_CONTROL,
DW9718_CONTROL_SW_LINEAR |
DW9718_CONTROL_S_SAC4 |
DW9718_CONTROL_OCP_DISABLE |
DW9718_CONTROL_UVLO_DISABLE);
if (ret < 0) {
dev_err(&client->dev, "write DW9718_CONTROL failed %d\n", ret);
goto fail_powerdown;
}
ret = dw9718_i2c_wr8(client, DW9718_SACT,
DW9718_SACT_MULT_TWO |
DW9718_SACT_PERIOD_8_8MS);
if (ret < 0) {
dev_err(&client->dev, "write DW9718_SACT failed %d\n", ret);
goto fail_powerdown;
}
ret = dw9718_t_focus_abs(sd, dw9718_dev.focus);
if (ret)
return ret;
dw9718_dev.initialized = true;
dw9718_dev.power_on = 1;
return 0;
fail_powerdown:
dev_err(&client->dev, "%s error, powerup failed\n", __func__);
dw9718_dev.platform_data->power_ctrl(sd, 0);
return ret;
}
int dw9718_vcm_power_down(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
if (!dw9718_dev.power_on)
return 0;
ret = dw9718_dev.platform_data->power_ctrl(sd, 0);
if (ret) {
dev_err(&client->dev, "%s power_ctrl failed\n",
__func__);
return ret;
}
dw9718_dev.power_on = 0;
return 0;
}
int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value)
{
static const struct timespec move_time = {
.tv_sec = 0,
.tv_nsec = 60000000
};
struct timespec current_time, finish_time, delta_time;
getnstimeofday(&current_time);
finish_time = timespec_add(dw9718_dev.focus_time, move_time);
delta_time = timespec_sub(current_time, finish_time);
if (delta_time.tv_sec >= 0 && delta_time.tv_nsec >= 0) {
*value = ATOMISP_FOCUS_HP_COMPLETE |
ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE;
} else {
*value = ATOMISP_FOCUS_STATUS_MOVING |
ATOMISP_FOCUS_HP_IN_PROGRESS;
}
return 0;
}
int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val)
{
return -EINVAL;
}
int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value)
{
return dw9718_t_focus_abs(sd, dw9718_dev.focus + value);
}
int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value)
{
*value = dw9718_dev.focus;
return 0;
}
int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value)
{
return 0;
}
int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value)
{
return 0;
}
int dw9718_vcm_init(struct v4l2_subdev *sd)
{
dw9718_dev.platform_data = camera_get_af_platform_data();
dw9718_dev.focus = DW9718_DEFAULT_FOCUS_POSITION;
dw9718_dev.power_on = 0;
return (NULL == dw9718_dev.platform_data) ? -ENODEV : 0;
}

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/*
* Support for dw9719 vcm driver.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __DW9718_H__
#define __DW9718_H__
#include <linux/atomisp_platform.h>
#include <linux/types.h>
#define DW9718_VCM_ADDR (0x18 >> 1)
/* dw9718 device structure */
struct dw9718_device {
struct timespec timestamp_t_focus_abs;
s16 number_of_steps;
bool initialized; /* true if dw9718 is detected */
s32 focus; /* Current focus value */
struct timespec focus_time; /* Time when focus was last time set */
__u8 buffer[4]; /* Used for i2c transactions */
const struct camera_af_platform_data *platform_data;
__u8 power_on;
};
#define DW9718_MAX_FOCUS_POS 1023
/* Register addresses */
#define DW9718_PD 0x00
#define DW9718_CONTROL 0x01
#define DW9718_DATA_M 0x02
#define DW9718_DATA_L 0x03
#define DW9718_SW 0x04
#define DW9718_SACT 0x05
#define DW9718_FLAG 0x10
#define DW9718_CONTROL_SW_LINEAR BIT(0)
#define DW9718_CONTROL_S_SAC4 (BIT(1) | BIT(3))
#define DW9718_CONTROL_OCP_DISABLE BIT(4)
#define DW9718_CONTROL_UVLO_DISABLE BIT(5)
#define DW9718_SACT_MULT_TWO 0x00
#define DW9718_SACT_PERIOD_8_8MS 0x19
#define DW9718_SACT_DEFAULT_VAL 0x60
#define DW9718_DEFAULT_FOCUS_POSITION 300
#endif /* __DW9718_H__ */

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/*
* Support for dw9719 vcm driver.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/delay.h>
#include "dw9719.h"
static struct dw9719_device dw9719_dev;
static int dw9719_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val)
{
struct i2c_msg msg[2];
u8 buf[2] = { reg };
msg[0].addr = DW9719_VCM_ADDR;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = buf;
msg[1].addr = DW9719_VCM_ADDR;
msg[1].flags = I2C_M_RD;
msg[1].len = 1;
msg[1].buf = &buf[1];
*val = 0;
if (i2c_transfer(client->adapter, msg, 2) != 2)
return -EIO;
*val = buf[1];
return 0;
}
static int dw9719_i2c_wr8(struct i2c_client *client, u8 reg, u8 val)
{
struct i2c_msg msg;
u8 buf[2] = { reg, val };
msg.addr = DW9719_VCM_ADDR;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(client->adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
static int dw9719_i2c_wr16(struct i2c_client *client, u8 reg, u16 val)
{
struct i2c_msg msg;
u8 buf[3] = { reg, (u8)(val >> 8), (u8)(val & 0xff)};
msg.addr = DW9719_VCM_ADDR;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(client->adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
int dw9719_vcm_power_up(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
u8 value;
/* Enable power */
ret = dw9719_dev.platform_data->power_ctrl(sd, 1);
/* waiting time requested by DW9714A(vcm) */
if (ret)
return ret;
/* Wait for VBAT to stabilize */
udelay(1);
/*
* Jiggle SCL pin to wake up device.
*/
ret = dw9719_i2c_wr8(client, DW9719_CONTROL, 1);
/* Need 100us to transit from SHUTDOWN to STANDBY*/
usleep_range(100, 1000);
/* Enable the ringing compensation */
ret = dw9719_i2c_wr8(client, DW9719_CONTROL, DW9719_ENABLE_RINGING);
if (ret < 0)
goto fail_powerdown;
/* Use SAC3 mode */
ret = dw9719_i2c_wr8(client, DW9719_MODE, DW9719_MODE_SAC3);
if (ret < 0)
goto fail_powerdown;
/* Set the resonance frequency */
ret = dw9719_i2c_wr8(client, DW9719_VCM_FREQ, DW9719_DEFAULT_VCM_FREQ);
if (ret < 0)
goto fail_powerdown;
/* Detect device */
ret = dw9719_i2c_rd8(client, DW9719_INFO, &value);
if (ret < 0)
goto fail_powerdown;
if (value != DW9719_ID) {
ret = -ENXIO;
goto fail_powerdown;
}
dw9719_dev.focus = 0;
dw9719_dev.initialized = true;
return 0;
fail_powerdown:
dw9719_dev.platform_data->power_ctrl(sd, 0);
return ret;
}
int dw9719_vcm_power_down(struct v4l2_subdev *sd)
{
return dw9719_dev.platform_data->power_ctrl(sd, 0);
}
int dw9719_q_focus_status(struct v4l2_subdev *sd, s32 *value)
{
static const struct timespec move_time = {
.tv_sec = 0,
.tv_nsec = 60000000
};
struct timespec current_time, finish_time, delta_time;
getnstimeofday(&current_time);
finish_time = timespec_add(dw9719_dev.focus_time, move_time);
delta_time = timespec_sub(current_time, finish_time);
if (delta_time.tv_sec >= 0 && delta_time.tv_nsec >= 0) {
*value = ATOMISP_FOCUS_HP_COMPLETE |
ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE;
} else {
*value = ATOMISP_FOCUS_STATUS_MOVING |
ATOMISP_FOCUS_HP_IN_PROGRESS;
}
return 0;
}
int dw9719_t_focus_vcm(struct v4l2_subdev *sd, u16 val)
{
return -EINVAL;
}
int dw9719_t_focus_abs(struct v4l2_subdev *sd, s32 value)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
value = clamp(value, 0, DW9719_MAX_FOCUS_POS);
ret = dw9719_i2c_wr16(client, DW9719_VCM_CURRENT, value);
if (ret < 0)
return ret;
getnstimeofday(&dw9719_dev.focus_time);
dw9719_dev.focus = value;
return 0;
}
int dw9719_t_focus_rel(struct v4l2_subdev *sd, s32 value)
{
return dw9719_t_focus_abs(sd, dw9719_dev.focus + value);
}
int dw9719_q_focus_abs(struct v4l2_subdev *sd, s32 *value)
{
*value = dw9719_dev.focus;
return 0;
}
int dw9719_t_vcm_slew(struct v4l2_subdev *sd, s32 value)
{
return 0;
}
int dw9719_t_vcm_timing(struct v4l2_subdev *sd, s32 value)
{
return 0;
}
int dw9719_vcm_init(struct v4l2_subdev *sd)
{
dw9719_dev.platform_data = camera_get_af_platform_data();
return (NULL == dw9719_dev.platform_data) ? -ENODEV : 0;
}

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/*
* Support for dw9719 vcm driver.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __DW9719_H__
#define __DW9719_H__
#include <linux/atomisp_platform.h>
#include <linux/types.h>
#define DW9719_VCM_ADDR (0x18 >> 1)
/* dw9719 device structure */
struct dw9719_device {
struct timespec timestamp_t_focus_abs;
s16 number_of_steps;
bool initialized; /* true if dw9719 is detected */
s32 focus; /* Current focus value */
struct timespec focus_time; /* Time when focus was last time set */
__u8 buffer[4]; /* Used for i2c transactions */
const struct camera_af_platform_data *platform_data;
};
#define DW9719_INVALID_CONFIG 0xffffffff
#define DW9719_MAX_FOCUS_POS 1023
#define DELAY_PER_STEP_NS 1000000
#define DELAY_MAX_PER_STEP_NS (1000000 * 1023)
#define DW9719_INFO 0
#define DW9719_ID 0xF1
#define DW9719_CONTROL 2
#define DW9719_VCM_CURRENT 3
#define DW9719_MODE 6
#define DW9719_VCM_FREQ 7
#define DW9719_MODE_SAC3 0x40
#define DW9719_DEFAULT_VCM_FREQ 0x04
#define DW9719_ENABLE_RINGING 0x02
#endif

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/*
* Support for Sony IMX camera sensor.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __IMX_H__
#define __IMX_H__
#include <linux/atomisp_platform.h>
#include <linux/atomisp.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/videodev2.h>
#include <linux/v4l2-mediabus.h>
#include <media/media-entity.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include "imx175.h"
#include "imx135.h"
#include "imx134.h"
#include "imx132.h"
#include "imx208.h"
#include "imx219.h"
#include "imx227.h"
#define IMX_MCLK 192
/* TODO - This should be added into include/linux/videodev2.h */
#ifndef V4L2_IDENT_IMX
#define V4L2_IDENT_IMX 8245
#endif
#define IMX_MAX_AE_LUT_LENGTH 5
/*
* imx System control registers
*/
#define IMX_MASK_5BIT 0x1F
#define IMX_MASK_4BIT 0xF
#define IMX_MASK_3BIT 0x7
#define IMX_MASK_2BIT 0x3
#define IMX_MASK_8BIT 0xFF
#define IMX_MASK_11BIT 0x7FF
#define IMX_INTG_BUF_COUNT 2
#define IMX_FINE_INTG_TIME 0x1E8
#define IMX_VT_PIX_CLK_DIV 0x0301
#define IMX_VT_SYS_CLK_DIV 0x0303
#define IMX_PRE_PLL_CLK_DIV 0x0305
#define IMX227_IOP_PRE_PLL_CLK_DIV 0x030D
#define IMX227_PLL_MULTIPLIER 0x0306
#define IMX227_IOP_PLL_MULTIPLIER 0x030E
#define IMX227_PLL_MULTI_DRIVE 0x0310
#define IMX227_OP_PIX_CLK_DIV 0x0309
#define IMX227_OP_SYS_CLK_DIV 0x030B
#define IMX_PLL_MULTIPLIER 0x030C
#define IMX_OP_PIX_DIV 0x0309
#define IMX_OP_SYS_DIV 0x030B
#define IMX_FRAME_LENGTH_LINES 0x0340
#define IMX_LINE_LENGTH_PIXELS 0x0342
#define IMX_COARSE_INTG_TIME_MIN 0x1004
#define IMX_COARSE_INTG_TIME_MAX 0x1006
#define IMX_BINNING_ENABLE 0x0390
#define IMX227_BINNING_ENABLE 0x0900
#define IMX_BINNING_TYPE 0x0391
#define IMX227_BINNING_TYPE 0x0901
#define IMX_READ_MODE 0x0390
#define IMX227_READ_MODE 0x0900
#define IMX_HORIZONTAL_START_H 0x0344
#define IMX_VERTICAL_START_H 0x0346
#define IMX_HORIZONTAL_END_H 0x0348
#define IMX_VERTICAL_END_H 0x034a
#define IMX_HORIZONTAL_OUTPUT_SIZE_H 0x034c
#define IMX_VERTICAL_OUTPUT_SIZE_H 0x034e
/* Post Divider setting register for imx132 and imx208 */
#define IMX132_208_VT_RGPLTD 0x30A4
/* Multiplier setting register for imx132, imx208, and imx219 */
#define IMX132_208_219_PLL_MULTIPLIER 0x0306
#define IMX_COARSE_INTEGRATION_TIME 0x0202
#define IMX_TEST_PATTERN_MODE 0x0600
#define IMX_TEST_PATTERN_COLOR_R 0x0602
#define IMX_TEST_PATTERN_COLOR_GR 0x0604
#define IMX_TEST_PATTERN_COLOR_B 0x0606
#define IMX_TEST_PATTERN_COLOR_GB 0x0608
#define IMX_IMG_ORIENTATION 0x0101
#define IMX_VFLIP_BIT 2
#define IMX_HFLIP_BIT 1
#define IMX_GLOBAL_GAIN 0x0205
#define IMX_SHORT_AGC_GAIN 0x0233
#define IMX_DGC_ADJ 0x020E
#define IMX_DGC_LEN 10
#define IMX227_DGC_LEN 4
#define IMX_MAX_EXPOSURE_SUPPORTED 0xfffb
#define IMX_MAX_GLOBAL_GAIN_SUPPORTED 0x00ff
#define IMX_MAX_DIGITAL_GAIN_SUPPORTED 0x0fff
#define MAX_FMTS 1
#define IMX_OTP_DATA_SIZE 1280
#define IMX_SUBDEV_PREFIX "imx"
#define IMX_DRIVER "imx1x5"
/* Sensor ids from identification register */
#define IMX_NAME_134 "imx134"
#define IMX_NAME_135 "imx135"
#define IMX_NAME_175 "imx175"
#define IMX_NAME_132 "imx132"
#define IMX_NAME_208 "imx208"
#define IMX_NAME_219 "imx219"
#define IMX_NAME_227 "imx227"
#define IMX175_ID 0x0175
#define IMX135_ID 0x0135
#define IMX134_ID 0x0134
#define IMX132_ID 0x0132
#define IMX208_ID 0x0208
#define IMX219_ID 0x0219
#define IMX227_ID 0x0227
/* Sensor id based on i2c_device_id table
* (Fuji module can not be detected based on sensor registers) */
#define IMX135_FUJI_ID 0x0136
#define IMX_NAME_135_FUJI "imx135fuji"
/* imx175 - use dw9714 vcm */
#define IMX175_MERRFLD 0x175
#define IMX175_VALLEYVIEW 0x176
#define IMX135_SALTBAY 0x135
#define IMX135_VICTORIABAY 0x136
#define IMX132_SALTBAY 0x132
#define IMX134_VALLEYVIEW 0x134
#define IMX208_MOFD_PD2 0x208
#define IMX219_MFV0_PRH 0x219
#define IMX227_SAND 0x227
/* otp - specific settings */
#define E2PROM_ADDR 0xa0
#define E2PROM_LITEON_12P1BA869D_ADDR 0xa0
#define E2PROM_ABICO_SS89A839_ADDR 0xa8
#define DEFAULT_OTP_SIZE 1280
#define IMX135_OTP_SIZE 1280
#define IMX219_OTP_SIZE 2048
#define IMX227_OTP_SIZE 2560
#define E2PROM_LITEON_12P1BA869D_SIZE 544
#define IMX_ID_DEFAULT 0x0000
#define IMX132_175_208_219_CHIP_ID 0x0000
#define IMX134_135_CHIP_ID 0x0016
#define IMX134_135_227_CHIP_ID 0x0016
#define IMX175_RES_WIDTH_MAX 3280
#define IMX175_RES_HEIGHT_MAX 2464
#define IMX135_RES_WIDTH_MAX 4208
#define IMX135_RES_HEIGHT_MAX 3120
#define IMX132_RES_WIDTH_MAX 1936
#define IMX132_RES_HEIGHT_MAX 1096
#define IMX134_RES_WIDTH_MAX 3280
#define IMX134_RES_HEIGHT_MAX 2464
#define IMX208_RES_WIDTH_MAX 1936
#define IMX208_RES_HEIGHT_MAX 1096
#define IMX219_RES_WIDTH_MAX 3280
#define IMX219_RES_HEIGHT_MAX 2464
#define IMX227_RES_WIDTH_MAX 2400
#define IMX227_RES_HEIGHT_MAX 2720
/* Defines for lens/VCM */
#define IMX_FOCAL_LENGTH_NUM 369 /*3.69mm*/
#define IMX_FOCAL_LENGTH_DEM 100
#define IMX_F_NUMBER_DEFAULT_NUM 22
#define IMX_F_NUMBER_DEM 10
#define IMX_INVALID_CONFIG 0xffffffff
#define IMX_MAX_FOCUS_POS 1023
#define IMX_MAX_FOCUS_NEG (-1023)
#define IMX_VCM_SLEW_STEP_MAX 0x3f
#define IMX_VCM_SLEW_TIME_MAX 0x1f
#define IMX_BIN_FACTOR_MAX 4
#define IMX_INTEGRATION_TIME_MARGIN 4
/*
* focal length bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define IMX_FOCAL_LENGTH_DEFAULT 0x1710064
/*
* current f-number bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define IMX_F_NUMBER_DEFAULT 0x16000a
/*
* f-number range bits definition:
* bits 31-24: max f-number numerator
* bits 23-16: max f-number denominator
* bits 15-8: min f-number numerator
* bits 7-0: min f-number denominator
*/
#define IMX_F_NUMBER_RANGE 0x160a160a
struct imx_vcm {
int (*power_up)(struct v4l2_subdev *sd);
int (*power_down)(struct v4l2_subdev *sd);
int (*init)(struct v4l2_subdev *sd);
int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val);
int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value);
int (*t_focus_abs_init)(struct v4l2_subdev *sd);
int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value);
int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value);
int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value);
int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value);
int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value);
};
struct imx_otp {
void * (*otp_read)(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size);
u32 start_addr;
u32 size;
u8 dev_addr;
};
struct max_res {
int res_max_width;
int res_max_height;
};
struct max_res imx_max_res[] = {
[IMX175_ID] = {
.res_max_width = IMX175_RES_WIDTH_MAX,
.res_max_height = IMX175_RES_HEIGHT_MAX,
},
[IMX135_ID] = {
.res_max_width = IMX135_RES_WIDTH_MAX,
.res_max_height = IMX135_RES_HEIGHT_MAX,
},
[IMX132_ID] = {
.res_max_width = IMX132_RES_WIDTH_MAX,
.res_max_height = IMX132_RES_HEIGHT_MAX,
},
[IMX134_ID] = {
.res_max_width = IMX134_RES_WIDTH_MAX,
.res_max_height = IMX134_RES_HEIGHT_MAX,
},
[IMX208_ID] = {
.res_max_width = IMX208_RES_WIDTH_MAX,
.res_max_height = IMX208_RES_HEIGHT_MAX,
},
[IMX219_ID] = {
.res_max_width = IMX219_RES_WIDTH_MAX,
.res_max_height = IMX219_RES_HEIGHT_MAX,
},
[IMX227_ID] = {
.res_max_width = IMX227_RES_WIDTH_MAX,
.res_max_height = IMX227_RES_HEIGHT_MAX,
},
};
struct imx_settings {
struct imx_reg const *init_settings;
struct imx_resolution *res_preview;
struct imx_resolution *res_still;
struct imx_resolution *res_video;
int n_res_preview;
int n_res_still;
int n_res_video;
};
struct imx_settings imx_sets[] = {
[IMX175_MERRFLD] = {
.init_settings = imx175_init_settings,
.res_preview = imx175_res_preview,
.res_still = imx175_res_still,
.res_video = imx175_res_video,
.n_res_preview = ARRAY_SIZE(imx175_res_preview),
.n_res_still = ARRAY_SIZE(imx175_res_still),
.n_res_video = ARRAY_SIZE(imx175_res_video),
},
[IMX175_VALLEYVIEW] = {
.init_settings = imx175_init_settings,
.res_preview = imx175_res_preview,
.res_still = imx175_res_still,
.res_video = imx175_res_video,
.n_res_preview = ARRAY_SIZE(imx175_res_preview),
.n_res_still = ARRAY_SIZE(imx175_res_still),
.n_res_video = ARRAY_SIZE(imx175_res_video),
},
[IMX135_SALTBAY] = {
.init_settings = imx135_init_settings,
.res_preview = imx135_res_preview,
.res_still = imx135_res_still,
.res_video = imx135_res_video,
.n_res_preview = ARRAY_SIZE(imx135_res_preview),
.n_res_still = ARRAY_SIZE(imx135_res_still),
.n_res_video = ARRAY_SIZE(imx135_res_video),
},
[IMX135_VICTORIABAY] = {
.init_settings = imx135_init_settings,
.res_preview = imx135_res_preview_mofd,
.res_still = imx135_res_still_mofd,
.res_video = imx135_res_video,
.n_res_preview = ARRAY_SIZE(imx135_res_preview_mofd),
.n_res_still = ARRAY_SIZE(imx135_res_still_mofd),
.n_res_video = ARRAY_SIZE(imx135_res_video),
},
[IMX132_SALTBAY] = {
.init_settings = imx132_init_settings,
.res_preview = imx132_res_preview,
.res_still = imx132_res_still,
.res_video = imx132_res_video,
.n_res_preview = ARRAY_SIZE(imx132_res_preview),
.n_res_still = ARRAY_SIZE(imx132_res_still),
.n_res_video = ARRAY_SIZE(imx132_res_video),
},
[IMX134_VALLEYVIEW] = {
.init_settings = imx134_init_settings,
.res_preview = imx134_res_preview,
.res_still = imx134_res_still,
.res_video = imx134_res_video,
.n_res_preview = ARRAY_SIZE(imx134_res_preview),
.n_res_still = ARRAY_SIZE(imx134_res_still),
.n_res_video = ARRAY_SIZE(imx134_res_video),
},
[IMX208_MOFD_PD2] = {
.init_settings = imx208_init_settings,
.res_preview = imx208_res_preview,
.res_still = imx208_res_still,
.res_video = imx208_res_video,
.n_res_preview = ARRAY_SIZE(imx208_res_preview),
.n_res_still = ARRAY_SIZE(imx208_res_still),
.n_res_video = ARRAY_SIZE(imx208_res_video),
},
[IMX219_MFV0_PRH] = {
.init_settings = imx219_init_settings,
.res_preview = imx219_res_preview,
.res_still = imx219_res_still,
.res_video = imx219_res_video,
.n_res_preview = ARRAY_SIZE(imx219_res_preview),
.n_res_still = ARRAY_SIZE(imx219_res_still),
.n_res_video = ARRAY_SIZE(imx219_res_video),
},
[IMX227_SAND] = {
.init_settings = imx227_init_settings,
.res_preview = imx227_res_preview,
.res_still = imx227_res_still,
.res_video = imx227_res_video,
.n_res_preview = ARRAY_SIZE(imx227_res_preview),
.n_res_still = ARRAY_SIZE(imx227_res_still),
.n_res_video = ARRAY_SIZE(imx227_res_video),
},
};
struct imx_reg_addr {
u16 frame_length_lines;
u16 line_length_pixels;
u16 horizontal_start_h;
u16 vertical_start_h;
u16 horizontal_end_h;
u16 vertical_end_h;
u16 horizontal_output_size_h;
u16 vertical_output_size_h;
u16 coarse_integration_time;
u16 img_orientation;
u16 global_gain;
u16 dgc_adj;
};
struct imx_reg_addr imx_addr = {
IMX_FRAME_LENGTH_LINES,
IMX_LINE_LENGTH_PIXELS,
IMX_HORIZONTAL_START_H,
IMX_VERTICAL_START_H,
IMX_HORIZONTAL_END_H,
IMX_VERTICAL_END_H,
IMX_HORIZONTAL_OUTPUT_SIZE_H,
IMX_VERTICAL_OUTPUT_SIZE_H,
IMX_COARSE_INTEGRATION_TIME,
IMX_IMG_ORIENTATION,
IMX_GLOBAL_GAIN,
IMX_DGC_ADJ,
};
struct imx_reg_addr imx219_addr = {
IMX219_FRAME_LENGTH_LINES,
IMX219_LINE_LENGTH_PIXELS,
IMX219_HORIZONTAL_START_H,
IMX219_VERTICAL_START_H,
IMX219_HORIZONTAL_END_H,
IMX219_VERTICAL_END_H,
IMX219_HORIZONTAL_OUTPUT_SIZE_H,
IMX219_VERTICAL_OUTPUT_SIZE_H,
IMX219_COARSE_INTEGRATION_TIME,
IMX219_IMG_ORIENTATION,
IMX219_GLOBAL_GAIN,
IMX219_DGC_ADJ,
};
#define v4l2_format_capture_type_entry(_width, _height, \
_pixelformat, _bytesperline, _colorspace) \
{\
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,\
.fmt.pix.width = (_width),\
.fmt.pix.height = (_height),\
.fmt.pix.pixelformat = (_pixelformat),\
.fmt.pix.bytesperline = (_bytesperline),\
.fmt.pix.colorspace = (_colorspace),\
.fmt.pix.sizeimage = (_height)*(_bytesperline),\
}
#define s_output_format_entry(_width, _height, _pixelformat, \
_bytesperline, _colorspace, _fps) \
{\
.v4l2_fmt = v4l2_format_capture_type_entry(_width, \
_height, _pixelformat, _bytesperline, \
_colorspace),\
.fps = (_fps),\
}
#define s_output_format_reg_entry(_width, _height, _pixelformat, \
_bytesperline, _colorspace, _fps, _reg_setting) \
{\
.s_fmt = s_output_format_entry(_width, _height,\
_pixelformat, _bytesperline, \
_colorspace, _fps),\
.reg_setting = (_reg_setting),\
}
/* imx device structure */
struct imx_device {
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_mbus_framefmt format;
struct camera_sensor_platform_data *platform_data;
struct mutex input_lock; /* serialize sensor's ioctl */
int fmt_idx;
int status;
int streaming;
int power;
int run_mode;
int vt_pix_clk_freq_mhz;
int fps_index;
u32 focus;
u16 sensor_id; /* Sensor id from registers */
u16 i2c_id; /* Sensor id from i2c_device_id */
u16 coarse_itg;
u16 fine_itg;
u16 digital_gain;
u16 gain;
u16 pixels_per_line;
u16 lines_per_frame;
u8 targetfps;
u8 fps;
const struct imx_reg *regs;
u8 res;
u8 type;
u8 sensor_revision;
u8 *otp_data;
struct imx_settings *mode_tables;
struct imx_vcm *vcm_driver;
struct imx_otp *otp_driver;
const struct imx_resolution *curr_res_table;
int entries_curr_table;
const struct firmware *fw;
struct imx_reg_addr *reg_addr;
const struct imx_reg *param_hold;
const struct imx_reg *param_update;
/* used for h/b blank tuning */
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_ctrl *pixel_rate;
struct v4l2_ctrl *h_blank;
struct v4l2_ctrl *v_blank;
struct v4l2_ctrl *link_freq;
struct v4l2_ctrl *h_flip;
struct v4l2_ctrl *v_flip;
/* Test pattern control */
struct v4l2_ctrl *tp_mode;
struct v4l2_ctrl *tp_r;
struct v4l2_ctrl *tp_gr;
struct v4l2_ctrl *tp_gb;
struct v4l2_ctrl *tp_b;
/* FIXME! */
bool new_res_sel_method;
};
#define to_imx_sensor(x) container_of(x, struct imx_device, sd)
#define IMX_MAX_WRITE_BUF_SIZE 32
struct imx_write_buffer {
u16 addr;
u8 data[IMX_MAX_WRITE_BUF_SIZE];
};
struct imx_write_ctrl {
int index;
struct imx_write_buffer buffer;
};
static const struct imx_reg imx_soft_standby[] = {
{IMX_8BIT, 0x0100, 0x00},
{IMX_TOK_TERM, 0, 0}
};
static const struct imx_reg imx_streaming[] = {
{IMX_8BIT, 0x0100, 0x01},
{IMX_TOK_TERM, 0, 0}
};
static const struct imx_reg imx_param_hold[] = {
{IMX_8BIT, 0x0104, 0x01}, /* GROUPED_PARAMETER_HOLD */
{IMX_TOK_TERM, 0, 0}
};
static const struct imx_reg imx_param_update[] = {
{IMX_8BIT, 0x0104, 0x00}, /* GROUPED_PARAMETER_HOLD */
{IMX_TOK_TERM, 0, 0}
};
static const struct imx_reg imx219_param_hold[] = {
{IMX_TOK_TERM, 0, 0}
};
static const struct imx_reg imx219_param_update[] = {
{IMX_TOK_TERM, 0, 0}
};
extern int ad5816g_vcm_power_up(struct v4l2_subdev *sd);
extern int ad5816g_vcm_power_down(struct v4l2_subdev *sd);
extern int ad5816g_vcm_init(struct v4l2_subdev *sd);
extern int ad5816g_t_focus_vcm(struct v4l2_subdev *sd, u16 val);
extern int ad5816g_t_focus_abs(struct v4l2_subdev *sd, s32 value);
extern int ad5816g_t_focus_rel(struct v4l2_subdev *sd, s32 value);
extern int ad5816g_q_focus_status(struct v4l2_subdev *sd, s32 *value);
extern int ad5816g_q_focus_abs(struct v4l2_subdev *sd, s32 *value);
extern int ad5816g_t_vcm_slew(struct v4l2_subdev *sd, s32 value);
extern int ad5816g_t_vcm_timing(struct v4l2_subdev *sd, s32 value);
extern int drv201_vcm_power_up(struct v4l2_subdev *sd);
extern int drv201_vcm_power_down(struct v4l2_subdev *sd);
extern int drv201_vcm_init(struct v4l2_subdev *sd);
extern int drv201_t_focus_vcm(struct v4l2_subdev *sd, u16 val);
extern int drv201_t_focus_abs(struct v4l2_subdev *sd, s32 value);
extern int drv201_t_focus_rel(struct v4l2_subdev *sd, s32 value);
extern int drv201_q_focus_status(struct v4l2_subdev *sd, s32 *value);
extern int drv201_q_focus_abs(struct v4l2_subdev *sd, s32 *value);
extern int drv201_t_vcm_slew(struct v4l2_subdev *sd, s32 value);
extern int drv201_t_vcm_timing(struct v4l2_subdev *sd, s32 value);
extern int dw9714_vcm_power_up(struct v4l2_subdev *sd);
extern int dw9714_vcm_power_down(struct v4l2_subdev *sd);
extern int dw9714_vcm_init(struct v4l2_subdev *sd);
extern int dw9714_t_focus_vcm(struct v4l2_subdev *sd, u16 val);
extern int dw9714_t_focus_abs(struct v4l2_subdev *sd, s32 value);
extern int dw9714_t_focus_abs_init(struct v4l2_subdev *sd);
extern int dw9714_t_focus_rel(struct v4l2_subdev *sd, s32 value);
extern int dw9714_q_focus_status(struct v4l2_subdev *sd, s32 *value);
extern int dw9714_q_focus_abs(struct v4l2_subdev *sd, s32 *value);
extern int dw9714_t_vcm_slew(struct v4l2_subdev *sd, s32 value);
extern int dw9714_t_vcm_timing(struct v4l2_subdev *sd, s32 value);
extern int dw9719_vcm_power_up(struct v4l2_subdev *sd);
extern int dw9719_vcm_power_down(struct v4l2_subdev *sd);
extern int dw9719_vcm_init(struct v4l2_subdev *sd);
extern int dw9719_t_focus_vcm(struct v4l2_subdev *sd, u16 val);
extern int dw9719_t_focus_abs(struct v4l2_subdev *sd, s32 value);
extern int dw9719_t_focus_rel(struct v4l2_subdev *sd, s32 value);
extern int dw9719_q_focus_status(struct v4l2_subdev *sd, s32 *value);
extern int dw9719_q_focus_abs(struct v4l2_subdev *sd, s32 *value);
extern int dw9719_t_vcm_slew(struct v4l2_subdev *sd, s32 value);
extern int dw9719_t_vcm_timing(struct v4l2_subdev *sd, s32 value);
extern int dw9718_vcm_power_up(struct v4l2_subdev *sd);
extern int dw9718_vcm_power_down(struct v4l2_subdev *sd);
extern int dw9718_vcm_init(struct v4l2_subdev *sd);
extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val);
extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value);
extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value);
extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value);
extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value);
extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value);
extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value);
extern int vcm_power_up(struct v4l2_subdev *sd);
extern int vcm_power_down(struct v4l2_subdev *sd);
struct imx_vcm imx_vcms[] = {
[IMX175_MERRFLD] = {
.power_up = drv201_vcm_power_up,
.power_down = drv201_vcm_power_down,
.init = drv201_vcm_init,
.t_focus_vcm = drv201_t_focus_vcm,
.t_focus_abs = drv201_t_focus_abs,
.t_focus_abs_init = NULL,
.t_focus_rel = drv201_t_focus_rel,
.q_focus_status = drv201_q_focus_status,
.q_focus_abs = drv201_q_focus_abs,
.t_vcm_slew = drv201_t_vcm_slew,
.t_vcm_timing = drv201_t_vcm_timing,
},
[IMX175_VALLEYVIEW] = {
.power_up = dw9714_vcm_power_up,
.power_down = dw9714_vcm_power_down,
.init = dw9714_vcm_init,
.t_focus_vcm = dw9714_t_focus_vcm,
.t_focus_abs = dw9714_t_focus_abs,
.t_focus_abs_init = NULL,
.t_focus_rel = dw9714_t_focus_rel,
.q_focus_status = dw9714_q_focus_status,
.q_focus_abs = dw9714_q_focus_abs,
.t_vcm_slew = dw9714_t_vcm_slew,
.t_vcm_timing = dw9714_t_vcm_timing,
},
[IMX135_SALTBAY] = {
.power_up = ad5816g_vcm_power_up,
.power_down = ad5816g_vcm_power_down,
.init = ad5816g_vcm_init,
.t_focus_vcm = ad5816g_t_focus_vcm,
.t_focus_abs = ad5816g_t_focus_abs,
.t_focus_abs_init = NULL,
.t_focus_rel = ad5816g_t_focus_rel,
.q_focus_status = ad5816g_q_focus_status,
.q_focus_abs = ad5816g_q_focus_abs,
.t_vcm_slew = ad5816g_t_vcm_slew,
.t_vcm_timing = ad5816g_t_vcm_timing,
},
[IMX135_VICTORIABAY] = {
.power_up = dw9719_vcm_power_up,
.power_down = dw9719_vcm_power_down,
.init = dw9719_vcm_init,
.t_focus_vcm = dw9719_t_focus_vcm,
.t_focus_abs = dw9719_t_focus_abs,
.t_focus_abs_init = NULL,
.t_focus_rel = dw9719_t_focus_rel,
.q_focus_status = dw9719_q_focus_status,
.q_focus_abs = dw9719_q_focus_abs,
.t_vcm_slew = dw9719_t_vcm_slew,
.t_vcm_timing = dw9719_t_vcm_timing,
},
[IMX134_VALLEYVIEW] = {
.power_up = dw9714_vcm_power_up,
.power_down = dw9714_vcm_power_down,
.init = dw9714_vcm_init,
.t_focus_vcm = dw9714_t_focus_vcm,
.t_focus_abs = dw9714_t_focus_abs,
.t_focus_abs_init = dw9714_t_focus_abs_init,
.t_focus_rel = dw9714_t_focus_rel,
.q_focus_status = dw9714_q_focus_status,
.q_focus_abs = dw9714_q_focus_abs,
.t_vcm_slew = dw9714_t_vcm_slew,
.t_vcm_timing = dw9714_t_vcm_timing,
},
[IMX219_MFV0_PRH] = {
.power_up = dw9718_vcm_power_up,
.power_down = dw9718_vcm_power_down,
.init = dw9718_vcm_init,
.t_focus_vcm = dw9718_t_focus_vcm,
.t_focus_abs = dw9718_t_focus_abs,
.t_focus_abs_init = NULL,
.t_focus_rel = dw9718_t_focus_rel,
.q_focus_status = dw9718_q_focus_status,
.q_focus_abs = dw9718_q_focus_abs,
.t_vcm_slew = dw9718_t_vcm_slew,
.t_vcm_timing = dw9718_t_vcm_timing,
},
[IMX_ID_DEFAULT] = {
.power_up = NULL,
.power_down = NULL,
.t_focus_abs_init = NULL,
},
};
extern void *dummy_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size);
extern void *imx_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size);
extern void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size);
extern void *brcc064_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size);
extern void *imx227_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size);
extern void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size);
struct imx_otp imx_otps[] = {
[IMX175_MERRFLD] = {
.otp_read = imx_otp_read,
.dev_addr = E2PROM_ADDR,
.start_addr = 0,
.size = DEFAULT_OTP_SIZE,
},
[IMX175_VALLEYVIEW] = {
.otp_read = e2prom_otp_read,
.dev_addr = E2PROM_ABICO_SS89A839_ADDR,
.start_addr = E2PROM_2ADDR,
.size = DEFAULT_OTP_SIZE,
},
[IMX135_SALTBAY] = {
.otp_read = e2prom_otp_read,
.dev_addr = E2PROM_ADDR,
.start_addr = 0,
.size = DEFAULT_OTP_SIZE,
},
[IMX135_VICTORIABAY] = {
.otp_read = imx_otp_read,
.size = DEFAULT_OTP_SIZE,
},
[IMX134_VALLEYVIEW] = {
.otp_read = e2prom_otp_read,
.dev_addr = E2PROM_LITEON_12P1BA869D_ADDR,
.start_addr = 0,
.size = E2PROM_LITEON_12P1BA869D_SIZE,
},
[IMX132_SALTBAY] = {
.otp_read = dummy_otp_read,
.size = DEFAULT_OTP_SIZE,
},
[IMX208_MOFD_PD2] = {
.otp_read = dummy_otp_read,
.size = DEFAULT_OTP_SIZE,
},
[IMX219_MFV0_PRH] = {
.otp_read = brcc064_otp_read,
.dev_addr = E2PROM_ADDR,
.start_addr = 0,
.size = IMX219_OTP_SIZE,
},
[IMX227_SAND] = {
.otp_read = imx227_otp_read,
.size = IMX227_OTP_SIZE,
},
[IMX_ID_DEFAULT] = {
.otp_read = dummy_otp_read,
.size = DEFAULT_OTP_SIZE,
},
};
#endif

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drivers/staging/media/atomisp/i2c/imx/imx132.h Normal file
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@ -0,0 +1,566 @@
/*
* Support for Sony IMX camera sensor.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __IMX132_H__
#define __IMX132_H__
#include "common.h"
/********************** registers define ********************************/
#define IMX132_RGLANESEL 0x3301 /* Number of lanes */
#define IMX132_RGLANESEL_1LANE 0x01
#define IMX132_RGLANESEL_2LANES 0x00
#define IMX132_RGLANESEL_4LANES 0x03
#define IMX132_2LANES_GAINFACT 2096 /* 524/256 * 2^10 */
#define IMX132_2LANES_GAINFACT_SHIFT 10
/********************** settings for imx from vendor*********************/
static struct imx_reg imx132_1080p_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
/* Global Settings */
{IMX_8BIT, 0x3087, 0x53},
{IMX_8BIT, 0x308B, 0x5A},
{IMX_8BIT, 0x3094, 0x11},
{IMX_8BIT, 0x309D, 0xA4},
{IMX_8BIT, 0x30AA, 0x01},
{IMX_8BIT, 0x30C6, 0x00},
{IMX_8BIT, 0x30C7, 0x00},
{IMX_8BIT, 0x3118, 0x2F},
{IMX_8BIT, 0x312A, 0x00},
{IMX_8BIT, 0x312B, 0x0B},
{IMX_8BIT, 0x312C, 0x0B},
{IMX_8BIT, 0x312D, 0x13},
/* PLL setting */
{IMX_8BIT, 0x0305, 0x02},
{IMX_8BIT, 0x0307, 0x50},
{IMX_8BIT, 0x30A4, 0x02},
{IMX_8BIT, 0x303C, 0x3C},
/* Mode setting */
{IMX_8BIT, 0x0344, 0x00},
{IMX_8BIT, 0x0345, 0x14},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0x32},
{IMX_8BIT, 0x0348, 0x07},
{IMX_8BIT, 0x0349, 0xA3},
{IMX_8BIT, 0x034A, 0x04},
{IMX_8BIT, 0x034B, 0x79},
{IMX_8BIT, 0x034C, 0x07},
{IMX_8BIT, 0x034D, 0x90},
{IMX_8BIT, 0x034E, 0x04},
{IMX_8BIT, 0x034F, 0x48},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0383, 0x01},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0387, 0x01},
{IMX_8BIT, 0x303D, 0x10},
{IMX_8BIT, 0x303E, 0x5A},
{IMX_8BIT, 0x3040, 0x00},
{IMX_8BIT, 0x3041, 0x00},
{IMX_8BIT, 0x3048, 0x00},
{IMX_8BIT, 0x304C, 0x2F},
{IMX_8BIT, 0x304D, 0x02},
{IMX_8BIT, 0x3064, 0x92},
{IMX_8BIT, 0x306A, 0x10},
{IMX_8BIT, 0x309B, 0x00},
{IMX_8BIT, 0x309E, 0x41},
{IMX_8BIT, 0x30A0, 0x10},
{IMX_8BIT, 0x30A1, 0x0B},
{IMX_8BIT, 0x30B2, 0x00},
{IMX_8BIT, 0x30D5, 0x00},
{IMX_8BIT, 0x30D6, 0x00},
{IMX_8BIT, 0x30D7, 0x00},
{IMX_8BIT, 0x30D8, 0x00},
{IMX_8BIT, 0x30D9, 0x00},
{IMX_8BIT, 0x30DA, 0x00},
{IMX_8BIT, 0x30DB, 0x00},
{IMX_8BIT, 0x30DC, 0x00},
{IMX_8BIT, 0x30DD, 0x00},
{IMX_8BIT, 0x30DE, 0x00},
{IMX_8BIT, 0x3102, 0x0C},
{IMX_8BIT, 0x3103, 0x33},
{IMX_8BIT, 0x3104, 0x18},
{IMX_8BIT, 0x3105, 0x00},
{IMX_8BIT, 0x3106, 0x65},
{IMX_8BIT, 0x3107, 0x00},
{IMX_8BIT, 0x3108, 0x06},
{IMX_8BIT, 0x3109, 0x04},
{IMX_8BIT, 0x310A, 0x04},
{IMX_8BIT, 0x315C, 0x3D},
{IMX_8BIT, 0x315D, 0x3C},
{IMX_8BIT, 0x316E, 0x3E},
{IMX_8BIT, 0x316F, 0x3D},
/* Global timing */
{IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */
{IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */
{IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */
{IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */
{IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */
{IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */
{IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */
{IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */
{IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */
{IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */
{IMX_8BIT, 0x330E, 0x03},
{IMX_8BIT, 0x3318, 0x62},
{IMX_8BIT, 0x3322, 0x09},
{IMX_8BIT, 0x3342, 0x00},
{IMX_8BIT, 0x3348, 0xE0},
{IMX_TOK_TERM, 0, 0},
};
static struct imx_reg imx132_1456x1096_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
/* Global Settings */
{IMX_8BIT, 0x3087, 0x53},
{IMX_8BIT, 0x308B, 0x5A},
{IMX_8BIT, 0x3094, 0x11},
{IMX_8BIT, 0x309D, 0xA4},
{IMX_8BIT, 0x30AA, 0x01},
{IMX_8BIT, 0x30C6, 0x00},
{IMX_8BIT, 0x30C7, 0x00},
{IMX_8BIT, 0x3118, 0x2F},
{IMX_8BIT, 0x312A, 0x00},
{IMX_8BIT, 0x312B, 0x0B},
{IMX_8BIT, 0x312C, 0x0B},
{IMX_8BIT, 0x312D, 0x13},
/* PLL setting */
{IMX_8BIT, 0x0305, 0x02},
{IMX_8BIT, 0x0307, 0x50},
{IMX_8BIT, 0x30A4, 0x02},
{IMX_8BIT, 0x303C, 0x3C},
/* Mode setting */
{IMX_8BIT, 0x0344, 0x01},
{IMX_8BIT, 0x0345, 0x04},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0x32},
{IMX_8BIT, 0x0348, 0x06},
{IMX_8BIT, 0x0349, 0xB3},
{IMX_8BIT, 0x034A, 0x04},
{IMX_8BIT, 0x034B, 0x79},
{IMX_8BIT, 0x034C, 0x05},
{IMX_8BIT, 0x034D, 0xB0},
{IMX_8BIT, 0x034E, 0x04},
{IMX_8BIT, 0x034F, 0x48},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0383, 0x01},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0387, 0x01},
{IMX_8BIT, 0x303D, 0x10},
{IMX_8BIT, 0x303E, 0x5A},
{IMX_8BIT, 0x3040, 0x00},
{IMX_8BIT, 0x3041, 0x00},
{IMX_8BIT, 0x3048, 0x00},
{IMX_8BIT, 0x304C, 0x2F},
{IMX_8BIT, 0x304D, 0x02},
{IMX_8BIT, 0x3064, 0x92},
{IMX_8BIT, 0x306A, 0x10},
{IMX_8BIT, 0x309B, 0x00},
{IMX_8BIT, 0x309E, 0x41},
{IMX_8BIT, 0x30A0, 0x10},
{IMX_8BIT, 0x30A1, 0x0B},
{IMX_8BIT, 0x30B2, 0x00},
{IMX_8BIT, 0x30D5, 0x00},
{IMX_8BIT, 0x30D6, 0x00},
{IMX_8BIT, 0x30D7, 0x00},
{IMX_8BIT, 0x30D8, 0x00},
{IMX_8BIT, 0x30D9, 0x00},
{IMX_8BIT, 0x30DA, 0x00},
{IMX_8BIT, 0x30DB, 0x00},
{IMX_8BIT, 0x30DC, 0x00},
{IMX_8BIT, 0x30DD, 0x00},
{IMX_8BIT, 0x30DE, 0x00},
{IMX_8BIT, 0x3102, 0x0C},
{IMX_8BIT, 0x3103, 0x33},
{IMX_8BIT, 0x3104, 0x18},
{IMX_8BIT, 0x3105, 0x00},
{IMX_8BIT, 0x3106, 0x65},
{IMX_8BIT, 0x3107, 0x00},
{IMX_8BIT, 0x3108, 0x06},
{IMX_8BIT, 0x3109, 0x04},
{IMX_8BIT, 0x310A, 0x04},
{IMX_8BIT, 0x315C, 0x3D},
{IMX_8BIT, 0x315D, 0x3C},
{IMX_8BIT, 0x316E, 0x3E},
{IMX_8BIT, 0x316F, 0x3D},
/* Global timing */
{IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */
{IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */
{IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */
{IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */
{IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */
{IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */
{IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */
{IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */
{IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */
{IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */
{IMX_8BIT, 0x330E, 0x03},
{IMX_8BIT, 0x3318, 0x62},
{IMX_8BIT, 0x3322, 0x09},
{IMX_8BIT, 0x3342, 0x00},
{IMX_8BIT, 0x3348, 0xE0},
{IMX_TOK_TERM, 0, 0},
};
static struct imx_reg imx132_1636x1096_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
/* Global Settings */
{IMX_8BIT, 0x3087, 0x53},
{IMX_8BIT, 0x308B, 0x5A},
{IMX_8BIT, 0x3094, 0x11},
{IMX_8BIT, 0x309D, 0xA4},
{IMX_8BIT, 0x30AA, 0x01},
{IMX_8BIT, 0x30C6, 0x00},
{IMX_8BIT, 0x30C7, 0x00},
{IMX_8BIT, 0x3118, 0x2F},
{IMX_8BIT, 0x312A, 0x00},
{IMX_8BIT, 0x312B, 0x0B},
{IMX_8BIT, 0x312C, 0x0B},
{IMX_8BIT, 0x312D, 0x13},
/* PLL setting */
{IMX_8BIT, 0x0305, 0x02},
{IMX_8BIT, 0x0307, 0x50},
{IMX_8BIT, 0x30A4, 0x02},
{IMX_8BIT, 0x303C, 0x3C},
/* Mode setting */
{IMX_8BIT, 0x0344, 0x00},
{IMX_8BIT, 0x0345, 0xAA},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0x32},
{IMX_8BIT, 0x0348, 0x07},
{IMX_8BIT, 0x0349, 0x0D},
{IMX_8BIT, 0x034A, 0x04},
{IMX_8BIT, 0x034B, 0x79},
{IMX_8BIT, 0x034C, 0x06},
{IMX_8BIT, 0x034D, 0x64},
{IMX_8BIT, 0x034E, 0x04},
{IMX_8BIT, 0x034F, 0x48},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0383, 0x01},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0387, 0x01},
{IMX_8BIT, 0x303D, 0x10},
{IMX_8BIT, 0x303E, 0x5A},
{IMX_8BIT, 0x3040, 0x00},
{IMX_8BIT, 0x3041, 0x00},
{IMX_8BIT, 0x3048, 0x00},
{IMX_8BIT, 0x304C, 0x2F},
{IMX_8BIT, 0x304D, 0x02},
{IMX_8BIT, 0x3064, 0x92},
{IMX_8BIT, 0x306A, 0x10},
{IMX_8BIT, 0x309B, 0x00},
{IMX_8BIT, 0x309E, 0x41},
{IMX_8BIT, 0x30A0, 0x10},
{IMX_8BIT, 0x30A1, 0x0B},
{IMX_8BIT, 0x30B2, 0x00},
{IMX_8BIT, 0x30D5, 0x00},
{IMX_8BIT, 0x30D6, 0x00},
{IMX_8BIT, 0x30D7, 0x00},
{IMX_8BIT, 0x30D8, 0x00},
{IMX_8BIT, 0x30D9, 0x00},
{IMX_8BIT, 0x30DA, 0x00},
{IMX_8BIT, 0x30DB, 0x00},
{IMX_8BIT, 0x30DC, 0x00},
{IMX_8BIT, 0x30DD, 0x00},
{IMX_8BIT, 0x30DE, 0x00},
{IMX_8BIT, 0x3102, 0x0C},
{IMX_8BIT, 0x3103, 0x33},
{IMX_8BIT, 0x3104, 0x18},
{IMX_8BIT, 0x3105, 0x00},
{IMX_8BIT, 0x3106, 0x65},
{IMX_8BIT, 0x3107, 0x00},
{IMX_8BIT, 0x3108, 0x06},
{IMX_8BIT, 0x3109, 0x04},
{IMX_8BIT, 0x310A, 0x04},
{IMX_8BIT, 0x315C, 0x3D},
{IMX_8BIT, 0x315D, 0x3C},
{IMX_8BIT, 0x316E, 0x3E},
{IMX_8BIT, 0x316F, 0x3D},
/* Global timing */
{IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */
{IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */
{IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */
{IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */
{IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */
{IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */
{IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */
{IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */
{IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */
{IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */
{IMX_8BIT, 0x330E, 0x03},
{IMX_8BIT, 0x3318, 0x62},
{IMX_8BIT, 0x3322, 0x09},
{IMX_8BIT, 0x3342, 0x00},
{IMX_8BIT, 0x3348, 0xE0},
{IMX_TOK_TERM, 0, 0},
};
static struct imx_reg imx132_1336x1096_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
/* Global Settings */
{IMX_8BIT, 0x3087, 0x53},
{IMX_8BIT, 0x308B, 0x5A},
{IMX_8BIT, 0x3094, 0x11},
{IMX_8BIT, 0x309D, 0xA4},
{IMX_8BIT, 0x30AA, 0x01},
{IMX_8BIT, 0x30C6, 0x00},
{IMX_8BIT, 0x30C7, 0x00},
{IMX_8BIT, 0x3118, 0x2F},
{IMX_8BIT, 0x312A, 0x00},
{IMX_8BIT, 0x312B, 0x0B},
{IMX_8BIT, 0x312C, 0x0B},
{IMX_8BIT, 0x312D, 0x13},
/* PLL setting */
{IMX_8BIT, 0x0305, 0x02},
{IMX_8BIT, 0x0307, 0x50},
{IMX_8BIT, 0x30A4, 0x02},
{IMX_8BIT, 0x303C, 0x3C},
/* Mode setting */
{IMX_8BIT, 0x0344, 0x01},
{IMX_8BIT, 0x0345, 0x2C},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0x32},
{IMX_8BIT, 0x0348, 0x06},
{IMX_8BIT, 0x0349, 0x77},
{IMX_8BIT, 0x034A, 0x04},
{IMX_8BIT, 0x034B, 0x79},
{IMX_8BIT, 0x034C, 0x05},
{IMX_8BIT, 0x034D, 0x38},
{IMX_8BIT, 0x034E, 0x04},
{IMX_8BIT, 0x034F, 0x48},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0383, 0x01},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0387, 0x01},
{IMX_8BIT, 0x303D, 0x10},
{IMX_8BIT, 0x303E, 0x5A},
{IMX_8BIT, 0x3040, 0x00},
{IMX_8BIT, 0x3041, 0x00},
{IMX_8BIT, 0x3048, 0x00},
{IMX_8BIT, 0x304C, 0x2F},
{IMX_8BIT, 0x304D, 0x02},
{IMX_8BIT, 0x3064, 0x92},
{IMX_8BIT, 0x306A, 0x10},
{IMX_8BIT, 0x309B, 0x00},
{IMX_8BIT, 0x309E, 0x41},
{IMX_8BIT, 0x30A0, 0x10},
{IMX_8BIT, 0x30A1, 0x0B},
{IMX_8BIT, 0x30B2, 0x00},
{IMX_8BIT, 0x30D5, 0x00},
{IMX_8BIT, 0x30D6, 0x00},
{IMX_8BIT, 0x30D7, 0x00},
{IMX_8BIT, 0x30D8, 0x00},
{IMX_8BIT, 0x30D9, 0x00},
{IMX_8BIT, 0x30DA, 0x00},
{IMX_8BIT, 0x30DB, 0x00},
{IMX_8BIT, 0x30DC, 0x00},
{IMX_8BIT, 0x30DD, 0x00},
{IMX_8BIT, 0x30DE, 0x00},
{IMX_8BIT, 0x3102, 0x0C},
{IMX_8BIT, 0x3103, 0x33},
{IMX_8BIT, 0x3104, 0x18},
{IMX_8BIT, 0x3105, 0x00},
{IMX_8BIT, 0x3106, 0x65},
{IMX_8BIT, 0x3107, 0x00},
{IMX_8BIT, 0x3108, 0x06},
{IMX_8BIT, 0x3109, 0x04},
{IMX_8BIT, 0x310A, 0x04},
{IMX_8BIT, 0x315C, 0x3D},
{IMX_8BIT, 0x315D, 0x3C},
{IMX_8BIT, 0x316E, 0x3E},
{IMX_8BIT, 0x316F, 0x3D},
/* Global timing */
{IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */
{IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */
{IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */
{IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */
{IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */
{IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */
{IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */
{IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */
{IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */
{IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */
{IMX_8BIT, 0x330E, 0x03},
{IMX_8BIT, 0x3318, 0x62},
{IMX_8BIT, 0x3322, 0x09},
{IMX_8BIT, 0x3342, 0x00},
{IMX_8BIT, 0x3348, 0xE0},
{IMX_TOK_TERM, 0, 0},
};
/********************** settings for imx - reference *********************/
static struct imx_reg const imx132_init_settings[] = {
/* sw reset */
{ IMX_8BIT, 0x0100, 0x00 },
{ IMX_8BIT, 0x0103, 0x01 },
{ IMX_TOK_DELAY, 0, 5},
{ IMX_8BIT, 0x0103, 0x00 },
GROUPED_PARAMETER_HOLD_ENABLE,
/* Global Settings */
{IMX_8BIT, 0x3087, 0x53},
{IMX_8BIT, 0x308B, 0x5A},
{IMX_8BIT, 0x3094, 0x11},
{IMX_8BIT, 0x309D, 0xA4},
{IMX_8BIT, 0x30AA, 0x01},
{IMX_8BIT, 0x30C6, 0x00},
{IMX_8BIT, 0x30C7, 0x00},
{IMX_8BIT, 0x3118, 0x2F},
{IMX_8BIT, 0x312A, 0x00},
{IMX_8BIT, 0x312B, 0x0B},
{IMX_8BIT, 0x312C, 0x0B},
{IMX_8BIT, 0x312D, 0x13},
GROUPED_PARAMETER_HOLD_DISABLE,
{ IMX_TOK_TERM, 0, 0}
};
struct imx_resolution imx132_res_preview[] = {
{
.desc = "imx132_1080p_30fps",
.regs = imx132_1080p_30fps,
.width = 1936,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08F2,
.lines_per_frame = 0x045C,
},
{
}
},
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.skip_frames = 2,
.mipi_freq = 384000,
},
};
struct imx_resolution imx132_res_still[] = {
{
.desc = "imx132_1080p_30fps",
.regs = imx132_1080p_30fps,
.width = 1936,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08F2,
.lines_per_frame = 0x045C,
},
{
}
},
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.skip_frames = 2,
.mipi_freq = 384000,
},
};
struct imx_resolution imx132_res_video[] = {
{
.desc = "imx132_1336x1096_30fps",
.regs = imx132_1336x1096_30fps,
.width = 1336,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08F2,
.lines_per_frame = 0x045C,
},
{
}
},
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.skip_frames = 2,
.mipi_freq = 384000,
},
{
.desc = "imx132_1456x1096_30fps",
.regs = imx132_1456x1096_30fps,
.width = 1456,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08F2,
.lines_per_frame = 0x045C,
},
{
}
},
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.skip_frames = 2,
.mipi_freq = 384000,
},
{
.desc = "imx132_1636x1096_30fps",
.regs = imx132_1636x1096_30fps,
.width = 1636,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08F2,
.lines_per_frame = 0x045C,
},
{
}
},
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.skip_frames = 2,
.mipi_freq = 384000,
},
{
.desc = "imx132_1080p_30fps",
.regs = imx132_1080p_30fps,
.width = 1936,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08F2,
.lines_per_frame = 0x045C,
},
{
}
},
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.skip_frames = 2,
.mipi_freq = 384000,
},
};
#endif

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/*
* Support for Sony IMX camera sensor.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __IMX208_H__
#define __IMX208_H__
#include "common.h"
/********************** settings for imx from vendor*********************/
static struct imx_reg imx208_1080p_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */
{IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */
{IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */
{IMX_8BIT, 0x30A4, 0x02}, /* Default */
{IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */
{IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */
{IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */
{IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */
{IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[12:8] */
{IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */
{IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */
{IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */
{IMX_8BIT, 0x0348, 0x07}, /* x_addr_end [12:8] */
{IMX_8BIT, 0x0349, 0x8F}, /* x_addr_end [7:0] */
{IMX_8BIT, 0x034A, 0x04}, /* y_addr_end [12:8] */
{IMX_8BIT, 0x034B, 0x47}, /* y_addr_end [7:0] */
{IMX_8BIT, 0x034C, 0x07}, /* x_output_size [ 12:8] */
{IMX_8BIT, 0x034D, 0x90}, /* x_output_size [7:0] */
{IMX_8BIT, 0x034E, 0x04}, /* y_output_size [11:8] */
{IMX_8BIT, 0x034F, 0x48}, /* y_output_size [7:0] */
{IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */
{IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */
{IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */
{IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */
{IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */
{IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */
{IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */
{IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */
{IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */
{IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */
{IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */
{IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */
{IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */
{IMX_8BIT, 0x0205, 0x00}, /* ana global gain */
{IMX_TOK_TERM, 0, 0},
};
static struct imx_reg imx208_1296x736_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */
{IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */
{IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */
{IMX_8BIT, 0x30A4, 0x02}, /* Default */
{IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */
{IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */
{IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */
{IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */
{IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[12:8] */
{IMX_8BIT, 0x0345, 0x40}, /* x_addr_start[7:0] */
{IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */
{IMX_8BIT, 0x0347, 0xB4}, /* y_addr_start[7:0] */
{IMX_8BIT, 0x0348, 0x06}, /* x_addr_end [12:8] */
{IMX_8BIT, 0x0349, 0x4F}, /* x_addr_end [7:0] */
{IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */
{IMX_8BIT, 0x034B, 0x93}, /* y_addr_end [7:0] */
{IMX_8BIT, 0x034C, 0x05}, /* x_output_size [ 12:8] */
{IMX_8BIT, 0x034D, 0x10}, /* x_output_size [7:0] */
{IMX_8BIT, 0x034E, 0x02}, /* y_output_size [11:8] */
{IMX_8BIT, 0x034F, 0xE0}, /* y_output_size [7:0] */
{IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */
{IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */
{IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */
{IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */
{IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */
{IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */
{IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */
{IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */
{IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */
{IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */
{IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */
{IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */
{IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */
{IMX_8BIT, 0x0205, 0x00}, /* ana global gain */
{IMX_TOK_TERM, 0, 0},
};
static struct imx_reg imx208_1296x976_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */
{IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */
{IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */
{IMX_8BIT, 0x30A4, 0x02}, /* Default */
{IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */
{IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */
{IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */
{IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */
{IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[12:8] */
{IMX_8BIT, 0x0345, 0x40}, /* x_addr_start[7:0] */
{IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */
{IMX_8BIT, 0x0347, 0x3C}, /* y_addr_start[7:0] */
{IMX_8BIT, 0x0348, 0x06}, /* x_addr_end [12:8] */
{IMX_8BIT, 0x0349, 0x4F}, /* x_addr_end [7:0] */
{IMX_8BIT, 0x034A, 0x04}, /* y_addr_end [12:8] */
{IMX_8BIT, 0x034B, 0x0B}, /* y_addr_end [7:0] */
{IMX_8BIT, 0x034C, 0x05}, /* x_output_size [ 12:8] */
{IMX_8BIT, 0x034D, 0x10}, /* x_output_size [7:0] */
{IMX_8BIT, 0x034E, 0x03}, /* y_output_size [11:8] */
{IMX_8BIT, 0x034F, 0xD0}, /* y_output_size [7:0] */
{IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */
{IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */
{IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */
{IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */
{IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */
{IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */
{IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */
{IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */
{IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */
{IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */
{IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */
{IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */
{IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */
{IMX_8BIT, 0x0205, 0x00}, /* ana global gain */
{IMX_TOK_TERM, 0, 0},
};
static struct imx_reg imx208_336x256_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */
{IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */
{IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */
{IMX_8BIT, 0x30A4, 0x02}, /* Default */
{IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */
{IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */
{IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */
{IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */
{IMX_8BIT, 0x0344, 0x02}, /* x_addr_start[12:8] */
{IMX_8BIT, 0x0345, 0x78}, /* x_addr_start[7:0] */
{IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[12:8] */
{IMX_8BIT, 0x0347, 0x24}, /* y_addr_start[7:0] */
{IMX_8BIT, 0x0348, 0x05}, /* x_addr_end [12:8] */
{IMX_8BIT, 0x0349, 0x17}, /* x_addr_end [7:0] */
{IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */
{IMX_8BIT, 0x034B, 0x23}, /* y_addr_end [7:0] */
{IMX_8BIT, 0x034C, 0x01}, /* x_output_size [ 12:8] */
{IMX_8BIT, 0x034D, 0x50}, /* x_output_size [7:0] */
{IMX_8BIT, 0x034E, 0x01}, /* y_output_size [11:8] */
{IMX_8BIT, 0x034F, 0x00}, /* y_output_size [7:0] */
{IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */
{IMX_8BIT, 0x0383, 0x03}, /* x_odd_inc */
{IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */
{IMX_8BIT, 0x0387, 0x03}, /* y_odd_inc */
{IMX_8BIT, 0x3048, 0x01}, /* VMODEFDS binning operation */
{IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */
{IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */
{IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */
{IMX_8BIT, 0x30D5, 0x03}, /* HADDEN ( binning ) */
{IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */
{IMX_8BIT, 0x3318, 0x66}, /* MIPI Global Timing */
{IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */
{IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */
{IMX_8BIT, 0x0205, 0x00}, /* ana global gain */
{IMX_TOK_TERM, 0, 0},
};
static struct imx_reg imx208_192x160_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */
{IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */
{IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */
{IMX_8BIT, 0x30A4, 0x02}, /* Default */
{IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */
{IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */
{IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */
{IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */
{IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */
{IMX_8BIT, 0x0344, 0x02}, /* x_addr_start[12:8] */
{IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */
{IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */
{IMX_8BIT, 0x0347, 0xE4}, /* y_addr_start[7:0] */
{IMX_8BIT, 0x0348, 0x05}, /* x_addr_end [12:8] */
{IMX_8BIT, 0x0349, 0x47}, /* x_addr_end [7:0] */
{IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */
{IMX_8BIT, 0x034B, 0x63}, /* y_addr_end [7:0] */
{IMX_8BIT, 0x034C, 0x00}, /* x_output_size [ 12:8] */
{IMX_8BIT, 0x034D, 0xC0}, /* x_output_size [7:0] */
{IMX_8BIT, 0x034E, 0x00}, /* y_output_size [11:8] */
{IMX_8BIT, 0x034F, 0xA0}, /* y_output_size [7:0] */
{IMX_8BIT, 0x0381, 0x03}, /* x_even_inc */
{IMX_8BIT, 0x0383, 0x05}, /* x_odd_inc */
{IMX_8BIT, 0x0385, 0x03}, /* y_even_inc */
{IMX_8BIT, 0x0387, 0x05}, /* y_odd_inc */
{IMX_8BIT, 0x3048, 0x01}, /* VMODEFDS binning operation */
{IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */
{IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */
{IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */
{IMX_8BIT, 0x30D5, 0x03}, /* HADDEN ( binning ) */
{IMX_8BIT, 0x3301, 0x11}, /* RGLANESEL */
{IMX_8BIT, 0x3318, 0x74}, /* MIPI Global Timing */
{IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */
{IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */
{IMX_8BIT, 0x0205, 0x00}, /* ana global gain */
{IMX_TOK_TERM, 0, 0},
};
/********************** settings for imx - reference *********************/
static struct imx_reg const imx208_init_settings[] = {
{ IMX_TOK_TERM, 0, 0}
};
struct imx_resolution imx208_res_preview[] = {
{
.desc = "imx208_1080p_30fps",
.regs = imx208_1080p_30fps,
.width = 1936,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_1296x976_30fps",
.regs = imx208_1296x976_30fps,
.width = 1296,
.height = 976,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_1296x736_30fps",
.regs = imx208_1296x736_30fps,
.width = 1296,
.height = 736,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_336x256_30fps",
.regs = imx208_336x256_30fps,
.width = 336,
.height = 256,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 2,
.bin_factor_y = 2,
.used = 0,
.skip_frames = 2,
.mipi_freq = 201600,
},
{
.desc = "imx208_192x160_30fps",
.regs = imx208_192x160_30fps,
.width = 192,
.height = 160,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 4,
.bin_factor_y = 4,
.used = 0,
.skip_frames = 2,
.mipi_freq = 100800,
},
};
struct imx_resolution imx208_res_still[] = {
{
.desc = "imx208_1080p_30fps",
.regs = imx208_1080p_30fps,
.width = 1936,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_1296x976_30fps",
.regs = imx208_1296x976_30fps,
.width = 1296,
.height = 976,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_1296x736_30fps",
.regs = imx208_1296x736_30fps,
.width = 1296,
.height = 736,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_336x256_30fps",
.regs = imx208_336x256_30fps,
.width = 336,
.height = 256,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 2,
.bin_factor_y = 2,
.used = 0,
.skip_frames = 2,
.mipi_freq = 201600,
},
{
.desc = "imx208_192x160_30fps",
.regs = imx208_192x160_30fps,
.width = 192,
.height = 160,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 4,
.bin_factor_y = 4,
.used = 0,
.skip_frames = 2,
.mipi_freq = 100800,
},
};
struct imx_resolution imx208_res_video[] = {
{
.desc = "imx208_1080p_30fps",
.regs = imx208_1080p_30fps,
.width = 1936,
.height = 1096,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_1296x976_30fps",
.regs = imx208_1296x976_30fps,
.width = 1296,
.height = 976,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_1296x736_30fps",
.regs = imx208_1296x736_30fps,
.width = 1296,
.height = 736,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 1,
.bin_factor_y = 1,
.used = 0,
.skip_frames = 2,
.mipi_freq = 403200,
},
{
.desc = "imx208_336x256_30fps",
.regs = imx208_336x256_30fps,
.width = 336,
.height = 256,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 2,
.bin_factor_y = 2,
.used = 0,
.skip_frames = 2,
.mipi_freq = 201600,
},
{
.desc = "imx208_192x160_30fps",
.regs = imx208_192x160_30fps,
.width = 192,
.height = 160,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x08C8,
.lines_per_frame = 0x04AA,
},
{
}
},
.bin_factor_x = 4,
.bin_factor_y = 4,
.used = 0,
.skip_frames = 2,
.mipi_freq = 100800,
},
};
#endif

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drivers/staging/media/atomisp/i2c/imx/imx219.h Normal file
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#ifndef __IMX219_H__
#define __IMX219_H__
#include "common.h"
#define IMX219_FRAME_LENGTH_LINES 0x0160
#define IMX219_LINE_LENGTH_PIXELS 0x0162
#define IMX219_HORIZONTAL_START_H 0x0164
#define IMX219_VERTICAL_START_H 0x0168
#define IMX219_HORIZONTAL_END_H 0x0166
#define IMX219_VERTICAL_END_H 0x016A
#define IMX219_HORIZONTAL_OUTPUT_SIZE_H 0x016c
#define IMX219_VERTICAL_OUTPUT_SIZE_H 0x016E
#define IMX219_COARSE_INTEGRATION_TIME 0x015A
#define IMX219_IMG_ORIENTATION 0x0172
#define IMX219_GLOBAL_GAIN 0x0157
#define IMX219_DGC_ADJ 0x0158
#define IMX219_DGC_LEN 4
/************************** settings for imx *************************/
static struct imx_reg const imx219_STILL_8M_30fps[] = {
{IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x30EB, 0x0C}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x300A, 0xFF}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x300B, 0xFF}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x30EB, 0x09}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x0114, 0x03}, /*CSI_LANE_MODE[1:0}*/
{IMX_8BIT, 0x0128, 0x00}, /*DPHY_CNTRL*/
{IMX_8BIT, 0x012A, 0x13}, /*EXCK_FREQ[15:8]*/
{IMX_8BIT, 0x012B, 0x34}, /*EXCK_FREQ[7:0]*/
{IMX_8BIT, 0x0160, 0x0A}, /*FRM_LENGTH_A[15:8]*/
{IMX_8BIT, 0x0161, 0x94}, /*FRM_LENGTH_A[7:0]*/
{IMX_8BIT, 0x0162, 0x0D}, /*LINE_LENGTH_A[15:8]*/
{IMX_8BIT, 0x0163, 0x78}, /*LINE_LENGTH_A[7:0]*/
{IMX_8BIT, 0x0164, 0x00}, /*X_ADD_STA_A[11:8]*/
{IMX_8BIT, 0x0165, 0x00}, /*X_ADD_STA_A[7:0]*/
{IMX_8BIT, 0x0166, 0x0C}, /*X_ADD_END_A[11:8]*/
{IMX_8BIT, 0x0167, 0xCF}, /*X_ADD_END_A[7:0]*/
{IMX_8BIT, 0x0168, 0x00}, /*Y_ADD_STA_A[11:8]*/
{IMX_8BIT, 0x0169, 0x00}, /*Y_ADD_STA_A[7:0]*/
{IMX_8BIT, 0x016A, 0x09}, /*Y_ADD_END_A[11:8]*/
{IMX_8BIT, 0x016B, 0x9F}, /*Y_ADD_END_A[7:0]*/
{IMX_8BIT, 0x016C, 0x0C}, /*X_OUTPUT_SIZE_A[11:8]*/
{IMX_8BIT, 0x016D, 0xD0}, /*X_OUTPUT_SIZE_A[7:0]*/
{IMX_8BIT, 0x016E, 0x09}, /*Y_OUTPUT_SIZE_A[11:8]*/
{IMX_8BIT, 0x016F, 0xA0}, /*Y_OUTPUT_SIZE_A[7:0]*/
{IMX_8BIT, 0x0170, 0x01}, /*X_ODD_INC_A[2:0]*/
{IMX_8BIT, 0x0171, 0x01}, /*Y_ODD_INC_A[2:0]*/
{IMX_8BIT, 0x0174, 0x00}, /*BINNING_MODE_H_A*/
{IMX_8BIT, 0x0175, 0x00}, /*BINNING_MODE_V_A*/
{IMX_8BIT, 0x018C, 0x0A}, /*CSI_DATA_FORMAT_A[15:8]*/
{IMX_8BIT, 0x018D, 0x0A}, /*CSI_DATA_FORMAT_A[7:0]*/
{IMX_8BIT, 0x0301, 0x05}, /*VTPXCK_DIV*/
{IMX_8BIT, 0x0303, 0x01}, /*VTSYCK_DIV*/
{IMX_8BIT, 0x0304, 0x02}, /*PREPLLCK_VT_DIV[3:0]*/
{IMX_8BIT, 0x0305, 0x02}, /*PREPLLCK_OP_DIV[3:0]*/
{IMX_8BIT, 0x0306, 0x00}, /*PLL_VT_MPY[10:8]*/
{IMX_8BIT, 0x0307, 0x49}, /*PLL_VT_MPY[7:0]*/
{IMX_8BIT, 0x0309, 0x0A}, /*OPPXCK_DIV[4:0]*/
{IMX_8BIT, 0x030B, 0x01}, /*OPSYCK_DIV*/
{IMX_8BIT, 0x030C, 0x00}, /*PLL_OP_MPY[10:8]*/
{IMX_8BIT, 0x030D, 0x4C}, /*PLL_OP_MPY[7:0]*/
{IMX_8BIT, 0x4767, 0x0F}, /*CIS Tuning*/
{IMX_8BIT, 0x4750, 0x14}, /*CIS Tuning*/
{IMX_8BIT, 0x47B4, 0x14}, /*CIS Tuning*/
{IMX_TOK_TERM, 0, 0}
};
static struct imx_reg const imx219_STILL_6M_30fps[] = {
{IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x30EB, 0x0C}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x300A, 0xFF}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x300B, 0xFF}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x30EB, 0x09}, /*Access Code for address over 0x3000*/
{IMX_8BIT, 0x0114, 0x03}, /*CSI_LANE_MODE[1:0}*/
{IMX_8BIT, 0x0128, 0x00}, /*DPHY_CNTRL*/
{IMX_8BIT, 0x012A, 0x13}, /*EXCK_FREQ[15:8]*/
{IMX_8BIT, 0x012B, 0x34}, /*EXCK_FREQ[7:0]*/
{IMX_8BIT, 0x0160, 0x07}, /*FRM_LENGTH_A[15:8]*/
{IMX_8BIT, 0x0161, 0x64}, /*FRM_LENGTH_A[7:0]*/
{IMX_8BIT, 0x0162, 0x0D}, /*LINE_LENGTH_A[15:8]*/
{IMX_8BIT, 0x0163, 0x78}, /*LINE_LENGTH_A[7:0]*/
{IMX_8BIT, 0x0164, 0x00}, /*X_ADD_STA_A[11:8]*/
{IMX_8BIT, 0x0165, 0x00}, /*X_ADD_STA_A[7:0]*/
{IMX_8BIT, 0x0166, 0x0C}, /*X_ADD_END_A[11:8]*/
{IMX_8BIT, 0x0167, 0xCF}, /*X_ADD_END_A[7:0]*/
{IMX_8BIT, 0x0168, 0x01}, /*Y_ADD_STA_A[11:8]*/
{IMX_8BIT, 0x0169, 0x32}, /*Y_ADD_STA_A[7:0]*/
{IMX_8BIT, 0x016A, 0x08}, /*Y_ADD_END_A[11:8]*/
{IMX_8BIT, 0x016B, 0x6D}, /*Y_ADD_END_A[7:0]*/
{IMX_8BIT, 0x016C, 0x0C}, /*X_OUTPUT_SIZE_A[11:8]*/
{IMX_8BIT, 0x016D, 0xD0}, /*X_OUTPUT_SIZE_A[7:0]*/
{IMX_8BIT, 0x016E, 0x07}, /*Y_OUTPUT_SIZE_A[11:8]*/
{IMX_8BIT, 0x016F, 0x3C}, /*Y_OUTPUT_SIZE_A[7:0]*/
{IMX_8BIT, 0x0170, 0x01}, /*X_ODD_INC_A[2:0]*/
{IMX_8BIT, 0x0171, 0x01}, /*Y_ODD_INC_A[2:0]*/
{IMX_8BIT, 0x0174, 0x00}, /*BINNING_MODE_H_A*/
{IMX_8BIT, 0x0175, 0x00}, /*BINNING_MODE_V_A*/
{IMX_8BIT, 0x018C, 0x0A}, /*CSI_DATA_FORMAT_A[15:8]*/
{IMX_8BIT, 0x018D, 0x0A}, /*CSI_DATA_FORMAT_A[7:0]*/
{IMX_8BIT, 0x0301, 0x05}, /*VTPXCK_DIV*/
{IMX_8BIT, 0x0303, 0x01}, /*VTSYCK_DIV*/
{IMX_8BIT, 0x0304, 0x02}, /*PREPLLCK_VT_DIV[3:0]*/
{IMX_8BIT, 0x0305, 0x02}, /*PREPLLCK_OP_DIV[3:0]*/
{IMX_8BIT, 0x0306, 0x00}, /*PLL_VT_MPY[10:8]*/
{IMX_8BIT, 0x0307, 0x33}, /*PLL_VT_MPY[7:0]*/
{IMX_8BIT, 0x0309, 0x0A}, /*OPPXCK_DIV[4:0]*/
{IMX_8BIT, 0x030B, 0x01}, /*OPSYCK_DIV*/
{IMX_8BIT, 0x030C, 0x00}, /*PLL_OP_MPY[10:8]*/
{IMX_8BIT, 0x030D, 0x36}, /*PLL_OP_MPY[7:0]*/
{IMX_8BIT, 0x4767, 0x0F}, /*CIS Tuning*/
{IMX_8BIT, 0x4750, 0x14}, /*CIS Tuning*/
{IMX_8BIT, 0x47B4, 0x14}, /*CIS Tuning*/
{IMX_TOK_TERM, 0, 0}
};
static struct imx_reg const imx219_init_settings[] = {
{IMX_TOK_TERM, 0, 0}
};
struct imx_resolution imx219_res_preview[] = {
{
.desc = "STILL_6M_30fps",
.regs = imx219_STILL_6M_30fps,
.width = 3280,
.height = 1852,
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0D78,
.lines_per_frame = 0x0764,
},
{
}
},
.mipi_freq = 259000,
},
{
.desc = "STILL_8M_30fps",
.regs = imx219_STILL_8M_30fps,
.width = 3280,
.height = 2464,
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0D78,
.lines_per_frame = 0x0A94,
},
{
}
},
.mipi_freq = 365000,
},
};
struct imx_resolution imx219_res_still[] = {
{
.desc = "STILL_6M_30fps",
.regs = imx219_STILL_6M_30fps,
.width = 3280,
.height = 1852,
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0D78,
.lines_per_frame = 0x0764,
},
{
}
},
.mipi_freq = 259000,
},
{
.desc = "STILL_8M_30fps",
.regs = imx219_STILL_8M_30fps,
.width = 3280,
.height = 2464,
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0D78,
.lines_per_frame = 0x0A94,
},
{
}
},
.mipi_freq = 365000,
},
};
struct imx_resolution imx219_res_video[] = {
{
.desc = "STILL_6M_30fps",
.regs = imx219_STILL_6M_30fps,
.width = 3280,
.height = 1852,
.bin_factor_x = 0,
.bin_factor_y = 0,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0D78,
.lines_per_frame = 0x0764,
},
{
}
},
.mipi_freq = 259000,
},
};
#endif

726
drivers/staging/media/atomisp/i2c/imx/imx227.h Normal file
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@ -0,0 +1,726 @@
#ifndef __IMX227_H__
#define __IMX227_H__
#include "common.h"
#define IMX227_EMBEDDED_DATA_LINE_NUM 2
#define IMX227_OUTPUT_DATA_FORMAT_REG 0x0112
#define IMX227_OUTPUT_FORMAT_RAW10 0x0a0a
/* AE Bracketing Registers */
#define IMX227_BRACKETING_LUT_MODE_BIT_CONTINUE_STREAMING 0x1
#define IMX227_BRACKETING_LUT_MODE_BIT_LOOP_MODE 0x2
#define IMX227_BRACKETING_LUT_CONTROL 0x0E00
#define IMX227_BRACKETING_LUT_MODE 0x0E01
#define IMX227_BRACKETING_LUT_ENTRY_CONTROL 0x0E02
/*
* The imx135 embedded data info:
* embedded data line num: 2
* line 0 effective data size(byte): 76
* line 1 effective data size(byte): 113
*/
static const uint32_t
imx227_embedded_effective_size[IMX227_EMBEDDED_DATA_LINE_NUM] = {160, 62};
/************************** settings for imx *************************/
/* Full Output Mode */
static struct imx_reg const imx_STILL_6_5M_25fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x6259, 0x06}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xd0}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3f}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* 4:3 Output Mode */
static struct imx_reg const imx_STILL_5_5M_3X4_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0344, 0x00},
{IMX_8BIT, 0x0345, 0xb0},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0x00},
{IMX_8BIT, 0x0348, 0x08},
{IMX_8BIT, 0x0349, 0xaf},
{IMX_8BIT, 0x034a, 0x0a},
{IMX_8BIT, 0x034b, 0x9f},
{IMX_8BIT, 0x034c, 0x08},
{IMX_8BIT, 0x034d, 0x00},
{IMX_8BIT, 0x034e, 0x0a},
{IMX_8BIT, 0x034f, 0xa0},
{IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xd8}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3f}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* Square Output Mode */
static struct imx_reg const imx_STILL_5_7M_1X1_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0344, 0x00},
{IMX_8BIT, 0x0345, 0x00},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0xa0},
{IMX_8BIT, 0x0348, 0x09},
{IMX_8BIT, 0x0349, 0x5f},
{IMX_8BIT, 0x034a, 0x09},
{IMX_8BIT, 0x034b, 0xff},
{IMX_8BIT, 0x034c, 0x09},
{IMX_8BIT, 0x034d, 0x60},
{IMX_8BIT, 0x034e, 0x09},
{IMX_8BIT, 0x034f, 0x60},
{IMX_8BIT, 0x6259, 0x06}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xd4}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3f}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* Full Frame 1080P Mode (use ISP scaler)*/
static struct imx_reg const imx_VIDEO_4M_9X16_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xdc}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3f}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* Cropped 1080P Mode */
static struct imx_reg const imx_VIDEO_2M_9X16_45fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0112, 0x0a},
{IMX_8BIT, 0x0113, 0x0a},
{IMX_8BIT, 0x0344, 0x02},
{IMX_8BIT, 0x0345, 0x8a},
{IMX_8BIT, 0x0346, 0x01},
{IMX_8BIT, 0x0347, 0x88},
{IMX_8BIT, 0x0348, 0x06},
{IMX_8BIT, 0x0349, 0xd1},
{IMX_8BIT, 0x034a, 0x09},
{IMX_8BIT, 0x034b, 0x17},
{IMX_8BIT, 0x034c, 0x04},
{IMX_8BIT, 0x034d, 0x48},
{IMX_8BIT, 0x034e, 0x07},
{IMX_8BIT, 0x034f, 0x90},
{IMX_8BIT, 0x0380, 0x00},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0382, 0x00},
{IMX_8BIT, 0x0383, 0x01},
{IMX_8BIT, 0x0384, 0x00},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0386, 0x00},
{IMX_8BIT, 0x0387, 0x01},
{IMX_8BIT, 0x0408, 0x00},
{IMX_8BIT, 0x0409, 0x00},
{IMX_8BIT, 0x040a, 0x00},
{IMX_8BIT, 0x040b, 0x00},
{IMX_8BIT, 0x040c, 0x04},
{IMX_8BIT, 0x040d, 0x48},
{IMX_8BIT, 0x040e, 0x07},
{IMX_8BIT, 0x040f, 0x90},
{IMX_8BIT, 0x0900, 0x00},
{IMX_8BIT, 0x0901, 0x00},
{IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xdc}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3c}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* Moment mode */
static struct imx_reg const imx_VIDEO_1_3M_3X4_60fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xd9}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3f}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* High Speed 3:4 mode */
static struct imx_reg const imx_VIDEO_VGA_3X4_120fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x9004, 0xca}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3f}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* Binned 720P mode */
static struct imx_reg const imx_VIDEO_1M_9X16_60fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0112, 0x0a},
{IMX_8BIT, 0x0113, 0x0a},
{IMX_8BIT, 0x0344, 0x01},
{IMX_8BIT, 0x0345, 0xd0},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0x40},
{IMX_8BIT, 0x0348, 0x07},
{IMX_8BIT, 0x0349, 0x8f},
{IMX_8BIT, 0x034a, 0x0a},
{IMX_8BIT, 0x034b, 0x5f},
{IMX_8BIT, 0x034c, 0x02},
{IMX_8BIT, 0x034d, 0xe0},
{IMX_8BIT, 0x034e, 0x05},
{IMX_8BIT, 0x034f, 0x10},
{IMX_8BIT, 0x0380, 0x00},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0382, 0x00},
{IMX_8BIT, 0x0383, 0x01},
{IMX_8BIT, 0x0384, 0x00},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0386, 0x00},
{IMX_8BIT, 0x0387, 0x01},
{IMX_8BIT, 0x0408, 0x00},
{IMX_8BIT, 0x0409, 0x00},
{IMX_8BIT, 0x040a, 0x00},
{IMX_8BIT, 0x040b, 0x00},
{IMX_8BIT, 0x040c, 0x02},
{IMX_8BIT, 0x040d, 0xe0},
{IMX_8BIT, 0x040e, 0x05},
{IMX_8BIT, 0x040f, 0x10},
{IMX_8BIT, 0x0900, 0x01},
{IMX_8BIT, 0x0901, 0x22},
{IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xdd}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3c}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* Binned 496x868 mode */
static struct imx_reg const imx_VIDEO_496x868_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0112, 0x0a},
{IMX_8BIT, 0x0113, 0x0a},
{IMX_8BIT, 0x0344, 0x02},
{IMX_8BIT, 0x0345, 0xc0},
{IMX_8BIT, 0x0346, 0x01},
{IMX_8BIT, 0x0347, 0xec},
{IMX_8BIT, 0x0348, 0x06},
{IMX_8BIT, 0x0349, 0x9f},
{IMX_8BIT, 0x034a, 0x08},
{IMX_8BIT, 0x034b, 0xb3},
{IMX_8BIT, 0x034c, 0x01},
{IMX_8BIT, 0x034d, 0xf0},
{IMX_8BIT, 0x034e, 0x03},
{IMX_8BIT, 0x034f, 0x64},
{IMX_8BIT, 0x0380, 0x00},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0382, 0x00},
{IMX_8BIT, 0x0383, 0x01},
{IMX_8BIT, 0x0384, 0x00},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0386, 0x00},
{IMX_8BIT, 0x0387, 0x01},
{IMX_8BIT, 0x0408, 0x00},
{IMX_8BIT, 0x0409, 0x00},
{IMX_8BIT, 0x040a, 0x00},
{IMX_8BIT, 0x040b, 0x00},
{IMX_8BIT, 0x040c, 0x01},
{IMX_8BIT, 0x040d, 0xf0},
{IMX_8BIT, 0x040e, 0x03},
{IMX_8BIT, 0x040f, 0x64},
{IMX_8BIT, 0x0900, 0x01},
{IMX_8BIT, 0x0901, 0x22},
{IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xdd}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3c}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
/* Hangout mode */
static struct imx_reg const imx_PREVIEW_374X652_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0112, 0x0a},
{IMX_8BIT, 0x0113, 0x0a},
{IMX_8BIT, 0x0344, 0x01},
{IMX_8BIT, 0x0345, 0xc0},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0x30},
{IMX_8BIT, 0x0348, 0x07},
{IMX_8BIT, 0x0349, 0x9f},
{IMX_8BIT, 0x034a, 0x0a},
{IMX_8BIT, 0x034b, 0x6f},
{IMX_8BIT, 0x034c, 0x01},
{IMX_8BIT, 0x034d, 0x78},
{IMX_8BIT, 0x034e, 0x02},
{IMX_8BIT, 0x034f, 0x90},
{IMX_8BIT, 0x0380, 0x00},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0382, 0x00},
{IMX_8BIT, 0x0383, 0x03},
{IMX_8BIT, 0x0384, 0x00},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0386, 0x00},
{IMX_8BIT, 0x0387, 0x03},
{IMX_8BIT, 0x0408, 0x00},
{IMX_8BIT, 0x0409, 0x00},
{IMX_8BIT, 0x040a, 0x00},
{IMX_8BIT, 0x040b, 0x02},
{IMX_8BIT, 0x040c, 0x01},
{IMX_8BIT, 0x040d, 0x76},
{IMX_8BIT, 0x040e, 0x02},
{IMX_8BIT, 0x040f, 0x8c},
{IMX_8BIT, 0x0900, 0x01},
{IMX_8BIT, 0x0901, 0x22},
{IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xde}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3c}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
static struct imx_reg const imx_VIDEO_NHD_9X16_30fps[] = {
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0112, 0x0a},
{IMX_8BIT, 0x0113, 0x0a},
{IMX_8BIT, 0x0344, 0x01},
{IMX_8BIT, 0x0345, 0xc0},
{IMX_8BIT, 0x0346, 0x00},
{IMX_8BIT, 0x0347, 0x30},
{IMX_8BIT, 0x0348, 0x07},
{IMX_8BIT, 0x0349, 0x9f},
{IMX_8BIT, 0x034a, 0x0a},
{IMX_8BIT, 0x034b, 0x6f},
{IMX_8BIT, 0x034c, 0x01},
{IMX_8BIT, 0x034d, 0x78},
{IMX_8BIT, 0x034e, 0x02},
{IMX_8BIT, 0x034f, 0x90},
{IMX_8BIT, 0x0380, 0x00},
{IMX_8BIT, 0x0381, 0x01},
{IMX_8BIT, 0x0382, 0x00},
{IMX_8BIT, 0x0383, 0x03},
{IMX_8BIT, 0x0384, 0x00},
{IMX_8BIT, 0x0385, 0x01},
{IMX_8BIT, 0x0386, 0x00},
{IMX_8BIT, 0x0387, 0x03},
{IMX_8BIT, 0x0408, 0x00},
{IMX_8BIT, 0x0409, 0x00},
{IMX_8BIT, 0x040a, 0x00},
{IMX_8BIT, 0x040b, 0x00},
{IMX_8BIT, 0x040c, 0x01},
{IMX_8BIT, 0x040d, 0x78},
{IMX_8BIT, 0x040e, 0x02},
{IMX_8BIT, 0x040f, 0x90},
{IMX_8BIT, 0x0900, 0x01},
{IMX_8BIT, 0x0901, 0x22},
{IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */
{IMX_8BIT, 0x9004, 0xde}, /* preset_sel */
{IMX_8BIT, 0x9005, 0x3c}, /* preset_en */
{IMX_8BIT, 0x0136, 0x13},
{IMX_8BIT, 0x0137, 0x33},
{IMX_TOK_TERM, 0, 0}
};
static struct imx_reg const imx227_init_settings[] = {
{IMX_8BIT, 0x0100, 0x00}, /* mode_select */
GROUPED_PARAMETER_HOLD_ENABLE,
{IMX_8BIT, 0x0306, 0x00},
{IMX_8BIT, 0x0307, 0xBB},
{IMX_8BIT, 0x030E, 0x03},
{IMX_8BIT, 0x030F, 0x0D},
{IMX_8BIT, 0x463b, 0x30},
{IMX_8BIT, 0x463e, 0x05},
{IMX_8BIT, 0x4612, 0x66},
{IMX_8BIT, 0x4815, 0x65},
{IMX_8BIT, 0x4991, 0x00},
{IMX_8BIT, 0x4992, 0x01},
{IMX_8BIT, 0x4993, 0xff},
{IMX_8BIT, 0x458b, 0x00},
{IMX_8BIT, 0x452a, 0x02},
{IMX_8BIT, 0x4a7c, 0x00},
{IMX_8BIT, 0x4a7d, 0x1c},
{IMX_8BIT, 0x4a7e, 0x00},
{IMX_8BIT, 0x4a7f, 0x17},
{IMX_8BIT, 0x462C, 0x2E},
{IMX_8BIT, 0x461B, 0x28},
{IMX_8BIT, 0x4663, 0x29},
{IMX_8BIT, 0x461A, 0x7C},
{IMX_8BIT, 0x4619, 0x28},
{IMX_8BIT, 0x4667, 0x22},
{IMX_8BIT, 0x466B, 0x23},
{IMX_8BIT, 0x40AD, 0xFF},
{IMX_8BIT, 0x40BE, 0x00},
{IMX_8BIT, 0x40BF, 0x6E},
{IMX_8BIT, 0x40CE, 0x00},
{IMX_8BIT, 0x40CF, 0x0A},
{IMX_8BIT, 0x40CA, 0x00},
{IMX_8BIT, 0x40CB, 0x1F},
{IMX_8BIT, 0x4D16, 0x00},
{IMX_8BIT, 0x6204, 0x01},
{IMX_8BIT, 0x6209, 0x00},
{IMX_8BIT, 0x621F, 0x01},
{IMX_8BIT, 0x621E, 0x10},
GROUPED_PARAMETER_HOLD_DISABLE,
{IMX_TOK_TERM, 0, 0}
};
/* TODO settings of preview/still/video will be updated with new use case */
struct imx_resolution imx227_res_preview[] = {
{
.desc = "imx_PREVIEW_374X652_30fps",
.regs = imx_PREVIEW_374X652_30fps,
.width = 374,
.height = 652,
.bin_factor_x = 2,
.bin_factor_y = 2,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0C0A,
},
{
}
},
},
{
.desc = "imx_VIDEO_496x868_30fps",
.regs = imx_VIDEO_496x868_30fps,
.width = 496,
.height = 868,
.bin_factor_x = 1,
.bin_factor_y = 1,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0C08,
},
{
}
},
},
{
.desc = "imx_STILL_5_5M_3X4_30fps",
.regs = imx_STILL_5_5M_3X4_30fps,
.width = 2048,
.height = 2720,
.bin_factor_x = 0,
.bin_factor_y = 0,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0ED8,
.lines_per_frame = 0x0BB8,
},
{
}
},
},
{
.desc = "imx_STILL_5_7M_1X1_30fps",
.regs = imx_STILL_5_7M_1X1_30fps,
.width = 2400,
.height = 2400,
.bin_factor_x = 0,
.bin_factor_y = 0,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x1130,
.lines_per_frame = 0x0A1E,
},
{
}
},
},
{
.desc = "imx_STILL_6_5M_25fps",
.regs = imx_STILL_6_5M_25fps,
.width = 2400,
.height = 2720,
.bin_factor_x = 0,
.bin_factor_y = 0,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 25,
.pixels_per_line = 0x1130,
.lines_per_frame = 0x0C24,
},
{
}
},
}
};
struct imx_resolution imx227_res_still[] = {
{
.desc = "imx_STILL_5_5M_3X4_30fps",
.regs = imx_STILL_5_5M_3X4_30fps,
.width = 2048,
.height = 2720,
.bin_factor_x = 0,
.bin_factor_y = 0,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 6,
.pixels_per_line = 0x2130,
.lines_per_frame = 0x1A22,
},
{
.fps = 30,
.pixels_per_line = 0x0ED8,
.lines_per_frame = 0x0BB8,
},
{
}
},
},
{
.desc = "imx_STILL_5_7M_1X1_30fps",
.regs = imx_STILL_5_7M_1X1_30fps,
.width = 2400,
.height = 2400,
.bin_factor_x = 0,
.bin_factor_y = 0,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 6,
.pixels_per_line = 0x266E,
.lines_per_frame = 0x1704,
},
{
.fps = 30,
.pixels_per_line = 0x1130,
.lines_per_frame = 0x0A1E,
},
{
}
},
},
{
.desc = "imx_STILL_6_5M_25fps",
.regs = imx_STILL_6_5M_25fps,
.width = 2400,
.height = 2720,
.bin_factor_x = 0,
.bin_factor_y = 0,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 25,
.pixels_per_line = 0x1130,
.lines_per_frame = 0x0C24,
},
{
}
},
},
};
struct imx_resolution imx227_res_video[] = {
{
.desc = "imx_VIDEO_4M_9X16_30fps",
.regs = imx_VIDEO_4M_9X16_30fps,
.width = 1536,
.height = 2720,
.bin_factor_x = 0,
.bin_factor_y = 0,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0C08,
},
{
}
},
},
{
.desc = "imx_VIDEO_2M_9X16_45fps",
.regs = imx_VIDEO_2M_9X16_45fps,
.width = 1096,
.height = 1936,
.bin_factor_x = 0,
.bin_factor_y = 0,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0C08,
},
{
.fps = 45,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0800,
},
{
}
},
},
{
.desc = "imx_VIDEO_1_3M_3X4_60fps",
.regs = imx_VIDEO_1_3M_3X4_60fps,
.width = 1024,
.height = 1360,
.bin_factor_x = 1,
.bin_factor_y = 1,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 60,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0604,
},
{
}
},
},
{
.desc = "imx_VIDEO_496x868_30fps",
.regs = imx_VIDEO_496x868_30fps,
.width = 496,
.height = 868,
.bin_factor_x = 1,
.bin_factor_y = 1,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0C08,
},
{
}
},
},
{
.desc = "imx_VIDEO_1M_9X16_60fps",
.regs = imx_VIDEO_1M_9X16_60fps,
.width = 736,
.height = 1296,
.bin_factor_x = 1,
.bin_factor_y = 1,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 60,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0604,
},
{
.fps = 30,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0C10,
},
{
}
},
},
{
.desc = "imx_VIDEO_VGA_3X4_120fps",
.regs = imx_VIDEO_VGA_3X4_120fps,
.width = 512,
.height = 680,
.bin_factor_x = 2,
.bin_factor_y = 2,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 120,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0302,
},
{
.fps = 30,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0C08,
},
{
}
},
},
{
.desc = "imx_VIDEO_NHD_9X16_30fps",
.regs = imx_VIDEO_NHD_9X16_30fps,
.width = 376,
.height = 656,
.bin_factor_x = 2,
.bin_factor_y = 2,
.mipi_freq = 499000,
.used = 0,
.fps_options = {
{
.fps = 30,
.pixels_per_line = 0x0E70,
.lines_per_frame = 0x0C0A,
},
{
}
},
},
};
#endif /* __IMX227_H__ */

39
drivers/staging/media/atomisp/i2c/imx/otp.c Normal file
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/*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
void *dummy_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
u8 *buf;
buf = devm_kzalloc(&client->dev, size, GFP_KERNEL);
if (!buf)
return ERR_PTR(-ENOMEM);
return buf;
}

81
drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c Normal file
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/*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include "common.h"
/*
* Read EEPROM data from brcc064 and store
* it into a kmalloced buffer. On error return NULL.
* @size: set to the size of the returned EEPROM data.
*/
void *brcc064_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
unsigned int e2prom_i2c_addr = dev_addr >> 1;
static const unsigned int max_read_size = 30;
int addr;
u32 s_addr = start_addr & E2PROM_ADDR_MASK;
unsigned char *buffer;
buffer = devm_kzalloc(&client->dev, size, GFP_KERNEL);
if (!buffer)
return NULL;
for (addr = s_addr; addr < size; addr += max_read_size) {
struct i2c_msg msg[2];
unsigned int i2c_addr = e2prom_i2c_addr;
u16 addr_buf;
int r;
msg[0].flags = 0;
msg[0].addr = i2c_addr;
addr_buf = cpu_to_be16(addr & 0xFFFF);
msg[0].len = 2;
msg[0].buf = (u8 *)&addr_buf;
msg[1].addr = i2c_addr;
msg[1].flags = I2C_M_RD;
msg[1].len = min(max_read_size, size - addr);
msg[1].buf = &buffer[addr];
r = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
if (r != ARRAY_SIZE(msg)) {
kfree(buffer);
dev_err(&client->dev, "read failed at 0x%03x\n", addr);
return NULL;
}
}
return buffer;
}

90
drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c Normal file
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/*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include "common.h"
/*
* Read EEPROM data from the gerneral e2prom chip(eg.
* CAT24C08, CAT24C128, le24l042cs, and store
* it into a kmalloced buffer. On error return NULL.
* @size: set to the size of the returned EEPROM data.
*/
void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
unsigned int e2prom_i2c_addr = dev_addr >> 1;
static const unsigned int max_read_size = 30;
int addr;
u32 s_addr = start_addr & E2PROM_ADDR_MASK;
bool two_addr = (start_addr & E2PROM_2ADDR) >> 31;
char *buffer;
buffer = devm_kzalloc(&client->dev, size, GFP_KERNEL);
if (!buffer)
return NULL;
for (addr = s_addr; addr < size; addr += max_read_size) {
struct i2c_msg msg[2];
unsigned int i2c_addr = e2prom_i2c_addr;
u16 addr_buf;
int r;
msg[0].flags = 0;
if (two_addr) {
msg[0].addr = i2c_addr;
addr_buf = cpu_to_be16(addr & 0xFFFF);
msg[0].len = 2;
msg[0].buf = (u8 *)&addr_buf;
} else {
i2c_addr |= (addr >> 8) & 0x7;
msg[0].addr = i2c_addr;
addr_buf = addr & 0xFF;
msg[0].len = 1;
msg[0].buf = (u8 *)&addr_buf;
}
msg[1].addr = i2c_addr;
msg[1].flags = I2C_M_RD;
msg[1].len = min(max_read_size, size - addr);
msg[1].buf = &buffer[addr];
r = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
if (r != ARRAY_SIZE(msg)) {
kfree(buffer);
dev_err(&client->dev, "read failed at 0x%03x\n", addr);
return NULL;
}
}
return buffer;
}

191
drivers/staging/media/atomisp/i2c/imx/otp_imx.c Normal file
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/*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include <asm/intel-mid.h>
#include "common.h"
/* Defines for OTP Data Registers */
#define IMX_OTP_START_ADDR 0x3B04
#define IMX_OTP_PAGE_SIZE 64
#define IMX_OTP_READY_REG 0x3B01
#define IMX_OTP_PAGE_REG 0x3B02
#define IMX_OTP_MODE_REG 0x3B00
#define IMX_OTP_PAGE_MAX 20
#define IMX_OTP_READY_REG_DONE 1
#define IMX_OTP_READ_ONETIME 32
#define IMX_OTP_MODE_READ 1
#define IMX227_OTP_START_ADDR 0x0A04
#define IMX227_OTP_ENABLE_REG 0x0A00
#define IMX227_OTP_READY_REG 0x0A01
#define IMX227_OTP_PAGE_REG 0x0A02
#define IMX227_OTP_READY_REG_DONE 1
#define IMX227_OTP_MODE_READ 1
static int
imx_read_otp_data(struct i2c_client *client, u16 len, u16 reg, void *val)
{
struct i2c_msg msg[2];
u16 data[IMX_SHORT_MAX] = { 0 };
int err;
if (len > IMX_BYTE_MAX) {
dev_err(&client->dev, "%s error, invalid data length\n",
__func__);
return -EINVAL;
}
memset(msg, 0 , sizeof(msg));
memset(data, 0 , sizeof(data));
msg[0].addr = client->addr;
msg[0].flags = 0;
msg[0].len = I2C_MSG_LENGTH;
msg[0].buf = (u8 *)data;
/* high byte goes first */
data[0] = cpu_to_be16(reg);
msg[1].addr = client->addr;
msg[1].len = len;
msg[1].flags = I2C_M_RD;
msg[1].buf = (u8 *)data;
err = i2c_transfer(client->adapter, msg, 2);
if (err != 2) {
if (err >= 0)
err = -EIO;
goto error;
}
memcpy(val, data, len);
return 0;
error:
dev_err(&client->dev, "read from offset 0x%x error %d", reg, err);
return err;
}
static int imx_read_otp_reg_array(struct i2c_client *client, u16 size, u16 addr,
u8 *buf)
{
u16 index;
int ret;
for (index = 0; index + IMX_OTP_READ_ONETIME <= size;
index += IMX_OTP_READ_ONETIME) {
ret = imx_read_otp_data(client, IMX_OTP_READ_ONETIME,
addr + index, &buf[index]);
if (ret)
return ret;
}
return 0;
}
void *imx_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
u8 *buf;
int ret;
int i;
buf = devm_kzalloc(&client->dev, size, GFP_KERNEL);
if (!buf)
return ERR_PTR(-ENOMEM);
for (i = 0; i < IMX_OTP_PAGE_MAX; i++) {
/*set page NO.*/
ret = imx_write_reg(client, IMX_8BIT,
IMX_OTP_PAGE_REG, i & 0xff);
if (ret)
goto fail;
/*set read mode*/
ret = imx_write_reg(client, IMX_8BIT,
IMX_OTP_MODE_REG, IMX_OTP_MODE_READ);
if (ret)
goto fail;
/* Reading the OTP data array */
ret = imx_read_otp_reg_array(client, IMX_OTP_PAGE_SIZE,
IMX_OTP_START_ADDR, buf + i * IMX_OTP_PAGE_SIZE);
if (ret)
goto fail;
}
return buf;
fail:
/* Driver has failed to find valid data */
dev_err(&client->dev, "sensor found no valid OTP data\n");
return ERR_PTR(ret);
}
void *imx227_otp_read(struct v4l2_subdev *sd, u8 dev_addr,
u32 start_addr, u32 size)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
u8 *buf;
int ret;
int i;
buf = devm_kzalloc(&client->dev, size, GFP_KERNEL);
if (!buf)
return ERR_PTR(-ENOMEM);
for (i = 0; i < IMX_OTP_PAGE_MAX; i++) {
/*set page NO.*/
ret = imx_write_reg(client, IMX_8BIT,
IMX227_OTP_PAGE_REG, i & 0xff);
if (ret)
goto fail;
/*set read mode*/
ret = imx_write_reg(client, IMX_8BIT,
IMX227_OTP_ENABLE_REG, IMX227_OTP_MODE_READ);
if (ret)
goto fail;
/* Reading the OTP data array */
ret = imx_read_otp_reg_array(client, IMX_OTP_PAGE_SIZE,
IMX227_OTP_START_ADDR, buf + i * IMX_OTP_PAGE_SIZE);
if (ret)
goto fail;
}
return buf;
fail:
/* Driver has failed to find valid data */
dev_err(&client->dev, "sensor found no valid OTP data\n");
return ERR_PTR(ret);
}

45
drivers/staging/media/atomisp/i2c/imx/vcm.c Normal file
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/*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <media/v4l2-device.h>
#include <linux/atomisp_platform.h>
int vcm_power_up(struct v4l2_subdev *sd)
{
const struct camera_af_platform_data *vcm_platform_data;
vcm_platform_data = camera_get_af_platform_data();
if (NULL == vcm_platform_data)
return -ENODEV;
/* Enable power */
return vcm_platform_data->power_ctrl(sd, 1);
}
int vcm_power_down(struct v4l2_subdev *sd)
{
const struct camera_af_platform_data *vcm_platform_data;
vcm_platform_data = camera_get_af_platform_data();
if (NULL == vcm_platform_data)
return -ENODEV;
return vcm_platform_data->power_ctrl(sd, 0);
}

209
drivers/staging/media/atomisp/i2c/libmsrlisthelper.c Normal file
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/*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/i2c.h>
#include <linux/firmware.h>
#include <linux/device.h>
#include <linux/export.h>
#include <linux/libmsrlisthelper.h>
#include <linux/module.h>
#include <linux/slab.h>
/* Tagged binary data container structure definitions. */
struct tbd_header {
uint32_t tag; /*!< Tag identifier, also checks endianness */
uint32_t size; /*!< Container size including this header */
uint32_t version; /*!< Version, format 0xYYMMDDVV */
uint32_t revision; /*!< Revision, format 0xYYMMDDVV */
uint32_t config_bits; /*!< Configuration flag bits set */
uint32_t checksum; /*!< Global checksum, header included */
} __packed;
struct tbd_record_header {
uint32_t size; /*!< Size of record including header */
uint8_t format_id; /*!< tbd_format_t enumeration values used */
uint8_t packing_key; /*!< Packing method; 0 = no packing */
uint16_t class_id; /*!< tbd_class_t enumeration values used */
} __packed;
struct tbd_data_record_header {
uint16_t next_offset;
uint16_t flags;
uint16_t data_offset;
uint16_t data_size;
} __packed;
#define TBD_CLASS_DRV_ID 2
static int set_msr_configuration(struct i2c_client *client, uint8_t *bufptr,
unsigned int size)
{
/* The configuration data contains any number of sequences where
* the first byte (that is, uint8_t) that marks the number of bytes
* in the sequence to follow, is indeed followed by the indicated
* number of bytes of actual data to be written to sensor.
* By convention, the first two bytes of actual data should be
* understood as an address in the sensor address space (hibyte
* followed by lobyte) where the remaining data in the sequence
* will be written. */
uint8_t *ptr = bufptr;
while (ptr < bufptr + size) {
struct i2c_msg msg = {
.addr = client->addr,
.flags = 0,
};
int ret;
/* How many bytes */
msg.len = *ptr++;
/* Where the bytes are located */
msg.buf = ptr;
ptr += msg.len;
if (ptr > bufptr + size)
/* Accessing data beyond bounds is not tolerated */
return -EINVAL;
ret = i2c_transfer(client->adapter, &msg, 1);
if (ret < 0) {
dev_err(&client->dev, "i2c write error: %d", ret);
return ret;
}
}
return 0;
}
static int parse_and_apply(struct i2c_client *client, uint8_t *buffer,
unsigned int size)
{
uint8_t *endptr8 = buffer + size;
struct tbd_data_record_header *header =
(struct tbd_data_record_header *)buffer;
/* There may be any number of datasets present */
unsigned int dataset = 0;
do {
/* In below, four variables are read from buffer */
if ((uint8_t *)header + sizeof(*header) > endptr8)
return -EINVAL;
/* All data should be located within given buffer */
if ((uint8_t *)header + header->data_offset +
header->data_size > endptr8)
return -EINVAL;
/* We have a new valid dataset */
dataset++;
/* See whether there is MSR data */
/* If yes, update the reg info */
if (header->data_size && (header->flags & 1)) {
int ret;
dev_info(&client->dev,
"New MSR data for sensor driver (dataset %02d) size:%d\n",
dataset, header->data_size);
ret = set_msr_configuration(client,
buffer + header->data_offset,
header->data_size);
if (ret)
return ret;
}
header = (struct tbd_data_record_header *)(buffer +
header->next_offset);
} while (header->next_offset);
return 0;
}
int apply_msr_data(struct i2c_client *client, const struct firmware *fw)
{
struct tbd_header *header;
struct tbd_record_header *record;
if (!fw) {
dev_warn(&client->dev, "Drv data is not loaded.\n");
return -EINVAL;
}
if (sizeof(*header) > fw->size)
return -EINVAL;
header = (struct tbd_header *)fw->data;
/* Check that we have drvb block. */
if (memcmp(&header->tag, "DRVB", 4))
return -EINVAL;
/* Check the size */
if (header->size != fw->size)
return -EINVAL;
if (sizeof(*header) + sizeof(*record) > fw->size)
return -EINVAL;
record = (struct tbd_record_header *)(header + 1);
/* Check that class id mathes tbd's drv id. */
if (record->class_id != TBD_CLASS_DRV_ID)
return -EINVAL;
/* Size 0 shall not be treated as an error */
if (!record->size)
return 0;
return parse_and_apply(client, (uint8_t *)(record + 1), record->size);
}
EXPORT_SYMBOL_GPL(apply_msr_data);
int load_msr_list(struct i2c_client *client, char *name,
const struct firmware **fw)
{
int ret = request_firmware(fw, name, &client->dev);
if (ret) {
dev_err(&client->dev,
"Error %d while requesting firmware %s\n",
ret, name);
return ret;
}
dev_info(&client->dev, "Received %lu bytes drv data\n",
(unsigned long)(*fw)->size);
return 0;
}
EXPORT_SYMBOL_GPL(load_msr_list);
void release_msr_list(struct i2c_client *client, const struct firmware *fw)
{
release_firmware(fw);
}
EXPORT_SYMBOL_GPL(release_msr_list);
static int init_msrlisthelper(void)
{
return 0;
}
static void exit_msrlisthelper(void)
{
}
module_init(init_msrlisthelper);
module_exit(exit_msrlisthelper);
MODULE_AUTHOR("Jukka Kaartinen <jukka.o.kaartinen@intel.com>");
MODULE_LICENSE("GPL");

1010
drivers/staging/media/atomisp/i2c/lm3554.c Normal file
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1969
drivers/staging/media/atomisp/i2c/mt9m114.c Normal file
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1786
drivers/staging/media/atomisp/i2c/mt9m114.h Normal file
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1562
drivers/staging/media/atomisp/i2c/ov2680.c Normal file
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drivers/staging/media/atomisp/i2c/ov2680.h Normal file
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/*
* Support for OmniVision OV2680 5M camera sensor.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __OV2680_H__
#define __OV2680_H__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/spinlock.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <linux/v4l2-mediabus.h>
#include <media/media-entity.h>
#include <linux/atomisp_platform.h>
#define OV2680_NAME "ov2680"
#define OV2680B_NAME "ov2680b"
#define OV2680F_NAME "ov2680f"
/* Defines for register writes and register array processing */
#define I2C_MSG_LENGTH 0x2
#define I2C_RETRY_COUNT 5
#define OV2680_FOCAL_LENGTH_NUM 334 /*3.34mm*/
#define OV2680_FOCAL_LENGTH_DEM 100
#define OV2680_F_NUMBER_DEFAULT_NUM 24
#define OV2680_F_NUMBER_DEM 10
#define OV2680_BIN_FACTOR_MAX 4
#define MAX_FMTS 1
/* sensor_mode_data read_mode adaptation */
#define OV2680_READ_MODE_BINNING_ON 0x0400
#define OV2680_READ_MODE_BINNING_OFF 0x00
#define OV2680_INTEGRATION_TIME_MARGIN 8
#define OV2680_MAX_EXPOSURE_VALUE 0xFFF1
#define OV2680_MAX_GAIN_VALUE 0xFF
/*
* focal length bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define OV2680_FOCAL_LENGTH_DEFAULT 0x1B70064
/*
* current f-number bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define OV2680_F_NUMBER_DEFAULT 0x18000a
/*
* f-number range bits definition:
* bits 31-24: max f-number numerator
* bits 23-16: max f-number denominator
* bits 15-8: min f-number numerator
* bits 7-0: min f-number denominator
*/
#define OV2680_F_NUMBER_RANGE 0x180a180a
#define OV2680_ID 0x2680
#define OV2680_FINE_INTG_TIME_MIN 0
#define OV2680_FINE_INTG_TIME_MAX_MARGIN 0
#define OV2680_COARSE_INTG_TIME_MIN 1
#define OV2680_COARSE_INTG_TIME_MAX_MARGIN 6
/*
* OV2680 System control registers
*/
#define OV2680_SW_SLEEP 0x0100
#define OV2680_SW_RESET 0x0103
#define OV2680_SW_STREAM 0x0100
#define OV2680_SC_CMMN_CHIP_ID_H 0x300A
#define OV2680_SC_CMMN_CHIP_ID_L 0x300B
#define OV2680_SC_CMMN_SCCB_ID 0x302B /* 0x300C*/
#define OV2680_SC_CMMN_SUB_ID 0x302A /* process, version*/
#define OV2680_GROUP_ACCESS 0x3208 /*Bit[7:4] Group control, Bit[3:0] Group ID*/
#define OV2680_EXPOSURE_H 0x3500 /*Bit[3:0] Bit[19:16] of exposure, remaining 16 bits lies in Reg0x3501&Reg0x3502*/
#define OV2680_EXPOSURE_M 0x3501
#define OV2680_EXPOSURE_L 0x3502
#define OV2680_AGC_H 0x350A /*Bit[1:0] means Bit[9:8] of gain*/
#define OV2680_AGC_L 0x350B /*Bit[7:0] of gain*/
#define OV2680_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/
#define OV2680_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/
#define OV2680_VERTICAL_START_H 0x3802 /*Bit[11:8]*/
#define OV2680_VERTICAL_START_L 0x3803 /*Bit[7:0]*/
#define OV2680_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/
#define OV2680_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/
#define OV2680_VERTICAL_END_H 0x3806 /*Bit[11:8]*/
#define OV2680_VERTICAL_END_L 0x3807 /*Bit[7:0]*/
#define OV2680_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/
#define OV2680_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/
#define OV2680_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/
#define OV2680_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/
#define OV2680_TIMING_HTS_H 0x380C /*High 8-bit, and low 8-bit HTS address is 0x380d*/
#define OV2680_TIMING_HTS_L 0x380D /*High 8-bit, and low 8-bit HTS address is 0x380d*/
#define OV2680_TIMING_VTS_H 0x380e /*High 8-bit, and low 8-bit HTS address is 0x380f*/
#define OV2680_TIMING_VTS_L 0x380f /*High 8-bit, and low 8-bit HTS address is 0x380f*/
#define OV2680_FRAME_OFF_NUM 0x4202
/*Flip/Mirror*/
#define OV2680_FLIP_REG 0x3820
#define OV2680_MIRROR_REG 0x3821
#define OV2680_FLIP_BIT 1
#define OV2680_MIRROR_BIT 2
#define OV2680_FLIP_MIRROR_BIT_ENABLE 4
#define OV2680_MWB_RED_GAIN_H 0x5004/*0x3400*/
#define OV2680_MWB_GREEN_GAIN_H 0x5006/*0x3402*/
#define OV2680_MWB_BLUE_GAIN_H 0x5008/*0x3404*/
#define OV2680_MWB_GAIN_MAX 0x0fff
#define OV2680_START_STREAMING 0x01
#define OV2680_STOP_STREAMING 0x00
#define OV2680_INVALID_CONFIG 0xffffffff
struct regval_list {
u16 reg_num;
u8 value;
};
struct ov2680_resolution {
u8 *desc;
const struct ov2680_reg *regs;
int res;
int width;
int height;
int fps;
int pix_clk_freq;
u32 skip_frames;
u16 pixels_per_line;
u16 lines_per_frame;
u8 bin_factor_x;
u8 bin_factor_y;
u8 bin_mode;
bool used;
};
struct ov2680_format {
u8 *desc;
u32 pixelformat;
struct ov2680_reg *regs;
};
/*
* ov2680 device structure.
*/
struct ov2680_device {
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_mbus_framefmt format;
struct mutex input_lock;
struct v4l2_ctrl_handler ctrl_handler;
struct camera_sensor_platform_data *platform_data;
struct timespec timestamp_t_focus_abs;
int vt_pix_clk_freq_mhz;
int fmt_idx;
int run_mode;
u8 res;
u8 type;
};
enum ov2680_tok_type {
OV2680_8BIT = 0x0001,
OV2680_16BIT = 0x0002,
OV2680_32BIT = 0x0004,
OV2680_TOK_TERM = 0xf000, /* terminating token for reg list */
OV2680_TOK_DELAY = 0xfe00, /* delay token for reg list */
OV2680_TOK_MASK = 0xfff0
};
/**
* struct ov2680_reg - MI sensor register format
* @type: type of the register
* @reg: 16-bit offset to register
* @val: 8/16/32-bit register value
*
* Define a structure for sensor register initialization values
*/
struct ov2680_reg {
enum ov2680_tok_type type;
u16 reg;
u32 val; /* @set value for read/mod/write, @mask */
};
#define to_ov2680_sensor(x) container_of(x, struct ov2680_device, sd)
#define OV2680_MAX_WRITE_BUF_SIZE 30
struct ov2680_write_buffer {
u16 addr;
u8 data[OV2680_MAX_WRITE_BUF_SIZE];
};
struct ov2680_write_ctrl {
int index;
struct ov2680_write_buffer buffer;
};
static const struct i2c_device_id ov2680_id[] = {
{OV2680B_NAME, 0},
{OV2680F_NAME, 0},
{}
};
static struct ov2680_reg const ov2680_global_setting[] = {
{OV2680_8BIT, 0x0103, 0x01},
{OV2680_8BIT, 0x3002, 0x00},
{OV2680_8BIT, 0x3016, 0x1c},
{OV2680_8BIT, 0x3018, 0x44},
{OV2680_8BIT, 0x3020, 0x00},
{OV2680_8BIT, 0x3080, 0x02},
{OV2680_8BIT, 0x3082, 0x45},
{OV2680_8BIT, 0x3084, 0x09},
{OV2680_8BIT, 0x3085, 0x04},
{OV2680_8BIT, 0x3503, 0x03},
{OV2680_8BIT, 0x350b, 0x36},
{OV2680_8BIT, 0x3600, 0xb4},
{OV2680_8BIT, 0x3603, 0x39},
{OV2680_8BIT, 0x3604, 0x24},
{OV2680_8BIT, 0x3605, 0x00},
{OV2680_8BIT, 0x3620, 0x26},
{OV2680_8BIT, 0x3621, 0x37},
{OV2680_8BIT, 0x3622, 0x04},
{OV2680_8BIT, 0x3628, 0x00},
{OV2680_8BIT, 0x3705, 0x3c},
{OV2680_8BIT, 0x370c, 0x50},
{OV2680_8BIT, 0x370d, 0xc0},
{OV2680_8BIT, 0x3718, 0x88},
{OV2680_8BIT, 0x3720, 0x00},
{OV2680_8BIT, 0x3721, 0x00},
{OV2680_8BIT, 0x3722, 0x00},
{OV2680_8BIT, 0x3723, 0x00},
{OV2680_8BIT, 0x3738, 0x00},
{OV2680_8BIT, 0x3717, 0x58},
{OV2680_8BIT, 0x3781, 0x80},
{OV2680_8BIT, 0x3789, 0x60},
{OV2680_8BIT, 0x3800, 0x00},
{OV2680_8BIT, 0x3819, 0x04},
{OV2680_8BIT, 0x4000, 0x81},
{OV2680_8BIT, 0x4001, 0x40},
{OV2680_8BIT, 0x4602, 0x02},
{OV2680_8BIT, 0x481f, 0x36},
{OV2680_8BIT, 0x4825, 0x36},
{OV2680_8BIT, 0x4837, 0x18},
{OV2680_8BIT, 0x5002, 0x30},
{OV2680_8BIT, 0x5004, 0x04},//manual awb 1x
{OV2680_8BIT, 0x5005, 0x00},
{OV2680_8BIT, 0x5006, 0x04},
{OV2680_8BIT, 0x5007, 0x00},
{OV2680_8BIT, 0x5008, 0x04},
{OV2680_8BIT, 0x5009, 0x00},
{OV2680_8BIT, 0x5080, 0x00},
{OV2680_8BIT, 0x3701, 0x64}, //add on 14/05/13
{OV2680_8BIT, 0x3784, 0x0c}, //based OV2680_R1A_AM10.ovt add on 14/06/13
{OV2680_8BIT, 0x5780, 0x3e}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13
{OV2680_8BIT, 0x5781, 0x0f},
{OV2680_8BIT, 0x5782, 0x04},
{OV2680_8BIT, 0x5783, 0x02},
{OV2680_8BIT, 0x5784, 0x01},
{OV2680_8BIT, 0x5785, 0x01},
{OV2680_8BIT, 0x5786, 0x00},
{OV2680_8BIT, 0x5787, 0x04},
{OV2680_8BIT, 0x5788, 0x02},
{OV2680_8BIT, 0x5789, 0x00},
{OV2680_8BIT, 0x578a, 0x01},
{OV2680_8BIT, 0x578b, 0x02},
{OV2680_8BIT, 0x578c, 0x03},
{OV2680_8BIT, 0x578d, 0x03},
{OV2680_8BIT, 0x578e, 0x08},
{OV2680_8BIT, 0x578f, 0x0c},
{OV2680_8BIT, 0x5790, 0x08},
{OV2680_8BIT, 0x5791, 0x04},
{OV2680_8BIT, 0x5792, 0x00},
{OV2680_8BIT, 0x5793, 0x00},
{OV2680_8BIT, 0x5794, 0x03}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13
{OV2680_8BIT, 0x0100, 0x00}, //stream off
{OV2680_TOK_TERM, 0, 0}
};
/*
* 176x144 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_QCIF_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x24},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xaf},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0x47},
{OV2680_8BIT, 0x3808, 0x00},
{OV2680_8BIT, 0x3809, 0xC0},
{OV2680_8BIT, 0x380a, 0x00},
{OV2680_8BIT, 0x380b, 0xa0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xb0},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x04},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x04},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4000, 0x81},
{OV2680_8BIT, 0x4001, 0x40},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 352x288 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_CIF_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x24},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x03},
{OV2680_8BIT, 0x3805, 0x8f},
{OV2680_8BIT, 0x3806, 0x02},
{OV2680_8BIT, 0x3807, 0xe7},
{OV2680_8BIT, 0x3808, 0x01},
{OV2680_8BIT, 0x3809, 0x70},
{OV2680_8BIT, 0x380a, 0x01},
{OV2680_8BIT, 0x380b, 0x30},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xb0},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x04},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x04},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 336x256 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_QVGA_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x24},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x03},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x02},
{OV2680_8BIT, 0x3807, 0x87},
{OV2680_8BIT, 0x3808, 0x01},
{OV2680_8BIT, 0x3809, 0x50},
{OV2680_8BIT, 0x380a, 0x01},
{OV2680_8BIT, 0x380b, 0x00},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xb0},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x04},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x04},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 656x496 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_656x496_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x24},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xcf},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0x67},
{OV2680_8BIT, 0x3808, 0x02},
{OV2680_8BIT, 0x3809, 0x90},
{OV2680_8BIT, 0x380a, 0x01},
{OV2680_8BIT, 0x380b, 0xf0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xb0},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x04},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x04},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 800x600 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_720x592_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x26},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0x00}, // X_ADDR_START;
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x00}, // Y_ADDR_START;
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xaf}, // X_ADDR_END;
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xaf}, // Y_ADDR_END;
{OV2680_8BIT, 0x3808, 0x02},
{OV2680_8BIT, 0x3809, 0xd0}, // X_OUTPUT_SIZE;
{OV2680_8BIT, 0x380a, 0x02},
{OV2680_8BIT, 0x380b, 0x50}, // Y_OUTPUT_SIZE;
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xac}, // HTS;
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84}, // VTS;
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5708, 0x00},
{OV2680_8BIT, 0x5704, 0x02},
{OV2680_8BIT, 0x5705, 0xd0}, // X_WIN;
{OV2680_8BIT, 0x5706, 0x02},
{OV2680_8BIT, 0x5707, 0x50}, // Y_WIN;
{OV2680_8BIT, 0x3820, 0xc2}, // FLIP_FORMAT;
{OV2680_8BIT, 0x3821, 0x01}, // MIRROR_FORMAT;
{OV2680_8BIT, 0x5090, 0x00}, // PRE ISP CTRL16, default value is 0x0C;
// BIT[3]: Mirror order, BG or GB;
// BIT[2]: Flip order, BR or RB;
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 800x600 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_800x600_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x26},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0x00},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x00},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xbf},
{OV2680_8BIT, 0x3808, 0x03},
{OV2680_8BIT, 0x3809, 0x20},
{OV2680_8BIT, 0x380a, 0x02},
{OV2680_8BIT, 0x380b, 0x58},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xac},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x5708, 0x00},
{OV2680_8BIT, 0x5704, 0x03},
{OV2680_8BIT, 0x5705, 0x20},
{OV2680_8BIT, 0x5706, 0x02},
{OV2680_8BIT, 0x5707, 0x58},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
{OV2680_8BIT, 0x5090, 0x00},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 720p=1280*720 30fps VBlanking 1lane 10Bit (no-Scaling)
*/
static struct ov2680_reg const ov2680_720p_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0xf2},
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xbf},
{OV2680_8BIT, 0x3806, 0x03},
{OV2680_8BIT, 0x3807, 0xdd},
{OV2680_8BIT, 0x3808, 0x05},
{OV2680_8BIT, 0x3809, 0x10},
{OV2680_8BIT, 0x380a, 0x02},
{OV2680_8BIT, 0x380b, 0xe0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x08},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x06},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 1296x976 30fps VBlanking 1lane 10Bit(no-scaling)
*/
static struct ov2680_reg const ov2680_1296x976_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xbf},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0x57},
{OV2680_8BIT, 0x3808, 0x05},
{OV2680_8BIT, 0x3809, 0x10},
{OV2680_8BIT, 0x380a, 0x03},
{OV2680_8BIT, 0x380b, 0xd0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x08},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x08},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00}, //miror/flip
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 1456*1096 30fps VBlanking 1lane 10bit(no-scaling)
*/
static struct ov2680_reg const ov2680_1456x1096_30fps[]= {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0x90},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xC0},
{OV2680_8BIT, 0x3808, 0x05},
{OV2680_8BIT, 0x3809, 0xb0},
{OV2680_8BIT, 0x380a, 0x04},
{OV2680_8BIT, 0x380b, 0x48},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x08},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
*1616x916 30fps VBlanking 1lane 10bit
*/
static struct ov2680_reg const ov2680_1616x916_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0x00},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x96},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0x39},
{OV2680_8BIT, 0x3808, 0x06},
{OV2680_8BIT, 0x3809, 0x50},
{OV2680_8BIT, 0x380a, 0x03},
{OV2680_8BIT, 0x380b, 0x94},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x08},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x06},
{OV2680_8BIT, 0x5705, 0x50},
{OV2680_8BIT, 0x5706, 0x03},
{OV2680_8BIT, 0x5707, 0x94},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0C},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 1612x1212 30fps VBlanking 1lane 10Bit
*/
static struct ov2680_reg const ov2680_1616x1082_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0x00},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x86},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xbf},
{OV2680_8BIT, 0x3808, 0x06},
{OV2680_8BIT, 0x3809, 0x50},
{OV2680_8BIT, 0x380a, 0x04},
{OV2680_8BIT, 0x380b, 0x3a},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x06},
{OV2680_8BIT, 0x5705, 0x50},
{OV2680_8BIT, 0x5706, 0x04},
{OV2680_8BIT, 0x5707, 0x3a},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0C},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 1616x1216 30fps VBlanking 1lane 10Bit
*/
static struct ov2680_reg const ov2680_1616x1216_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0x00},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x00},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xbf},
{OV2680_8BIT, 0x3808, 0x06},
{OV2680_8BIT, 0x3809, 0x50},//50},//4line for mirror and flip
{OV2680_8BIT, 0x380a, 0x04},
{OV2680_8BIT, 0x380b, 0xc0},//c0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x0b},
{OV2680_8BIT, 0x5081, 0x01},
{OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x06},
{OV2680_8BIT, 0x5705, 0x50},
{OV2680_8BIT, 0x5706, 0x04},
{OV2680_8BIT, 0x5707, 0xcc},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0C},
{OV2680_TOK_TERM, 0, 0}
};
static struct ov2680_resolution ov2680_res_preview[] = {
{
.desc = "ov2680_1616x1216_30fps",
.width = 1616,
.height = 1216,
.pix_clk_freq = 66,
.fps = 30,
.used = 0,
.pixels_per_line = 1698,//1704,
.lines_per_frame = 1294,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = ov2680_1616x1216_30fps,
},
{
.desc = "ov2680_1616x916_30fps",
.width = 1616,
.height = 916,
.fps = 30,
.pix_clk_freq = 66,
.used = 0,
.pixels_per_line = 1698,//1704,
.lines_per_frame = 1294,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = ov2680_1616x916_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview))
static struct ov2680_resolution ov2680_res_still[] = {
{
.desc = "ov2680_1616x1216_30fps",
.width = 1616,
.height = 1216,
.pix_clk_freq = 66,
.fps = 30,
.used = 0,
.pixels_per_line = 1698,//1704,
.lines_per_frame = 1294,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = ov2680_1616x1216_30fps,
},
{
.desc = "ov2680_1616x916_30fps",
.width = 1616,
.height = 916,
.fps = 30,
.pix_clk_freq = 66,
.used = 0,
.pixels_per_line = 1698,//1704,
.lines_per_frame = 1294,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = ov2680_1616x916_30fps,
},
};
#define N_RES_STILL (ARRAY_SIZE(ov2680_res_still))
static struct ov2680_resolution ov2680_res_video[] = {
{
.desc = "ov2680_1616x1216_30fps",
.width = 1616,
.height = 1216,
.pix_clk_freq = 66,
.fps = 30,
.used = 0,
.pixels_per_line = 1698,//1704,
.lines_per_frame = 1294,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = ov2680_1616x1216_30fps,
},
{
.desc = "ov2680_720p_30fps",
.width = 1616,
.height = 916,
.fps = 30,
.pix_clk_freq = 66,
.used = 0,
.pixels_per_line = 1698,//1704,
.lines_per_frame = 1294,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = ov2680_1616x916_30fps,
},
};
#define N_RES_VIDEO (ARRAY_SIZE(ov2680_res_video))
static struct ov2680_resolution *ov2680_res = ov2680_res_preview;
static int N_RES = N_RES_PREVIEW;
#endif

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config VIDEO_OV5693
tristate "Omnivision ov5693 sensor support"
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the Micron
ov5693 5 Mpixel camera.
ov5693 is video camera sensor.
It currently only works with the atomisp driver.

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obj-$(CONFIG_VIDEO_OV5693) += ov5693.o
ccflags-y += -Werror

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/*
* Support for AD5823 VCM.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __AD5823_H__
#define __AD5823_H__
#include <linux/types.h>
#define AD5823_VCM_ADDR 0x0c
#define AD5823_REG_RESET 0x01
#define AD5823_REG_MODE 0x02
#define AD5823_REG_VCM_MOVE_TIME 0x03
#define AD5823_REG_VCM_CODE_MSB 0x04
#define AD5823_REG_VCM_CODE_LSB 0x05
#define AD5823_REG_VCM_THRESHOLD_MSB 0x06
#define AD5823_REG_VCM_THRESHOLD_LSB 0x07
#define AD5823_REG_LENGTH 0x1
#define AD5823_RING_CTRL_ENABLE 0x04
#define AD5823_RING_CTRL_DISABLE 0x00
#define AD5823_RESONANCE_PERIOD 100000
#define AD5823_RESONANCE_COEF 512
#define AD5823_HIGH_FREQ_RANGE 0x80
#define VCM_CODE_MSB_MASK 0xfc
#define AD5823_INIT_FOCUS_POS 350
enum ad5823_tok_type {
AD5823_8BIT = 0x1,
AD5823_16BIT = 0x2,
};
enum ad5823_vcm_mode {
AD5823_ARC_RES0 = 0x0, /* Actuator response control RES1 */
AD5823_ARC_RES1 = 0x1, /* Actuator response control RES0.5 */
AD5823_ARC_RES2 = 0x2, /* Actuator response control RES2 */
AD5823_ESRC = 0x3, /* Enhanced slew rate control */
AD5823_DIRECT = 0x4, /* Direct control */
};
#define AD5823_INVALID_CONFIG 0xffffffff
#define AD5823_MAX_FOCUS_POS 1023
#define DELAY_PER_STEP_NS 1000000
#define DELAY_MAX_PER_STEP_NS (1000000 * 1023)
#endif

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/*
* Access to message bus through three registers
* in CUNIT(0:0:0) PCI configuration space.
* MSGBUS_CTRL_REG(0xD0):
* 31:24 = message bus opcode
* 23:16 = message bus port
* 15:8 = message bus address, low 8 bits.
* 7:4 = message bus byte enables
* MSGBUS_CTRL_EXT_REG(0xD8):
* 31:8 = message bus address, high 24 bits.
* MSGBUS_DATA_REG(0xD4):
* hold the data for write or read
*/
#define PCI_ROOT_MSGBUS_CTRL_REG 0xD0
#define PCI_ROOT_MSGBUS_DATA_REG 0xD4
#define PCI_ROOT_MSGBUS_CTRL_EXT_REG 0xD8
#define PCI_ROOT_MSGBUS_READ 0x10
#define PCI_ROOT_MSGBUS_WRITE 0x11
#define PCI_ROOT_MSGBUS_DWORD_ENABLE 0xf0
/* In BYT platform for all internal PCI devices d3 delay
* of 3 ms is sufficient. Default value of 10 ms is overkill.
*/
#define INTERNAL_PCI_PM_D3_WAIT 3
#define ISP_SUB_CLASS 0x80
#define SUB_CLASS_MASK 0xFF00
u32 intel_mid_msgbus_read32_raw(u32 cmd);
u32 intel_mid_msgbus_read32(u8 port, u32 addr);
void intel_mid_msgbus_write32_raw(u32 cmd, u32 data);
void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data);
u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext);
void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data);
u32 intel_mid_soc_stepping(void);
int intel_mid_dw_i2c_acquire_ownership(void);
int intel_mid_dw_i2c_release_ownership(void);

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/*
* Support for Intel MID SoC Camera Imaging ISP subsystem.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef ATOMISP_GMIN_PLATFORM_H_
#define ATOMISP_GMIN_PLATFORM_H_
#include <linux/atomisp_platform.h>
const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void);
const struct atomisp_platform_data *atomisp_get_platform_data(void);
const struct camera_af_platform_data *camera_get_af_platform_data(void);
int atomisp_register_i2c_module(struct v4l2_subdev *subdev,
struct camera_sensor_platform_data *plat_data,
enum intel_v4l2_subdev_type type);
struct v4l2_subdev *atomisp_gmin_find_subdev(struct i2c_adapter *adapter,
struct i2c_board_info *board_info);
int atomisp_gmin_remove_subdev(struct v4l2_subdev *sd);
int gmin_get_config_var(struct device *dev, const char *var, char *out, size_t *out_len);
int gmin_get_var_int(struct device *dev, const char *var, int def);
int camera_sensor_csi(struct v4l2_subdev *sd, u32 port,
u32 lanes, u32 format, u32 bayer_order, int flag);
struct camera_sensor_platform_data *gmin_camera_platform_data(
struct v4l2_subdev *subdev,
enum atomisp_input_format csi_format,
enum atomisp_bayer_order csi_bayer);
int atomisp_gmin_register_vcm_control(struct camera_vcm_control *);
#endif

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef ATOMISP_PLATFORM_H_
#define ATOMISP_PLATFORM_H_
#include <linux/i2c.h>
#include <linux/sfi.h>
#include <media/v4l2-subdev.h>
#include "atomisp.h"
#define MAX_SENSORS_PER_PORT 4
#define MAX_STREAMS_PER_CHANNEL 2
#define CAMERA_MODULE_ID_LEN 64
enum atomisp_bayer_order {
atomisp_bayer_order_grbg,
atomisp_bayer_order_rggb,
atomisp_bayer_order_bggr,
atomisp_bayer_order_gbrg
};
enum atomisp_input_stream_id {
ATOMISP_INPUT_STREAM_GENERAL = 0,
ATOMISP_INPUT_STREAM_CAPTURE = 0,
ATOMISP_INPUT_STREAM_POSTVIEW,
ATOMISP_INPUT_STREAM_PREVIEW,
ATOMISP_INPUT_STREAM_VIDEO,
ATOMISP_INPUT_STREAM_NUM
};
enum atomisp_input_format {
ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY,/* 8 bits per subpixel (legacy) */
ATOMISP_INPUT_FORMAT_YUV420_8, /* 8 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV420_10,/* 10 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV420_16,/* 16 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV422_8, /* UYVY..UVYV, 8 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV422_10,/* UYVY..UVYV, 10 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV422_16,/* UYVY..UVYV, 16 bits per subpixel */
ATOMISP_INPUT_FORMAT_RGB_444, /* BGR..BGR, 4 bits per subpixel */
ATOMISP_INPUT_FORMAT_RGB_555, /* BGR..BGR, 5 bits per subpixel */
ATOMISP_INPUT_FORMAT_RGB_565, /* BGR..BGR, 5 bits B and R, 6 bits G */
ATOMISP_INPUT_FORMAT_RGB_666, /* BGR..BGR, 6 bits per subpixel */
ATOMISP_INPUT_FORMAT_RGB_888, /* BGR..BGR, 8 bits per subpixel */
ATOMISP_INPUT_FORMAT_RAW_6, /* RAW data, 6 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_7, /* RAW data, 7 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_8, /* RAW data, 8 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_10, /* RAW data, 10 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_12, /* RAW data, 12 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_14, /* RAW data, 14 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_16, /* RAW data, 16 bits per pixel */
ATOMISP_INPUT_FORMAT_BINARY_8, /* Binary byte stream. */
/* CSI2-MIPI specific format: Generic short packet data. It is used to
* keep the timing information for the opening/closing of shutters,
* triggering of flashes and etc.
*/
ATOMISP_INPUT_FORMAT_GENERIC_SHORT1, /* Generic Short Packet Code 1 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT2, /* Generic Short Packet Code 2 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT3, /* Generic Short Packet Code 3 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT4, /* Generic Short Packet Code 4 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT5, /* Generic Short Packet Code 5 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT6, /* Generic Short Packet Code 6 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT7, /* Generic Short Packet Code 7 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT8, /* Generic Short Packet Code 8 */
/* CSI2-MIPI specific format: YUV data.
*/
ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT, /* YUV420 8-bit (Chroma Shifted
Pixel Sampling) */
ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT, /* YUV420 8-bit (Chroma Shifted
Pixel Sampling) */
/* CSI2-MIPI specific format: Generic long packet data
*/
ATOMISP_INPUT_FORMAT_EMBEDDED, /* Embedded 8-bit non Image Data */
/* CSI2-MIPI specific format: User defined byte-based data. For example,
* the data transmitter (e.g. the SoC sensor) can keep the JPEG data as
* the User Defined Data Type 4 and the MPEG data as the
* User Defined Data Type 7.
*/
ATOMISP_INPUT_FORMAT_USER_DEF1, /* User defined 8-bit data type 1 */
ATOMISP_INPUT_FORMAT_USER_DEF2, /* User defined 8-bit data type 2 */
ATOMISP_INPUT_FORMAT_USER_DEF3, /* User defined 8-bit data type 3 */
ATOMISP_INPUT_FORMAT_USER_DEF4, /* User defined 8-bit data type 4 */
ATOMISP_INPUT_FORMAT_USER_DEF5, /* User defined 8-bit data type 5 */
ATOMISP_INPUT_FORMAT_USER_DEF6, /* User defined 8-bit data type 6 */
ATOMISP_INPUT_FORMAT_USER_DEF7, /* User defined 8-bit data type 7 */
ATOMISP_INPUT_FORMAT_USER_DEF8, /* User defined 8-bit data type 8 */
};
enum intel_v4l2_subdev_type {
RAW_CAMERA = 1,
SOC_CAMERA = 2,
CAMERA_MOTOR = 3,
LED_FLASH = 4,
XENON_FLASH = 5,
FILE_INPUT = 6,
TEST_PATTERN = 7,
};
struct intel_v4l2_subdev_id {
char name[17];
enum intel_v4l2_subdev_type type;
enum atomisp_camera_port port;
};
struct intel_v4l2_subdev_i2c_board_info {
struct i2c_board_info board_info;
int i2c_adapter_id;
};
struct intel_v4l2_subdev_table {
struct intel_v4l2_subdev_i2c_board_info v4l2_subdev;
enum intel_v4l2_subdev_type type;
enum atomisp_camera_port port;
struct v4l2_subdev *subdev;
};
struct atomisp_platform_data {
struct intel_v4l2_subdev_table *subdevs;
};
/* Describe the capacities of one single sensor. */
struct atomisp_sensor_caps {
/* The number of streams this sensor can output. */
int stream_num;
bool is_slave;
};
/* Describe the capacities of sensors connected to one camera port. */
struct atomisp_camera_caps {
/* The number of sensors connected to this camera port. */
int sensor_num;
/* The capacities of each sensor. */
struct atomisp_sensor_caps sensor[MAX_SENSORS_PER_PORT];
/* Define whether stream control is required for multiple streams. */
bool multi_stream_ctrl;
};
/*
* Sensor of external ISP can send multiple steams with different mipi data
* type in the same virtual channel. This information needs to come from the
* sensor or external ISP
*/
struct atomisp_isys_config_info {
u8 input_format;
u16 width;
u16 height;
};
struct atomisp_input_stream_info {
enum atomisp_input_stream_id stream;
u8 enable;
/* Sensor driver fills ch_id with the id
of the virtual channel. */
u8 ch_id;
/* Tells how many streams in this virtual channel. If 0 ignore rest
* and the input format will be from mipi_info */
u8 isys_configs;
/*
* if more isys_configs is more than 0, sensor needs to configure the
* input format differently. width and height can be 0. If width and
* height is not zero, then the corresponsing data needs to be set
*/
struct atomisp_isys_config_info isys_info[MAX_STREAMS_PER_CHANNEL];
};
struct camera_vcm_control;
struct camera_vcm_ops {
int (*power_up)(struct v4l2_subdev *sd, struct camera_vcm_control *vcm);
int (*power_down)(struct v4l2_subdev *sd,
struct camera_vcm_control *vcm);
int (*queryctrl)(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc,
struct camera_vcm_control *vcm);
int (*g_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl,
struct camera_vcm_control *vcm);
int (*s_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl,
struct camera_vcm_control *vcm);
};
struct camera_vcm_control {
char camera_module[CAMERA_MODULE_ID_LEN];
struct camera_vcm_ops *ops;
struct list_head list;
};
struct camera_sensor_platform_data {
int (*gpio_ctrl)(struct v4l2_subdev *subdev, int flag);
int (*flisclk_ctrl)(struct v4l2_subdev *subdev, int flag);
int (*power_ctrl)(struct v4l2_subdev *subdev, int flag);
int (*csi_cfg)(struct v4l2_subdev *subdev, int flag);
bool (*low_fps)(void);
int (*platform_init)(struct i2c_client *);
int (*platform_deinit)(void);
char *(*msr_file_name)(void);
struct atomisp_camera_caps *(*get_camera_caps)(void);
int (*gpio_intr_ctrl)(struct v4l2_subdev *subdev);
/* New G-Min power and GPIO interface, replaces
* power/gpio_ctrl with methods to control individual
* lines as implemented on all known camera modules. */
int (*gpio0_ctrl)(struct v4l2_subdev *subdev, int on);
int (*gpio1_ctrl)(struct v4l2_subdev *subdev, int on);
int (*v1p8_ctrl)(struct v4l2_subdev *subdev, int on);
int (*v2p8_ctrl)(struct v4l2_subdev *subdev, int on);
int (*v1p2_ctrl)(struct v4l2_subdev *subdev, int on);
struct camera_vcm_control * (*get_vcm_ctrl)(struct v4l2_subdev *subdev,
char *module_id);
};
struct camera_af_platform_data {
int (*power_ctrl)(struct v4l2_subdev *subdev, int flag);
};
const struct camera_af_platform_data *camera_get_af_platform_data(void);
struct camera_mipi_info {
enum atomisp_camera_port port;
unsigned int num_lanes;
enum atomisp_input_format input_format;
enum atomisp_bayer_order raw_bayer_order;
struct atomisp_sensor_mode_data data;
enum atomisp_input_format metadata_format;
uint32_t metadata_width;
uint32_t metadata_height;
const uint32_t *metadata_effective_width;
};
extern const struct atomisp_platform_data *atomisp_get_platform_data(void);
extern const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void);
/* API from old platform_camera.h, new CPUID implementation */
#define __IS_SOC(x) (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && \
boot_cpu_data.x86 == 6 && \
boot_cpu_data.x86_model == x)
#define IS_MFLD __IS_SOC(0x27)
#define IS_BYT __IS_SOC(0x37)
#define IS_CHT __IS_SOC(0x4C)
#define IS_MOFD __IS_SOC(0x5A)
#endif /* ATOMISP_PLATFORM_H_ */

233
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/*
* intel_mid_pm.h
* Copyright (c) 2010, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/errno.h>
#ifndef INTEL_MID_PM_H
#define INTEL_MID_PM_H
#include <asm/intel-mid.h>
#include <linux/init.h>
#include <linux/pci.h>
/* Chip ID of Intel Atom SOC*/
#define INTEL_ATOM_MRST 0x26
#define INTEL_ATOM_MFLD 0x27
#define INTEL_ATOM_CLV 0x35
#define INTEL_ATOM_MRFLD 0x4a
#define INTEL_ATOM_BYT 0x37
#define INTEL_ATOM_MOORFLD 0x5a
#define INTEL_ATOM_CHT 0x4c
static inline int platform_is(u8 model)
{
return boot_cpu_data.x86_model == model;
}
/* Register Type definitions */
#define OSPM_REG_TYPE 0x0
#define APM_REG_TYPE 0x1
#define OSPM_MAX_POWER_ISLANDS 16
#define OSPM_ISLAND_UP 0x0
#define OSPM_ISLAND_DOWN 0x1
/*Soft reset*/
#define OSPM_ISLAND_SR 0x2
/* North complex power islands definitions for APM block*/
#define APM_GRAPHICS_ISLAND 0x1
#define APM_VIDEO_DEC_ISLAND 0x2
#define APM_VIDEO_ENC_ISLAND 0x4
#define APM_GL3_CACHE_ISLAND 0x8
#define APM_ISP_ISLAND 0x10
#define APM_IPH_ISLAND 0x20
/* North complex power islands definitions for OSPM block*/
#define OSPM_DISPLAY_A_ISLAND 0x2
#define OSPM_DISPLAY_B_ISLAND 0x80
#define OSPM_DISPLAY_C_ISLAND 0x100
#define OSPM_MIPI_ISLAND 0x200
/* North Complex power islands definitions for Tangier */
#define TNG_ISP_ISLAND 0x1
/* North Complex Register definitions for Tangier */
#define ISP_SS_PM0 0x39
#define C4_STATE_IDX 3
#define C6_STATE_IDX 4
#define S0I1_STATE_IDX 5
#define LPMP3_STATE_IDX 6
#define S0I3_STATE_IDX 7
#define C4_HINT (0x30)
#define C6_HINT (0x52)
#define CSTATE_EXIT_LATENCY_C1 1
#define CSTATE_EXIT_LATENCY_C2 20
#define CSTATE_EXIT_LATENCY_C4 100
#define CSTATE_EXIT_LATENCY_C6 140
#define CSTATE_EXIT_LATENCY_C7 1200
/* Since entry latency is substantial
* put exit_latency = entry+exit latency
*/
#ifdef CONFIG_REMOVEME_INTEL_ATOM_MRFLD_POWER
#define CSTATE_EXIT_LATENCY_S0i1 1200
#define CSTATE_EXIT_LATENCY_S0i2 2000
#define CSTATE_EXIT_LATENCY_S0i3 10000
#else
#define CSTATE_EXIT_LATENCY_LPMP3 1040
#define CSTATE_EXIT_LATENCY_S0i1 1040
#define CSTATE_EXIT_LATENCY_S0i3 2800
#endif
#define BYT_S0I1_STATE 0x60
#define BYT_S0I2_STATE 0x62
#define BYT_LPMP3_STATE 0x62
#define BYT_S0I3_STATE 0x64
enum s3_parts {
PROC_FRZ,
DEV_SUS,
NB_CPU_OFF,
NB_CPU_ON,
DEV_RES,
PROC_UNFRZ,
MAX_S3_PARTS
};
#ifdef CONFIG_ATOM_SOC_POWER
#define LOG_PMU_EVENTS
/* Error codes for pmu */
#define PMU_SUCCESS 0
#define PMU_FAILED -1
#define PMU_BUSY_STATUS 0
#define PMU_MODE_ID 1
#define SET_MODE 1
#define SET_AOAC_S0i1 2
#define SET_AOAC_S0i3 3
#define SET_LPAUDIO 4
#define SET_AOAC_S0i2 7
#ifdef CONFIG_REMOVEME_INTEL_ATOM_MRFLD_POWER
#define MID_S0I1_STATE 0x60
#define MID_S0I2_STATE 0x62
#define MID_LPMP3_STATE 0x62
#define MID_S0I3_STATE 0x64
#else
#define MID_S0I1_STATE 0x1
#define MID_LPMP3_STATE 0x3
#define MID_S0I2_STATE 0x7
#define MID_S0I3_STATE 0x7
#endif
#define MID_S0IX_STATE 0xf
#define MID_S3_STATE 0x1f
#define MID_FAST_ON_OFF_STATE 0x3f
/* combinations */
#define MID_LPI1_STATE 0x1f
#define MID_LPI3_STATE 0x7f
#define MID_I1I3_STATE 0xff
#define REMOVE_LP_FROM_LPIX 4
/* Power number for MID_POWER */
#define C0_POWER_USAGE 450
#define C6_POWER_USAGE 200
#define LPMP3_POWER_USAGE 130
#define S0I1_POWER_USAGE 50
#define S0I3_POWER_USAGE 31
extern unsigned int enable_s3;
extern unsigned int enable_s0ix;
extern void pmu_s0ix_demotion_stat(int req_state, int grant_state);
extern unsigned int pmu_get_new_cstate(unsigned int cstate, int *index);
extern int get_target_platform_state(unsigned long *eax);
extern int mid_s0ix_enter(int);
extern int pmu_set_devices_in_d0i0(void);
extern int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
extern pci_power_t pmu_pci_choose_state(struct pci_dev *pdev);
extern void time_stamp_in_suspend_flow(int mark, bool start);
extern void time_stamp_for_sleep_state_latency(int sleep_state,
bool start, bool entry);
extern int mid_state_to_sys_state(int mid_state);
extern void pmu_power_off(void);
extern void pmu_set_s0ix_complete(void);
extern bool pmu_is_s0ix_in_progress(void);
extern int pmu_nc_set_power_state
(int islands, int state_type, int reg_type);
extern int pmu_nc_get_power_state(int island, int reg_type);
extern int pmu_set_emmc_to_d0i0_atomic(void);
#ifdef LOG_PMU_EVENTS
extern void pmu_log_ipc(u32 command);
extern void pmu_log_ipc_irq(void);
#else
static inline void pmu_log_ipc(u32 command) { return; };
static inline void pmu_log_ipc_irq(void) { return; };
#endif
extern void dump_nc_power_history(void);
extern bool mid_pmu_is_wake_source(u32 lss_number);
extern void (*nc_report_power_state) (u32, int);
#else
/*
* If CONFIG_ATOM_SOC_POWER is not defined
* fall back to C6
*/
#define MID_S0I1_STATE C6_HINT
#define MID_LPMP3_STATE C6_HINT
#define MID_S0I3_STATE C6_HINT
#define MID_S3_STATE C6_HINT
#define MID_FAST_ON_OFF_STATE C6_HINT
/* Power usage unknown if MID_POWER not defined */
#define C0_POWER_USAGE 0
#define C6_POWER_USAGE 0
#define LPMP3_POWER_USAGE 0
#define S0I1_POWER_USAGE 0
#define S0I3_POWER_USAGE 0
#define TEMP_DTS_ID 43
static inline int pmu_nc_set_power_state
(int islands, int state_type, int reg_type) { return 0; }
static inline int pmu_nc_get_power_state(int island, int reg_type) { return 0; }
static inline void pmu_set_s0ix_complete(void) { return; }
static inline bool pmu_is_s0ix_in_progress(void) { return false; };
static inline unsigned int pmu_get_new_cstate
(unsigned int cstate, int *index) { return cstate; };
/*returns function not implemented*/
static inline void time_stamp_in_suspend_flow(int mark, bool start) {}
static inline void time_stamp_for_sleep_state_latency(int sleep_state,
bool start, bool entry) {}
static inline int mid_state_to_sys_state(int mid_state) { return 0; }
static inline int pmu_set_devices_in_d0i0(void) { return 0; }
static inline void pmu_log_ipc(u32 command) { return; };
static inline void pmu_log_ipc_irq(void) { return; };
static inline int pmu_set_emmc_to_d0i0_atomic(void) { return -ENOSYS; }
static inline void pmu_power_off(void) { return; }
static inline bool mid_pmu_is_wake_source(u32 lss_number) { return false; }
#endif /* #ifdef CONFIG_ATOM_SOC_POWER */
#endif /* #ifndef INTEL_MID_PM_H */

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/*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __LIBMSRLISTHELPER_H__
#define __LIBMSRLISTHELPER_H__
struct i2c_client;
struct firmware;
extern int load_msr_list(struct i2c_client *client, char *path,
const struct firmware **fw);
extern int apply_msr_data(struct i2c_client *client, const struct firmware *fw);
extern void release_msr_list(struct i2c_client *client,
const struct firmware *fw);
#endif /* ifndef __LIBMSRLISTHELPER_H__ */

30
drivers/staging/media/atomisp/include/linux/vlv2_plat_clock.h Normal file
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/*
* vlv2_plat_clock.h
*
* Copyright (C) 2013 Intel Corp
* Author: Asutosh Pathak <asutosh.pathak@intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*/
#ifndef __VLV2_PLAT_CLOCK_H
#define __VLV2_PLAT_CLOCK_H
int vlv2_plat_set_clock_freq(int clock_num, int freq_type);
int vlv2_plat_get_clock_freq(int clock_num);
int vlv2_plat_configure_clock(int clock_num, u32 conf);
int vlv2_plat_get_clock_status(int clock_num);
#endif /* __VLV2_PLAT_CLOCK_H */

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drivers/staging/media/atomisp/include/media/lm3554.h Normal file
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/*
* include/media/lm3554.h
*
* Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef _LM3554_H_
#define _LM3554_H_
#include <linux/videodev2.h>
#include <media/v4l2-subdev.h>
#define LM3554_NAME "lm3554"
#define LM3554_ID 3554
#define v4l2_queryctrl_entry_integer(_id, _name,\
_minimum, _maximum, _step, \
_default_value, _flags) \
{\
.id = (_id), \
.type = V4L2_CTRL_TYPE_INTEGER, \
.name = _name, \
.minimum = (_minimum), \
.maximum = (_maximum), \
.step = (_step), \
.default_value = (_default_value),\
.flags = (_flags),\
}
#define v4l2_queryctrl_entry_boolean(_id, _name,\
_default_value, _flags) \
{\
.id = (_id), \
.type = V4L2_CTRL_TYPE_BOOLEAN, \
.name = _name, \
.minimum = 0, \
.maximum = 1, \
.step = 1, \
.default_value = (_default_value),\
.flags = (_flags),\
}
#define s_ctrl_id_entry_integer(_id, _name, \
_minimum, _maximum, _step, \
_default_value, _flags, \
_s_ctrl, _g_ctrl) \
{\
.qc = v4l2_queryctrl_entry_integer(_id, _name,\
_minimum, _maximum, _step,\
_default_value, _flags), \
.s_ctrl = _s_ctrl, \
.g_ctrl = _g_ctrl, \
}
#define s_ctrl_id_entry_boolean(_id, _name, \
_default_value, _flags, \
_s_ctrl, _g_ctrl) \
{\
.qc = v4l2_queryctrl_entry_boolean(_id, _name,\
_default_value, _flags), \
.s_ctrl = _s_ctrl, \
.g_ctrl = _g_ctrl, \
}
/* Value settings for Flash Time-out Duration*/
#define LM3554_DEFAULT_TIMEOUT 512U
#define LM3554_MIN_TIMEOUT 32U
#define LM3554_MAX_TIMEOUT 1024U
#define LM3554_TIMEOUT_STEPSIZE 32U
/* Flash modes */
#define LM3554_MODE_SHUTDOWN 0
#define LM3554_MODE_INDICATOR 1
#define LM3554_MODE_TORCH 2
#define LM3554_MODE_FLASH 3
/* timer delay time */
#define LM3554_TIMER_DELAY 5
/* Percentage <-> value macros */
#define LM3554_MIN_PERCENT 0U
#define LM3554_MAX_PERCENT 100U
#define LM3554_CLAMP_PERCENTAGE(val) \
clamp(val, LM3554_MIN_PERCENT, LM3554_MAX_PERCENT)
#define LM3554_VALUE_TO_PERCENT(v, step) (((((unsigned long)(v))*(step))+50)/100)
#define LM3554_PERCENT_TO_VALUE(p, step) (((((unsigned long)(p))*100)+(step>>1))/(step))
/* Product specific limits
* TODO: get these from platform data */
#define LM3554_FLASH_MAX_LVL 0x0F /* 1191mA */
/* Flash brightness, input is percentage, output is [0..15] */
#define LM3554_FLASH_STEP \
((100ul*(LM3554_MAX_PERCENT)+((LM3554_FLASH_MAX_LVL)>>1))/((LM3554_FLASH_MAX_LVL)))
#define LM3554_FLASH_DEFAULT_BRIGHTNESS \
LM3554_VALUE_TO_PERCENT(13, LM3554_FLASH_STEP)
/* Torch brightness, input is percentage, output is [0..7] */
#define LM3554_TORCH_STEP 1250
#define LM3554_TORCH_DEFAULT_BRIGHTNESS \
LM3554_VALUE_TO_PERCENT(2, LM3554_TORCH_STEP)
/* Indicator brightness, input is percentage, output is [0..3] */
#define LM3554_INDICATOR_STEP 2500
#define LM3554_INDICATOR_DEFAULT_BRIGHTNESS \
LM3554_VALUE_TO_PERCENT(1, LM3554_INDICATOR_STEP)
/*
* lm3554_platform_data - Flash controller platform data
*/
struct lm3554_platform_data {
int gpio_torch;
int gpio_strobe;
int gpio_reset;
unsigned int current_limit;
unsigned int envm_tx2;
unsigned int tx2_polarity;
};
#endif /* _LM3554_H_ */

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drivers/staging/media/atomisp/include/media/lm3642.h Normal file
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/*
* include/media/lm3642.h
*
* Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program.
*/
#ifndef _LM3642_H_
#define _LM3642_H_
#include <linux/videodev2.h>
#include <media/v4l2-subdev.h>
#define LM3642_NAME "lm3642"
#define LM3642_ID 3642
#define v4l2_queryctrl_entry_integer(_id, _name,\
_minimum, _maximum, _step, \
_default_value, _flags) \
{\
.id = (_id), \
.type = V4L2_CTRL_TYPE_INTEGER, \
.name = _name, \
.minimum = (_minimum), \
.maximum = (_maximum), \
.step = (_step), \
.default_value = (_default_value),\
.flags = (_flags),\
}
#define v4l2_queryctrl_entry_boolean(_id, _name,\
_default_value, _flags) \
{\
.id = (_id), \
.type = V4L2_CTRL_TYPE_BOOLEAN, \
.name = _name, \
.minimum = 0, \
.maximum = 1, \
.step = 1, \
.default_value = (_default_value),\
.flags = (_flags),\
}
#define s_ctrl_id_entry_integer(_id, _name, \
_minimum, _maximum, _step, \
_default_value, _flags, \
_s_ctrl, _g_ctrl) \
{\
.qc = v4l2_queryctrl_entry_integer(_id, _name,\
_minimum, _maximum, _step,\
_default_value, _flags), \
.s_ctrl = _s_ctrl, \
.g_ctrl = _g_ctrl, \
}
#define s_ctrl_id_entry_boolean(_id, _name, \
_default_value, _flags, \
_s_ctrl, _g_ctrl) \
{\
.qc = v4l2_queryctrl_entry_boolean(_id, _name,\
_default_value, _flags), \
.s_ctrl = _s_ctrl, \
.g_ctrl = _g_ctrl, \
}
/* Default Values */
#define LM3642_DEFAULT_TIMEOUT 300U
#define LM3642_DEFAULT_RAMP_TIME 0x10 /* 1.024ms */
#define LM3642_DEFAULT_INDICATOR_CURRENT 0x01 /* 1.88A */
#define LM3642_DEFAULT_FLASH_CURRENT 0x0f /* 1500mA */
/* Value settings for Flash Time-out Duration*/
#define LM3642_MIN_TIMEOUT 100U
#define LM3642_MAX_TIMEOUT 800U
#define LM3642_TIMEOUT_STEPSIZE 100U
/* Flash modes */
#define LM3642_MODE_SHUTDOWN 0
#define LM3642_MODE_INDICATOR 1
#define LM3642_MODE_TORCH 2
#define LM3642_MODE_FLASH 3
/* timer delay time */
#define LM3642_TIMER_DELAY 5
/* Percentage <-> value macros */
#define LM3642_MIN_PERCENT 0U
#define LM3642_MAX_PERCENT 100U
#define LM3642_CLAMP_PERCENTAGE(val) \
clamp(val, LM3642_MIN_PERCENT, LM3642_MAX_PERCENT)
#define LM3642_VALUE_TO_PERCENT(v, step) \
(((((unsigned long)((v)+1))*(step))+50)/100)
#define LM3642_PERCENT_TO_VALUE(p, step) \
(((((unsigned long)(p))*100)+((step)>>1))/(step)-1)
/* Product specific limits
* TODO: get these from platform data */
#define LM3642_FLASH_MAX_LVL 0x0F /* 1500mA */
#define LM3642_TORCH_MAX_LVL 0x07 /* 187mA */
#define LM3642_INDICATOR_MAX_LVL 0x01 /* 1.88A */
/* Flash brightness, input is percentage, output is [0..15] */
#define LM3642_FLASH_STEP \
((100ul*(LM3642_MAX_PERCENT) \
+((LM3642_FLASH_MAX_LVL+1)>>1)) \
/((LM3642_FLASH_MAX_LVL+1)))
#define LM3642_FLASH_DEFAULT_BRIGHTNESS \
LM3642_VALUE_TO_PERCENT(15, LM3642_FLASH_STEP)
/* Torch brightness, input is percentage, output is [0..7] */
#define LM3642_TORCH_STEP \
((100ul*(LM3642_MAX_PERCENT) \
+((LM3642_TORCH_MAX_LVL+1)>>1)) \
/((LM3642_TORCH_MAX_LVL+1)))
#define LM3642_TORCH_DEFAULT_BRIGHTNESS \
LM3642_VALUE_TO_PERCENT(0, LM3642_TORCH_STEP)
/* Indicator brightness, input is percentage, output is [0..1] */
#define LM3642_INDICATOR_STEP \
((100ul*(LM3642_MAX_PERCENT) \
+((LM3642_INDICATOR_MAX_LVL+1)>>1)) \
/((LM3642_INDICATOR_MAX_LVL+1)))
#define LM3642_INDICATOR_DEFAULT_BRIGHTNESS \
LM3642_VALUE_TO_PERCENT(1, LM3642_INDICATOR_STEP)
/*
* lm3642_platform_data - Flash controller platform data
*/
struct lm3642_platform_data {
int gpio_torch;
int gpio_strobe;
int (*power_ctrl)(struct v4l2_subdev *subdev, int on);
unsigned int torch_en;
unsigned int flash_en;
unsigned int tx_en;
unsigned int ivfm_en;
};
#endif /* _LM3642_H_ */

13
drivers/staging/media/atomisp/pci/Kconfig Normal file
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#
# Kconfig for ISP driver
#
config VIDEO_ATOMISP
tristate "Intel Atom Image Signal Processor Driver"
depends on VIDEO_V4L2
select VIDEOBUF_VMALLOC
---help---
Say Y here if your platform supports Intel Atom SoC
camera imaging subsystem.
To compile this driver as a module, choose M here: the
module will be called atomisp

5
drivers/staging/media/atomisp/pci/Makefile Normal file
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#
# Makefile for ISP driver
#
obj-$(CONFIG_VIDEO_ATOMISP) += atomisp2/

380
drivers/staging/media/atomisp/pci/atomisp2/Makefile Normal file
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atomisp-objs += \
./atomisp_drvfs.o \
./atomisp_file.o \
./css2400/sh_css_mipi.o \
./css2400/runtime/pipeline/src/pipeline.o \
./css2400/runtime/spctrl/src/spctrl.o \
./css2400/runtime/rmgr/src/rmgr.o \
./css2400/runtime/rmgr/src/rmgr_vbuf.o \
./css2400/runtime/isp_param/src/isp_param.o \
./css2400/runtime/inputfifo/src/inputfifo.o \
./css2400/runtime/queue/src/queue_access.o \
./css2400/runtime/queue/src/queue.o \
./css2400/runtime/frame/src/frame.o \
./css2400/runtime/eventq/src/eventq.o \
./css2400/runtime/binary/src/binary.o \
./css2400/runtime/timer/src/timer.o \
./css2400/runtime/isys/src/csi_rx_rmgr.o \
./css2400/runtime/isys/src/isys_stream2mmio_rmgr.o \
./css2400/runtime/isys/src/virtual_isys.o \
./css2400/runtime/isys/src/rx.o \
./css2400/runtime/isys/src/isys_dma_rmgr.o \
./css2400/runtime/isys/src/ibuf_ctrl_rmgr.o \
./css2400/runtime/isys/src/isys_init.o \
./css2400/runtime/bufq/src/bufq.o \
./css2400/runtime/ifmtr/src/ifmtr.o \
./css2400/runtime/debug/src/ia_css_debug.o \
./css2400/runtime/event/src/event.o \
./css2400/sh_css_sp.o \
./css2400/css_2400_system/spmem_dump.o \
./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.o \
./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.o \
./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.o \
./css2400/sh_css_stream_format.o \
./css2400/sh_css_hrt.o \
./css2400/sh_css_properties.o \
./css2400/memory_realloc.o \
./css2400/hive_isp_css_shared/host/tag.o \
./css2400/sh_css_params.o \
./css2400/sh_css.o \
./css2400/isp/kernels/hdr/ia_css_hdr.host.o \
./css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.o \
./css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.o \
./css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.o \
./css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.o \
./css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.o \
./css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.o \
./css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.o \
./css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.o \
./css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.o \
./css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.o \
./css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.o \
./css2400/isp/kernels/output/output_1.0/ia_css_output.host.o \
./css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.o \
./css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.o \
./css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.o \
./css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.o \
./css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.o \
./css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.o \
./css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.o \
./css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.o \
./css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.o \
./css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.o \
./css2400/isp/kernels/dpc2/ia_css_dpc2.host.o \
./css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.o \
./css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.o \
./css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.o \
./css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.o \
./css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.o \
./css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.o \
./css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.o \
./css2400/isp/kernels/bh/bh_2/ia_css_bh.host.o \
./css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.o \
./css2400/isp/kernels/bnlm/ia_css_bnlm.host.o \
./css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.o \
./css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.o \
./css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.o \
./css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.o \
./css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.o \
./css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.o \
./css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.o \
./css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.o \
./css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.o \
./css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.o \
./css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.o \
./css2400/isp/kernels/satm/ia_css_satm.host.o \
./css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.o \
./css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.o \
./css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.o \
./css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.o \
./css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.o \
./css2400/isp/kernels/de/de_1.0/ia_css_de.host.o \
./css2400/isp/kernels/de/de_2/ia_css_de2.host.o \
./css2400/isp/kernels/gc/gc_2/ia_css_gc2.host.o \
./css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.o \
./css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.o \
./css2400/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.o \
./css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.o \
./css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.o \
./css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.o \
./css2400/isp/kernels/pdaf/ia_css_pdaf.host.o \
./css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.o \
./css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.o \
./css2400/isp/kernels/ob/ob2/ia_css_ob2.host.o \
./css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.o \
./css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.o \
./css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.o \
./css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.o \
./css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.o \
./css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.o \
./css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.o \
./css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.o \
./css2400/sh_css_lace_stat.o \
./css2400/sh_css_pipe.o \
./css2400/ia_css_device_access.o \
./css2400/sh_css_host_data.o \
./css2400/sh_css_mmu.o \
./css2400/sh_css_metadata.o \
./css2400/base/refcount/src/refcount.o \
./css2400/base/circbuf/src/circbuf.o \
./css2400/sh_css_irq.o \
./css2400/camera/pipe/src/pipe_binarydesc.o \
./css2400/camera/pipe/src/pipe_util.o \
./css2400/camera/pipe/src/pipe_stagedesc.o \
./css2400/camera/util/src/util.o \
./css2400/sh_css_metrics.o \
./css2400/sh_css_version.o \
./css2400/ia_css_memory_access.o \
./css2400/sh_css_param_shading.o \
./css2400/sh_css_morph.o \
./css2400/sh_css_firmware.o \
./css2400/hive_isp_css_common/host/isp.o \
./css2400/hive_isp_css_common/host/gdc.o \
./css2400/hive_isp_css_common/host/sp.o \
./css2400/hive_isp_css_common/host/vmem.o \
./css2400/hive_isp_css_common/host/dma.o \
./css2400/hive_isp_css_common/host/input_formatter.o \
./css2400/hive_isp_css_common/host/debug.o \
./css2400/hive_isp_css_common/host/hmem.o \
./css2400/hive_isp_css_common/host/gp_device.o \
./css2400/hive_isp_css_common/host/fifo_monitor.o \
./css2400/hive_isp_css_common/host/gp_timer.o \
./css2400/hive_isp_css_common/host/irq.o \
./css2400/hive_isp_css_common/host/input_system.o \
./css2400/hive_isp_css_common/host/timed_ctrl.o \
./css2400/hive_isp_css_common/host/mmu.o \
./css2400/hive_isp_css_common/host/event_fifo.o \
./css2400/sh_css_param_dvs.o \
./css2400/sh_css_shading.o \
./css2400/sh_css_stream.o \
./mmu/sh_mmu_mrfld.o \
./mmu/isp_mmu.o \
./atomisp_acc.o \
./atomisp_compat_css20.o \
./atomisp_fops.o \
./atomisp_subdev.o \
./atomisp_ioctl.o \
./atomisp_compat_ioctl32.o \
./atomisp_csi2.o \
./atomisp_cmd.o \
./atomisp_tpg.o \
./hmm/hmm_vm.o \
./hmm/hmm.o \
./hmm/hmm_bo.o \
./hmm/hmm_reserved_pool.o \
./hmm/hmm_dynamic_pool.o \
./hrt/hive_isp_css_mm_hrt.o \
./atomisp_v4l2.o
extra= \
./hrt/hive_isp_css_mm_hrt.o \
./hrt/memory_access.o \
./hrt/device_access.o \
./hmm/hmm_dynamic_pool.o \
./hmm/hmm_vm.o \
./hmm/hmm_reserved_pool.o \
./hmm/hmm_bo_dev.o \
./hmm/hmm.o \
./hmm/hmm_bo.o
# These will be needed when clean merge CHT support nicely into the driver
# Keep them here handy for when we get to that point
#
obj-cht= \
./css2400/css_2401_system/spmem_dump.o \
./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.o \
./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.o \
./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.o \
./css2400/css_2401_csi2p_system/spmem_dump.o \
./css2400/css_2401_csi2p_system/host/isys_stream2mmio.o \
./css2400/css_2401_csi2p_system/host/ibuf_ctrl.o \
./css2400/css_2401_csi2p_system/host/isys_irq.o \
./css2400/css_2401_csi2p_system/host/isys_dma.o \
./css2400/css_2401_csi2p_system/host/csi_rx.o \
./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.o \
./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.o \
./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.o \
# -I$(atomisp)/css2400/css_2401_csi2p_system/ \
# -I$(atomisp)/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ \
# -I$(atomisp)/css2400/css_2401_csi2p_system/host/ \
# -I$(atomisp)/css2400/css_2401_csi2p_system/hrt/ \
# -I$(atomisp)/css2400/css_2401_system/hive_isp_css_2401_system_generated/ \
# -I$(atomisp)/css2400/css_2401_system/hrt/ \
obj-$(CONFIG_VIDEO_ATOMISP) += atomisp.o
atomisp = $(srctree)/drivers/staging/media/atomisp/pci/atomisp2
INCLUDES += \
-I$(atomisp)/ \
-I$(atomisp)/css2400/ \
-I$(atomisp)/hrt/ \
-I$(atomisp)/include/ \
-I$(atomisp)/include/hmm/ \
-I$(atomisp)/include/mmu/ \
-I$(atomisp)/css2400/base/circbuf/interface/ \
-I$(atomisp)/css2400/base/refcount/interface/ \
-I$(atomisp)/css2400/camera/pipe/interface/ \
-I$(atomisp)/css2400/camera/util/interface/ \
-I$(atomisp)/css2400/css_2400_system/ \
-I$(atomisp)/css2400/css_2400_system/hive_isp_css_2400_system_generated/ \
-I$(atomisp)/css2400/css_2400_system/hrt/ \
-I$(atomisp)/css2400/hive_isp_css_common/ \
-I$(atomisp)/css2400/hive_isp_css_common/host/ \
-I$(atomisp)/css2400/hive_isp_css_include/ \
-I$(atomisp)/css2400/hive_isp_css_include/device_access/ \
-I$(atomisp)/css2400/hive_isp_css_include/host/ \
-I$(atomisp)/css2400/hive_isp_css_include/memory_access/ \
-I$(atomisp)/css2400/hive_isp_css_shared/ \
-I$(atomisp)/css2400/hive_isp_css_shared/host/ \
-I$(atomisp)/css2400/isp/kernels/ \
-I$(atomisp)/css2400/isp/kernels/aa/aa_2/ \
-I$(atomisp)/css2400/isp/kernels/anr/anr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/anr/anr_2/ \
-I$(atomisp)/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ \
-I$(atomisp)/css2400/isp/kernels/bh/bh_2/ \
-I$(atomisp)/css2400/isp/kernels/bnlm/ \
-I$(atomisp)/css2400/isp/kernels/bnr/ \
-I$(atomisp)/css2400/isp/kernels/bnr/bnr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/bnr/bnr2_2/ \
-I$(atomisp)/css2400/isp/kernels/cnr/ \
-I$(atomisp)/css2400/isp/kernels/cnr/cnr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/cnr/cnr_2/ \
-I$(atomisp)/css2400/isp/kernels/conversion/ \
-I$(atomisp)/css2400/isp/kernels/conversion/conversion_1.0/ \
-I$(atomisp)/css2400/isp/kernels/copy_output/ \
-I$(atomisp)/css2400/isp/kernels/copy_output/copy_output_1.0/ \
-I$(atomisp)/css2400/isp/kernels/crop/ \
-I$(atomisp)/css2400/isp/kernels/crop/crop_1.0/ \
-I$(atomisp)/css2400/isp/kernels/csc/ \
-I$(atomisp)/css2400/isp/kernels/csc/csc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ctc/ \
-I$(atomisp)/css2400/isp/kernels/ctc/ctc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ctc/ctc1_5/ \
-I$(atomisp)/css2400/isp/kernels/ctc/ctc2/ \
-I$(atomisp)/css2400/isp/kernels/de/ \
-I$(atomisp)/css2400/isp/kernels/de/de_1.0/ \
-I$(atomisp)/css2400/isp/kernels/de/de_2/ \
-I$(atomisp)/css2400/isp/kernels/dpc2/ \
-I$(atomisp)/css2400/isp/kernels/dp/ \
-I$(atomisp)/css2400/isp/kernels/dp/dp_1.0/ \
-I$(atomisp)/css2400/isp/kernels/dvs/ \
-I$(atomisp)/css2400/isp/kernels/dvs/dvs_1.0/ \
-I$(atomisp)/css2400/isp/kernels/eed1_8/ \
-I$(atomisp)/css2400/isp/kernels/fc/ \
-I$(atomisp)/css2400/isp/kernels/fc/fc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/fixedbds/ \
-I$(atomisp)/css2400/isp/kernels/fixedbds/fixedbds_1.0/ \
-I$(atomisp)/css2400/isp/kernels/fpn/ \
-I$(atomisp)/css2400/isp/kernels/fpn/fpn_1.0/ \
-I$(atomisp)/css2400/isp/kernels/gc/ \
-I$(atomisp)/css2400/isp/kernels/gc/gc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/gc/gc_2/ \
-I$(atomisp)/css2400/isp/kernels/hdr/ \
-I$(atomisp)/css2400/isp/kernels/iefd2_6/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/bayer_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/common/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/plane_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/yuv420_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/yuv444_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/common/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/plane_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/yuv420_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/iterator/ \
-I$(atomisp)/css2400/isp/kernels/iterator/iterator_1.0/ \
-I$(atomisp)/css2400/isp/kernels/macc/ \
-I$(atomisp)/css2400/isp/kernels/macc/macc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/macc/macc1_5/ \
-I$(atomisp)/css2400/isp/kernels/norm/ \
-I$(atomisp)/css2400/isp/kernels/norm/norm_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ob/ \
-I$(atomisp)/css2400/isp/kernels/ob/ob_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ob/ob2/ \
-I$(atomisp)/css2400/isp/kernels/output/ \
-I$(atomisp)/css2400/isp/kernels/output/output_1.0/ \
-I$(atomisp)/css2400/isp/kernels/pdaf/ \
-I$(atomisp)/css2400/isp/kernels/qplane/ \
-I$(atomisp)/css2400/isp/kernels/qplane/qplane_2/ \
-I$(atomisp)/css2400/isp/kernels/raw_aa_binning/ \
-I$(atomisp)/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ \
-I$(atomisp)/css2400/isp/kernels/raw/ \
-I$(atomisp)/css2400/isp/kernels/raw/raw_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ref/ \
-I$(atomisp)/css2400/isp/kernels/ref/ref_1.0/ \
-I$(atomisp)/css2400/isp/kernels/s3a/ \
-I$(atomisp)/css2400/isp/kernels/s3a/s3a_1.0/ \
-I$(atomisp)/css2400/isp/kernels/s3a_stat_ls/ \
-I$(atomisp)/css2400/isp/kernels/satm/ \
-I$(atomisp)/css2400/isp/kernels/scale/ \
-I$(atomisp)/css2400/isp/kernels/scale/scale_1.0/ \
-I$(atomisp)/css2400/isp/kernels/sc/ \
-I$(atomisp)/css2400/isp/kernels/sc/sc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/sdis/ \
-I$(atomisp)/css2400/isp/kernels/sdis/common/ \
-I$(atomisp)/css2400/isp/kernels/sdis/sdis_1.0/ \
-I$(atomisp)/css2400/isp/kernels/sdis/sdis_2/ \
-I$(atomisp)/css2400/isp/kernels/tdf/ \
-I$(atomisp)/css2400/isp/kernels/tdf/tdf_1.0/ \
-I$(atomisp)/css2400/isp/kernels/tnr/ \
-I$(atomisp)/css2400/isp/kernels/tnr/tnr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/tnr/tnr3/ \
-I$(atomisp)/css2400/isp/kernels/uds/ \
-I$(atomisp)/css2400/isp/kernels/uds/uds_1.0/ \
-I$(atomisp)/css2400/isp/kernels/vf/ \
-I$(atomisp)/css2400/isp/kernels/vf/vf_1.0/ \
-I$(atomisp)/css2400/isp/kernels/wb/ \
-I$(atomisp)/css2400/isp/kernels/wb/wb_1.0/ \
-I$(atomisp)/css2400/isp/kernels/xnr/ \
-I$(atomisp)/css2400/isp/kernels/xnr/xnr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/xnr/xnr_3.0/ \
-I$(atomisp)/css2400/isp/kernels/xnr/xnr3_0_11 \
-I$(atomisp)/css2400/isp/kernels/xnr/xnr3_0_5/ \
-I$(atomisp)/css2400/isp/kernels/ynr/ \
-I$(atomisp)/css2400/isp/kernels/ynr/ynr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ynr/ynr_2/ \
-I$(atomisp)/css2400/isp/kernels/yuv_ls \
-I$(atomisp)/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ \
-I$(atomisp)/css2400/isp/modes/interface/ \
-I$(atomisp)/css2400/runtime/binary/interface/ \
-I$(atomisp)/css2400/runtime/bufq/interface/ \
-I$(atomisp)/css2400/runtime/debug/interface/ \
-I$(atomisp)/css2400/runtime/event/interface/ \
-I$(atomisp)/css2400/runtime/eventq/interface/ \
-I$(atomisp)/css2400/runtime/frame/interface/ \
-I$(atomisp)/css2400/runtime/ifmtr/interface/ \
-I$(atomisp)/css2400/runtime/inputfifo/interface/ \
-I$(atomisp)/css2400/runtime/isp_param/interface/ \
-I$(atomisp)/css2400/runtime/isys/interface/ \
-I$(atomisp)/css2400/runtime/isys/src/ \
-I$(atomisp)/css2400/runtime/pipeline/interface/ \
-I$(atomisp)/css2400/runtime/queue/interface/ \
-I$(atomisp)/css2400/runtime/queue/src/ \
-I$(atomisp)/css2400/runtime/rmgr/interface/ \
-I$(atomisp)/css2400/runtime/spctrl/interface/ \
-I$(atomisp)/css2400/runtime/tagger/interface/
ifeq ($(CONFIG_ION),y)
INCLUDES += -I$(srctree)/drivers/staging/android/ion
endif
DEFINES := -DHRT_HW -DHRT_ISP_CSS_CUSTOM_HOST -DHRT_USE_VIR_ADDRS -DHRT_KERNEL -D__HOST__
DEFINES += -DUSE_DYNAMIC_BIN
DEFINES += -DISP_POWER_GATING
DEFINES += -DUSE_INTERRUPTS
#DEFINES += -DUSE_SSSE3
DEFINES += -DPUNIT_CAMERA_BUSY
DEFINES += -DUSE_KMEM_CACHE
DEFINES += -DATOMISP_POSTFIX=\"css2400b0_v21\" -DISP2400B0
DEFINES += -DSYSTEM_hive_isp_css_2400_system -DISP2400
ccflags-y += $(INCLUDES) $(DEFINES) -fno-common -Werror

209
drivers/staging/media/atomisp/pci/atomisp2/atomisp-regs.h Normal file
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef ATOMISP_REGS_H
#define ATOMISP_REGS_H
/* common register definitions */
#define PUNIT_PORT 0x04
#define CCK_PORT 0x14
#define PCICMDSTS 0x01
#define INTR 0x0f
#define MSI_CAPID 0x24
#define MSI_ADDRESS 0x25
#define MSI_DATA 0x26
#define INTR_CTL 0x27
#define PCI_MSI_CAPID 0x90
#define PCI_MSI_ADDR 0x94
#define PCI_MSI_DATA 0x98
#define PCI_INTERRUPT_CTRL 0x9C
#define PCI_I_CONTROL 0xfc
/* MRFLD specific register definitions */
#define MRFLD_CSI_AFE 0x39
#define MRFLD_CSI_CONTROL 0x3a
#define MRFLD_CSI_RCOMP 0x3d
#define MRFLD_PCI_PMCS 0x84
#define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL 0xd4
#define MRFLD_PCI_CSI_AFE_HS_CONTROL 0xdc
#define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL 0xe0
#define MRFLD_PCI_CSI_CONTROL 0xe8
#define MRFLD_PCI_CSI_AFE_TRIM_CONTROL 0xe4
#define MRFLD_PCI_CSI_DEADLINE_CONTROL 0xec
#define MRFLD_PCI_CSI_RCOMP_CONTROL 0xf4
/* Select Arasan (legacy)/Intel input system */
#define MRFLD_PCI_CSI_CONTROL_PARPATHEN BIT(24)
/* Enable CSI interface (ANN B0/K0) */
#define MRFLD_PCI_CSI_CONTROL_CSI_READY BIT(25)
/*
* Enables the combining of adjacent 32-byte read requests to the same
* cache line. When cleared, each 32-byte read request is sent as a
* separate request on the IB interface.
*/
#define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING 0x1
/*
* Register: MRFLD_PCI_CSI_RCOMP_CONTROL
* If cleared, the high speed clock going to the digital logic is gated when
* RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
* If this bit is set, then the high speed clock is not gated during the
* update cycle.
*/
#define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE 0x800000
/*
* Enables the combining of adjacent 32-byte write requests to the same
* cache line. When cleared, each 32-byte write request is sent as a
* separate request on the IB interface.
*/
#define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING 0x2
#define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK 0xc
#define MRFLD_PCI_CSI1_HSRXCLKTRIM 0x2
#define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT 16
#define MRFLD_PCI_CSI2_HSRXCLKTRIM 0x3
#define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT 24
#define MRFLD_PCI_CSI3_HSRXCLKTRIM 0x2
#define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT 28
#define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK 0xf
/*
* This register is IUINT MMIO register, it is used to select the CSI
* receiver backend.
* 1: SH CSI backend
* 0: Arasan CSI backend
*/
#define MRFLD_CSI_RECEIVER_SELECTION_REG 0x8081c
#define MRFLD_INTR_CLEAR_REG 0x50c
#define MRFLD_INTR_STATUS_REG 0x508
#define MRFLD_INTR_ENABLE_REG 0x510
#define MRFLD_MAX_ZOOM_FACTOR 1024
/* MRFLD ISP POWER related */
#define MRFLD_ISPSSPM0 0x39
#define MRFLD_ISPSSPM0_ISPSSC_OFFSET 0
#define MRFLD_ISPSSPM0_ISPSSS_OFFSET 24
#define MRFLD_ISPSSPM0_ISPSSC_MASK 0x3
#define MRFLD_ISPSSPM0_IUNIT_POWER_ON 0
#define MRFLD_ISPSSPM0_IUNIT_POWER_OFF 0x3
#define MRFLD_ISPSSDVFS 0x13F
#define MRFLD_BIT0 0x0001
#define MRFLD_BIT1 0x0002
/* MRFLD CSI lane configuration related */
#define MRFLD_PORT_CONFIG_NUM 8
#define MRFLD_PORT_NUM 3
#define MRFLD_PORT1_ENABLE_SHIFT 0
#define MRFLD_PORT2_ENABLE_SHIFT 1
#define MRFLD_PORT3_ENABLE_SHIFT 2
#define MRFLD_PORT1_LANES_SHIFT 3
#define MRFLD_PORT2_LANES_SHIFT 7
#define MRFLD_PORT3_LANES_SHIFT 8
#define MRFLD_PORT_CONFIG_MASK 0x000f03ff
#define MRFLD_PORT_CONFIGCODE_SHIFT 16
#define MRFLD_ALL_CSI_PORTS_OFF_MASK 0x7
#define CHV_PORT3_LANES_SHIFT 9
#define CHV_PORT_CONFIG_MASK 0x1f07ff
#define ISPSSPM1 0x3a
#define ISP_FREQ_STAT_MASK (0x1f << ISP_FREQ_STAT_OFFSET)
#define ISP_REQ_FREQ_MASK 0x1f
#define ISP_FREQ_VALID_MASK (0x1 << ISP_FREQ_VALID_OFFSET)
#define ISP_FREQ_STAT_OFFSET 0x18
#define ISP_REQ_GUAR_FREQ_OFFSET 0x8
#define ISP_REQ_FREQ_OFFSET 0x0
#define ISP_FREQ_VALID_OFFSET 0x7
#define ISP_FREQ_RULE_ANY 0x0
#define ISP_FREQ_457MHZ 0x1C9
#define ISP_FREQ_400MHZ 0x190
#define ISP_FREQ_356MHZ 0x164
#define ISP_FREQ_320MHZ 0x140
#define ISP_FREQ_266MHZ 0x10a
#define ISP_FREQ_200MHZ 0xc8
#define ISP_FREQ_100MHZ 0x64
#define HPLL_FREQ_800MHZ 0x320
#define HPLL_FREQ_1600MHZ 0x640
#define HPLL_FREQ_2000MHZ 0x7D0
#define CCK_FUSE_REG_0 0x08
#define CCK_FUSE_HPLL_FREQ_MASK 0x03
#if defined(ISP2401)
#define ISP_FREQ_MAX ISP_FREQ_320MHZ
#else
#define ISP_FREQ_MAX ISP_FREQ_400MHZ
#endif
/* ISP2401 CSI2+ receiver delay settings */
#define CSI2_PORT_A_BASE 0xC0000
#define CSI2_PORT_B_BASE 0xC2000
#define CSI2_PORT_C_BASE 0xC4000
#define CSI2_LANE_CL_BASE 0x418
#define CSI2_LANE_D0_BASE 0x420
#define CSI2_LANE_D1_BASE 0x428
#define CSI2_LANE_D2_BASE 0x430
#define CSI2_LANE_D3_BASE 0x438
#define CSI2_REG_RX_CSI_DLY_CNT_TERMEN 0
#define CSI2_REG_RX_CSI_DLY_CNT_SETTLE 0x4
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC0418
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC041C
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC0420
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC0424
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC0428
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC042C
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE2 0xC0430
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE2 0xC0434
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE3 0xC0438
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE3 0xC043C
#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC2418
#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC241C
#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC2420
#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC2424
#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC2428
#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC242C
#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC4418
#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC441C
#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC4420
#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC4424
#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC4428
#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC442C
#define DMA_BURST_SIZE_REG 0xCD408
#define ISP_DFS_TRY_TIMES 2
#endif /* ATOMISP_REGS_H */

610
drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.c Normal file
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/*
* Support for Clovertrail PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
/*
* This file implements loadable acceleration firmware API,
* including ioctls to map and unmap acceleration parameters and buffers.
*/
#include <linux/init.h>
#include <media/v4l2-event.h>
#include "atomisp_acc.h"
#include "atomisp_internal.h"
#include "atomisp_compat.h"
#include "atomisp_cmd.h"
#include "hrt/hive_isp_css_mm_hrt.h"
#include "memory_access/memory_access.h"
#include "ia_css.h"
static const struct {
unsigned int flag;
enum atomisp_css_pipe_id pipe_id;
} acc_flag_to_pipe[] = {
{ ATOMISP_ACC_FW_LOAD_FL_PREVIEW, CSS_PIPE_ID_PREVIEW },
{ ATOMISP_ACC_FW_LOAD_FL_COPY, CSS_PIPE_ID_COPY },
{ ATOMISP_ACC_FW_LOAD_FL_VIDEO, CSS_PIPE_ID_VIDEO },
{ ATOMISP_ACC_FW_LOAD_FL_CAPTURE, CSS_PIPE_ID_CAPTURE },
{ ATOMISP_ACC_FW_LOAD_FL_ACC, CSS_PIPE_ID_ACC }
};
/*
* Allocate struct atomisp_acc_fw along with space for firmware.
* The returned struct atomisp_acc_fw is cleared (firmware region is not).
*/
static struct atomisp_acc_fw *acc_alloc_fw(unsigned int fw_size)
{
struct atomisp_acc_fw *acc_fw;
acc_fw = kzalloc(sizeof(*acc_fw), GFP_KERNEL);
if (!acc_fw)
return NULL;
acc_fw->fw = vmalloc(fw_size);
if (!acc_fw->fw) {
kfree(acc_fw);
return NULL;
}
return acc_fw;
}
static void acc_free_fw(struct atomisp_acc_fw *acc_fw)
{
vfree(acc_fw->fw);
kfree(acc_fw);
}
static struct atomisp_acc_fw *
acc_get_fw(struct atomisp_sub_device *asd, unsigned int handle)
{
struct atomisp_acc_fw *acc_fw;
list_for_each_entry(acc_fw, &asd->acc.fw, list)
if (acc_fw->handle == handle)
return acc_fw;
return NULL;
}
static struct atomisp_map *acc_get_map(struct atomisp_sub_device *asd,
unsigned long css_ptr, size_t length)
{
struct atomisp_map *atomisp_map;
list_for_each_entry(atomisp_map, &asd->acc.memory_maps, list) {
if (atomisp_map->ptr == css_ptr &&
atomisp_map->length == length)
return atomisp_map;
}
return NULL;
}
static int acc_stop_acceleration(struct atomisp_sub_device *asd)
{
int ret;
ret = atomisp_css_stop_acc_pipe(asd);
atomisp_css_destroy_acc_pipe(asd);
return ret;
}
void atomisp_acc_cleanup(struct atomisp_device *isp)
{
int i;
for (i = 0; i < isp->num_of_streams; i++)
ida_destroy(&isp->asd[i].acc.ida);
}
void atomisp_acc_release(struct atomisp_sub_device *asd)
{
struct atomisp_acc_fw *acc_fw, *ta;
struct atomisp_map *atomisp_map, *tm;
/* Stop acceleration if already running */
if (asd->acc.pipeline)
acc_stop_acceleration(asd);
/* Unload all loaded acceleration binaries */
list_for_each_entry_safe(acc_fw, ta, &asd->acc.fw, list) {
list_del(&acc_fw->list);
ida_remove(&asd->acc.ida, acc_fw->handle);
acc_free_fw(acc_fw);
}
/* Free all mapped memory blocks */
list_for_each_entry_safe(atomisp_map, tm, &asd->acc.memory_maps, list) {
list_del(&atomisp_map->list);
mmgr_free(atomisp_map->ptr);
kfree(atomisp_map);
}
}
int atomisp_acc_load_to_pipe(struct atomisp_sub_device *asd,
struct atomisp_acc_fw_load_to_pipe *user_fw)
{
static const unsigned int pipeline_flags =
ATOMISP_ACC_FW_LOAD_FL_PREVIEW | ATOMISP_ACC_FW_LOAD_FL_COPY |
ATOMISP_ACC_FW_LOAD_FL_VIDEO |
ATOMISP_ACC_FW_LOAD_FL_CAPTURE | ATOMISP_ACC_FW_LOAD_FL_ACC;
struct atomisp_acc_fw *acc_fw;
int handle;
if (!user_fw->data || user_fw->size < sizeof(*acc_fw->fw))
return -EINVAL;
/* Binary has to be enabled at least for one pipeline */
if (!(user_fw->flags & pipeline_flags))
return -EINVAL;
/* We do not support other flags yet */
if (user_fw->flags & ~pipeline_flags)
return -EINVAL;
if (user_fw->type < ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT ||
user_fw->type > ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE)
return -EINVAL;
if (asd->acc.pipeline || asd->acc.extension_mode)
return -EBUSY;
acc_fw = acc_alloc_fw(user_fw->size);
if (!acc_fw)
return -ENOMEM;
if (copy_from_user(acc_fw->fw, user_fw->data, user_fw->size)) {
acc_free_fw(acc_fw);
return -EFAULT;
}
if (!ida_pre_get(&asd->acc.ida, GFP_KERNEL) ||
ida_get_new_above(&asd->acc.ida, 1, &handle)) {
acc_free_fw(acc_fw);
return -ENOSPC;
}
user_fw->fw_handle = handle;
acc_fw->handle = handle;
acc_fw->flags = user_fw->flags;
acc_fw->type = user_fw->type;
acc_fw->fw->handle = handle;
/*
* correct isp firmware type in order ISP firmware can be appended
* to correct pipe properly
*/
if (acc_fw->fw->type == ia_css_isp_firmware) {
static const int type_to_css[] = {
[ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT] =
IA_CSS_ACC_OUTPUT,
[ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER] =
IA_CSS_ACC_VIEWFINDER,
[ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE] =
IA_CSS_ACC_STANDALONE,
};
acc_fw->fw->info.isp.type = type_to_css[acc_fw->type];
}
list_add_tail(&acc_fw->list, &asd->acc.fw);
return 0;
}
int atomisp_acc_load(struct atomisp_sub_device *asd,
struct atomisp_acc_fw_load *user_fw)
{
struct atomisp_acc_fw_load_to_pipe ltp = {0};
int r;
ltp.flags = ATOMISP_ACC_FW_LOAD_FL_ACC;
ltp.type = ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE;
ltp.size = user_fw->size;
ltp.data = user_fw->data;
r = atomisp_acc_load_to_pipe(asd, &ltp);
user_fw->fw_handle = ltp.fw_handle;
return r;
}
int atomisp_acc_unload(struct atomisp_sub_device *asd, unsigned int *handle)
{
struct atomisp_acc_fw *acc_fw;
if (asd->acc.pipeline || asd->acc.extension_mode)
return -EBUSY;
acc_fw = acc_get_fw(asd, *handle);
if (!acc_fw)
return -EINVAL;
list_del(&acc_fw->list);
ida_remove(&asd->acc.ida, acc_fw->handle);
acc_free_fw(acc_fw);
return 0;
}
int atomisp_acc_start(struct atomisp_sub_device *asd, unsigned int *handle)
{
struct atomisp_device *isp = asd->isp;
struct atomisp_acc_fw *acc_fw;
int ret;
unsigned int nbin;
if (asd->acc.pipeline || asd->acc.extension_mode)
return -EBUSY;
/* Invalidate caches. FIXME: should flush only necessary buffers */
wbinvd();
ret = atomisp_css_create_acc_pipe(asd);
if (ret)
return ret;
nbin = 0;
list_for_each_entry(acc_fw, &asd->acc.fw, list) {
if (*handle != 0 && *handle != acc_fw->handle)
continue;
if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE)
continue;
/* Add the binary into the pipeline */
ret = atomisp_css_load_acc_binary(asd, acc_fw->fw, nbin);
if (ret < 0) {
dev_err(isp->dev, "acc_load_binary failed\n");
goto err_stage;
}
ret = atomisp_css_set_acc_parameters(acc_fw);
if (ret < 0) {
dev_err(isp->dev, "acc_set_parameters failed\n");
goto err_stage;
}
nbin++;
}
if (nbin < 1) {
/* Refuse creating pipelines with no binaries */
dev_err(isp->dev, "%s: no acc binary available\n", __func__);
ret = -EINVAL;
goto err_stage;
}
ret = atomisp_css_start_acc_pipe(asd);
if (ret) {
dev_err(isp->dev, "%s: atomisp_acc_start_acc_pipe failed\n",
__func__);
goto err_stage;
}
return 0;
err_stage:
atomisp_css_destroy_acc_pipe(asd);
return ret;
}
int atomisp_acc_wait(struct atomisp_sub_device *asd, unsigned int *handle)
{
struct atomisp_device *isp = asd->isp;
int ret;
if (!asd->acc.pipeline)
return -ENOENT;
if (*handle && !acc_get_fw(asd, *handle))
return -EINVAL;
ret = atomisp_css_wait_acc_finish(asd);
if (acc_stop_acceleration(asd) == -EIO) {
atomisp_reset(isp);
return -EINVAL;
}
return ret;
}
void atomisp_acc_done(struct atomisp_sub_device *asd, unsigned int handle)
{
struct v4l2_event event = { 0 };
event.type = V4L2_EVENT_ATOMISP_ACC_COMPLETE;
event.u.frame_sync.frame_sequence = atomic_read(&asd->sequence);
event.id = handle;
v4l2_event_queue(asd->subdev.devnode, &event);
}
int atomisp_acc_map(struct atomisp_sub_device *asd, struct atomisp_acc_map *map)
{
struct atomisp_map *atomisp_map;
ia_css_ptr cssptr;
int pgnr;
if (map->css_ptr)
return -EINVAL;
if (asd->acc.pipeline)
return -EBUSY;
if (map->user_ptr) {
/* Buffer to map must be page-aligned */
if ((unsigned long)map->user_ptr & ~PAGE_MASK) {
dev_err(asd->isp->dev,
"%s: mapped buffer address %p is not page aligned\n",
__func__, map->user_ptr);
return -EINVAL;
}
pgnr = DIV_ROUND_UP(map->length, PAGE_SIZE);
cssptr = hrt_isp_css_mm_alloc_user_ptr(
map->length, map->user_ptr,
pgnr, HRT_USR_PTR,
(map->flags & ATOMISP_MAP_FLAG_CACHED));
} else {
/* Allocate private buffer. */
if (map->flags & ATOMISP_MAP_FLAG_CACHED)
cssptr = hrt_isp_css_mm_calloc_cached(map->length);
else
cssptr = hrt_isp_css_mm_calloc(map->length);
}
if (!cssptr)
return -ENOMEM;
atomisp_map = kmalloc(sizeof(*atomisp_map), GFP_KERNEL);
if (!atomisp_map) {
mmgr_free(cssptr);
return -ENOMEM;
}
atomisp_map->ptr = cssptr;
atomisp_map->length = map->length;
list_add(&atomisp_map->list, &asd->acc.memory_maps);
dev_dbg(asd->isp->dev, "%s: userptr %p, css_address 0x%x, size %d\n",
__func__, map->user_ptr, cssptr, map->length);
map->css_ptr = cssptr;
return 0;
}
int atomisp_acc_unmap(struct atomisp_sub_device *asd, struct atomisp_acc_map *map)
{
struct atomisp_map *atomisp_map;
if (asd->acc.pipeline)
return -EBUSY;
atomisp_map = acc_get_map(asd, map->css_ptr, map->length);
if (!atomisp_map)
return -EINVAL;
list_del(&atomisp_map->list);
mmgr_free(atomisp_map->ptr);
kfree(atomisp_map);
return 0;
}
int atomisp_acc_s_mapped_arg(struct atomisp_sub_device *asd,
struct atomisp_acc_s_mapped_arg *arg)
{
struct atomisp_acc_fw *acc_fw;
if (arg->memory >= ATOMISP_ACC_NR_MEMORY)
return -EINVAL;
if (asd->acc.pipeline)
return -EBUSY;
acc_fw = acc_get_fw(asd, arg->fw_handle);
if (!acc_fw)
return -EINVAL;
if (arg->css_ptr != 0 || arg->length != 0) {
/* Unless the parameter is cleared, check that it exists */
if (!acc_get_map(asd, arg->css_ptr, arg->length))
return -EINVAL;
}
acc_fw->args[arg->memory].length = arg->length;
acc_fw->args[arg->memory].css_ptr = arg->css_ptr;
dev_dbg(asd->isp->dev, "%s: mem %d, address %p, size %ld\n",
__func__, arg->memory, (void *)arg->css_ptr,
(unsigned long)arg->length);
return 0;
}
/*
* Appends the loaded acceleration binary extensions to the
* current ISP mode. Must be called just before sh_css_start().
*/
int atomisp_acc_load_extensions(struct atomisp_sub_device *asd)
{
struct atomisp_acc_fw *acc_fw;
bool ext_loaded = false;
bool continuous = asd->continuous_mode->val &&
asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW;
int ret = 0, i = -1;
struct atomisp_device *isp = asd->isp;
if (asd->acc.pipeline || asd->acc.extension_mode)
return -EBUSY;
/* Invalidate caches. FIXME: should flush only necessary buffers */
wbinvd();
list_for_each_entry(acc_fw, &asd->acc.fw, list) {
if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT &&
acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER)
continue;
for (i = 0; i < ARRAY_SIZE(acc_flag_to_pipe); i++) {
/* QoS (ACC pipe) acceleration stages are currently
* allowed only in continuous mode. Skip them for
* all other modes. */
if (!continuous &&
acc_flag_to_pipe[i].flag ==
ATOMISP_ACC_FW_LOAD_FL_ACC)
continue;
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
ret = atomisp_css_load_acc_extension(asd,
acc_fw->fw,
acc_flag_to_pipe[i].pipe_id,
acc_fw->type);
if (ret) {
i--;
goto error;
}
ext_loaded = true;
}
}
ret = atomisp_css_set_acc_parameters(acc_fw);
if (ret < 0)
goto error;
}
if (!ext_loaded)
return ret;
ret = atomisp_css_update_stream(asd);
if (ret) {
dev_err(isp->dev, "%s: update stream failed.\n", __func__);
goto error;
}
asd->acc.extension_mode = true;
return 0;
error:
for (; i >= 0; i--) {
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
atomisp_css_unload_acc_extension(asd, acc_fw->fw,
acc_flag_to_pipe[i].pipe_id);
}
}
list_for_each_entry_continue_reverse(acc_fw, &asd->acc.fw, list) {
if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT &&
acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER)
continue;
for (i = ARRAY_SIZE(acc_flag_to_pipe) - 1; i >= 0; i--) {
if (!continuous &&
acc_flag_to_pipe[i].flag ==
ATOMISP_ACC_FW_LOAD_FL_ACC)
continue;
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
atomisp_css_unload_acc_extension(asd,
acc_fw->fw,
acc_flag_to_pipe[i].pipe_id);
}
}
}
return ret;
}
void atomisp_acc_unload_extensions(struct atomisp_sub_device *asd)
{
struct atomisp_acc_fw *acc_fw;
int i;
if (!asd->acc.extension_mode)
return;
list_for_each_entry_reverse(acc_fw, &asd->acc.fw, list) {
if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT &&
acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER)
continue;
for (i = ARRAY_SIZE(acc_flag_to_pipe) - 1; i >= 0; i--) {
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
atomisp_css_unload_acc_extension(asd,
acc_fw->fw,
acc_flag_to_pipe[i].pipe_id);
}
}
}
asd->acc.extension_mode = false;
}
int atomisp_acc_set_state(struct atomisp_sub_device *asd,
struct atomisp_acc_state *arg)
{
struct atomisp_acc_fw *acc_fw;
bool enable = (arg->flags & ATOMISP_STATE_FLAG_ENABLE) != 0;
struct ia_css_pipe *pipe;
enum ia_css_err r;
int i;
if (!asd->acc.extension_mode)
return -EBUSY;
if (arg->flags & ~ATOMISP_STATE_FLAG_ENABLE)
return -EINVAL;
acc_fw = acc_get_fw(asd, arg->fw_handle);
if (!acc_fw)
return -EINVAL;
if (enable)
wbinvd();
for (i = 0; i < ARRAY_SIZE(acc_flag_to_pipe); i++) {
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
pipe = asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].
pipes[acc_flag_to_pipe[i].pipe_id];
r = ia_css_pipe_set_qos_ext_state(pipe, acc_fw->handle,
enable);
if (r != IA_CSS_SUCCESS)
return -EBADRQC;
}
}
if (enable)
acc_fw->flags |= ATOMISP_ACC_FW_LOAD_FL_ENABLE;
else
acc_fw->flags &= ~ATOMISP_ACC_FW_LOAD_FL_ENABLE;
return 0;
}
int atomisp_acc_get_state(struct atomisp_sub_device *asd,
struct atomisp_acc_state *arg)
{
struct atomisp_acc_fw *acc_fw;
if (!asd->acc.extension_mode)
return -EBUSY;
acc_fw = acc_get_fw(asd, arg->fw_handle);
if (!acc_fw)
return -EINVAL;
arg->flags = acc_fw->flags;
return 0;
}

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/*
* Support for Clovertrail PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_ACC_H__
#define __ATOMISP_ACC_H__
#include <linux/atomisp.h>
#include "atomisp_internal.h"
#include "ia_css_types.h"
/*
* Interface functions for AtomISP driver acceleration API implementation.
*/
struct atomisp_sub_device;
void atomisp_acc_cleanup(struct atomisp_device *isp);
/*
* Free up any allocated resources.
* Must be called each time when the device is closed.
* Note that there isn't corresponding open() call;
* this function may be called sequentially multiple times.
* Must be called to free up resources before driver is unloaded.
*/
void atomisp_acc_release(struct atomisp_sub_device *asd);
/* Load acceleration binary. DEPRECATED. */
int atomisp_acc_load(struct atomisp_sub_device *asd,
struct atomisp_acc_fw_load *fw);
/* Load acceleration binary with specified properties */
int atomisp_acc_load_to_pipe(struct atomisp_sub_device *asd,
struct atomisp_acc_fw_load_to_pipe *fw);
/* Unload specified acceleration binary */
int atomisp_acc_unload(struct atomisp_sub_device *asd,
unsigned int *handle);
/*
* Map a memory region into ISP memory space.
*/
int atomisp_acc_map(struct atomisp_sub_device *asd,
struct atomisp_acc_map *map);
/*
* Unmap a mapped memory region.
*/
int atomisp_acc_unmap(struct atomisp_sub_device *asd,
struct atomisp_acc_map *map);
/*
* Set acceleration binary argument to a previously mapped memory region.
*/
int atomisp_acc_s_mapped_arg(struct atomisp_sub_device *asd,
struct atomisp_acc_s_mapped_arg *arg);
/*
* Start acceleration.
* Return immediately, acceleration is left running in background.
* Specify either acceleration binary or pipeline which to start.
*/
int atomisp_acc_start(struct atomisp_sub_device *asd,
unsigned int *handle);
/*
* Wait until acceleration finishes.
* This MUST be called after each acceleration has been started.
* Specify either acceleration binary or pipeline handle.
*/
int atomisp_acc_wait(struct atomisp_sub_device *asd,
unsigned int *handle);
/*
* Used by ISR to notify ACC stage finished.
* This is internally used and does not export as IOCTL.
*/
void atomisp_acc_done(struct atomisp_sub_device *asd, unsigned int handle);
/*
* Appends the loaded acceleration binary extensions to the
* current ISP mode. Must be called just before atomisp_css_start().
*/
int atomisp_acc_load_extensions(struct atomisp_sub_device *asd);
/*
* Must be called after streaming is stopped:
* unloads any loaded acceleration extensions.
*/
void atomisp_acc_unload_extensions(struct atomisp_sub_device *asd);
/*
* Set acceleration firmware flags.
*/
int atomisp_acc_set_state(struct atomisp_sub_device *asd,
struct atomisp_acc_state *arg);
/*
* Get acceleration firmware flags.
*/
int atomisp_acc_get_state(struct atomisp_sub_device *asd,
struct atomisp_acc_state *arg);
#endif /* __ATOMISP_ACC_H__ */

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_CMD_H__
#define __ATOMISP_CMD_H__
#include <linux/atomisp.h>
#include <linux/interrupt.h>
#include <linux/videodev2.h>
#include <media/v4l2-subdev.h>
#include "atomisp_internal.h"
#include "ia_css_types.h"
#include "ia_css.h"
struct atomisp_device;
struct atomisp_css_frame;
#define MSI_ENABLE_BIT 16
#define INTR_DISABLE_BIT 10
#define BUS_MASTER_ENABLE 2
#define MEMORY_SPACE_ENABLE 1
#define INTR_IER 24
#define INTR_IIR 16
#ifdef ISP2401
#define RUNMODE_MASK (ATOMISP_RUN_MODE_VIDEO | ATOMISP_RUN_MODE_STILL_CAPTURE \
| ATOMISP_RUN_MODE_PREVIEW)
/* FIXME: check if can go */
extern int atomisp_punit_hpll_freq;
#endif
/*
* Helper function
*/
void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr,
unsigned int size);
struct camera_mipi_info *atomisp_to_sensor_mipi_info(struct v4l2_subdev *sd);
struct atomisp_video_pipe *atomisp_to_video_pipe(struct video_device *dev);
struct atomisp_acc_pipe *atomisp_to_acc_pipe(struct video_device *dev);
int atomisp_reset(struct atomisp_device *isp);
void atomisp_flush_bufs_and_wakeup(struct atomisp_sub_device *asd);
void atomisp_clear_css_buffer_counters(struct atomisp_sub_device *asd);
#ifndef ISP2401
bool atomisp_buffers_queued(struct atomisp_sub_device *asd);
#else
bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe);
#endif
/* TODO:should be here instead of atomisp_helper.h
extern void __iomem *atomisp_io_base;
static inline void __iomem *atomisp_get_io_virt_addr(unsigned int address)
{
void __iomem *ret = atomisp_io_base + (address & 0x003FFFFF);
return ret;
}
*/
void *atomisp_kernel_malloc(size_t bytes);
void *atomisp_kernel_zalloc(size_t bytes, bool zero_mem);
void atomisp_kernel_free(void *ptr);
/*
* Interrupt functions
*/
void atomisp_msi_irq_init(struct atomisp_device *isp, struct pci_dev *dev);
void atomisp_msi_irq_uninit(struct atomisp_device *isp, struct pci_dev *dev);
void atomisp_wdt_work(struct work_struct *work);
#ifndef ISP2401
void atomisp_wdt(unsigned long isp_addr);
#else
void atomisp_wdt(unsigned long pipe_addr);
#endif
void atomisp_setup_flash(struct atomisp_sub_device *asd);
irqreturn_t atomisp_isr(int irq, void *dev);
irqreturn_t atomisp_isr_thread(int irq, void *isp_ptr);
const struct atomisp_format_bridge *get_atomisp_format_bridge_from_mbus(
u32 mbus_code);
bool atomisp_is_mbuscode_raw(uint32_t code);
int atomisp_get_frame_pgnr(struct atomisp_device *isp,
const struct atomisp_css_frame *frame, u32 *p_pgnr);
void atomisp_delayed_init_work(struct work_struct *work);
/*
* Get internal fmt according to V4L2 fmt
*/
bool atomisp_is_viewfinder_support(struct atomisp_device *isp);
/*
* ISP features control function
*/
/*
#ifdef ISP2401
* Function to set sensor runmode by user when
* ATOMISP_IOC_S_SENSOR_RUNMODE ioctl was called
*/
int atomisp_set_sensor_runmode(struct atomisp_sub_device *asd,
struct atomisp_s_runmode *runmode);
/*
#endif
* Function to enable/disable lens geometry distortion correction (GDC) and
* chromatic aberration correction (CAC)
*/
int atomisp_gdc_cac(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to enable/disable low light mode (including ANR)
*/
int atomisp_low_light(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to enable/disable extra noise reduction (XNR) in low light
* condition
*/
int atomisp_xnr(struct atomisp_sub_device *asd, int flag, int *arg);
int atomisp_formats(struct atomisp_sub_device *asd, int flag,
struct atomisp_formats_config *config);
/*
* Function to configure noise reduction
*/
int atomisp_nr(struct atomisp_sub_device *asd, int flag,
struct atomisp_nr_config *config);
/*
* Function to configure temporal noise reduction (TNR)
*/
int atomisp_tnr(struct atomisp_sub_device *asd, int flag,
struct atomisp_tnr_config *config);
/*
* Function to configure black level compensation
*/
int atomisp_black_level(struct atomisp_sub_device *asd, int flag,
struct atomisp_ob_config *config);
/*
* Function to configure edge enhancement
*/
int atomisp_ee(struct atomisp_sub_device *asd, int flag,
struct atomisp_ee_config *config);
/*
* Function to update Gamma table for gamma, brightness and contrast config
*/
int atomisp_gamma(struct atomisp_sub_device *asd, int flag,
struct atomisp_gamma_table *config);
/*
* Function to update Ctc table for Chroma Enhancement
*/
int atomisp_ctc(struct atomisp_sub_device *asd, int flag,
struct atomisp_ctc_table *config);
/*
* Function to update gamma correction parameters
*/
int atomisp_gamma_correction(struct atomisp_sub_device *asd, int flag,
struct atomisp_gc_config *config);
/*
* Function to update Gdc table for gdc
*/
int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag,
struct atomisp_morph_table *config);
/*
* Function to update table for macc
*/
int atomisp_macc_table(struct atomisp_sub_device *asd, int flag,
struct atomisp_macc_config *config);
/*
* Function to get DIS statistics.
*/
int atomisp_get_dis_stat(struct atomisp_sub_device *asd,
struct atomisp_dis_statistics *stats);
/*
* Function to get DVS2 BQ resolution settings
*/
int atomisp_get_dvs2_bq_resolutions(struct atomisp_sub_device *asd,
struct atomisp_dvs2_bq_resolutions *bq_res);
/*
* Function to set the DIS coefficients.
*/
int atomisp_set_dis_coefs(struct atomisp_sub_device *asd,
struct atomisp_dis_coefficients *coefs);
/*
* Function to set the DIS motion vector.
*/
int atomisp_set_dis_vector(struct atomisp_sub_device *asd,
struct atomisp_dis_vector *vector);
/*
* Function to set/get 3A stat from isp
*/
int atomisp_3a_stat(struct atomisp_sub_device *asd, int flag,
struct atomisp_3a_statistics *config);
/*
* Function to get metadata from isp
*/
int atomisp_get_metadata(struct atomisp_sub_device *asd, int flag,
struct atomisp_metadata *config);
int atomisp_get_metadata_by_type(struct atomisp_sub_device *asd, int flag,
struct atomisp_metadata_with_type *config);
int atomisp_set_parameters(struct video_device *vdev,
struct atomisp_parameters *arg);
/*
* Function to set/get isp parameters to isp
*/
int atomisp_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_parm *config);
/*
* Function to configure color effect of the image
*/
int atomisp_color_effect(struct atomisp_sub_device *asd, int flag,
__s32 *effect);
/*
* Function to configure bad pixel correction
*/
int atomisp_bad_pixel(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to configure bad pixel correction params
*/
int atomisp_bad_pixel_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_dp_config *config);
/*
* Function to enable/disable video image stablization
*/
int atomisp_video_stable(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to configure fixed pattern noise
*/
int atomisp_fixed_pattern(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to configure fixed pattern noise table
*/
int atomisp_fixed_pattern_table(struct atomisp_sub_device *asd,
struct v4l2_framebuffer *config);
/*
* Function to configure false color correction
*/
int atomisp_false_color(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to configure false color correction params
*/
int atomisp_false_color_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_de_config *config);
/*
* Function to configure white balance params
*/
int atomisp_white_balance_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_wb_config *config);
int atomisp_3a_config_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_3a_config *config);
/*
* Function to setup digital zoom
*/
int atomisp_digital_zoom(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function set camera_prefiles.xml current sensor pixel array size
*/
int atomisp_set_array_res(struct atomisp_sub_device *asd,
struct atomisp_resolution *config);
/*
* Function to calculate real zoom region for every pipe
*/
int atomisp_calculate_real_zoom_region(struct atomisp_sub_device *asd,
struct atomisp_css_dz_config *dz_config,
enum atomisp_css_pipe_id css_pipe_id);
int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
struct atomisp_parameters *arg,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_cp_lsc_table(struct atomisp_sub_device *asd,
struct atomisp_shading_table *source_st,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd,
struct ia_css_dvs2_coefficients *coefs,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_cp_morph_table(struct atomisp_sub_device *asd,
struct atomisp_morph_table *source_morph_table,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_cp_dvs_6axis_config(struct atomisp_sub_device *asd,
struct atomisp_dvs_6axis_config *user_6axis_config,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_makeup_css_parameters(struct atomisp_sub_device *asd,
struct atomisp_parameters *arg,
struct atomisp_css_params *css_param);
int atomisp_compare_grid(struct atomisp_sub_device *asd,
struct atomisp_grid_info *atomgrid);
int atomisp_get_sensor_mode_data(struct atomisp_sub_device *asd,
struct atomisp_sensor_mode_data *config);
int atomisp_get_fmt(struct video_device *vdev, struct v4l2_format *f);
/* This function looks up the closest available resolution. */
int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f,
bool *res_overflow);
int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f);
int atomisp_set_fmt_file(struct video_device *vdev, struct v4l2_format *f);
int atomisp_set_shading_table(struct atomisp_sub_device *asd,
struct atomisp_shading_table *shading_table);
int atomisp_offline_capture_configure(struct atomisp_sub_device *asd,
struct atomisp_cont_capture_conf *cvf_config);
int atomisp_ospm_dphy_down(struct atomisp_device *isp);
int atomisp_ospm_dphy_up(struct atomisp_device *isp);
int atomisp_exif_makernote(struct atomisp_sub_device *asd,
struct atomisp_makernote_info *config);
void atomisp_free_internal_buffers(struct atomisp_sub_device *asd);
int atomisp_s_ae_window(struct atomisp_sub_device *asd,
struct atomisp_ae_window *arg);
int atomisp_flash_enable(struct atomisp_sub_device *asd,
int num_frames);
int atomisp_freq_scaling(struct atomisp_device *vdev,
enum atomisp_dfs_mode mode,
bool force);
void atomisp_buf_done(struct atomisp_sub_device *asd, int error,
enum atomisp_css_buffer_type buf_type,
enum atomisp_css_pipe_id css_pipe_id,
bool q_buffers, enum atomisp_input_stream_id stream_id);
void atomisp_css_flush(struct atomisp_device *isp);
int atomisp_source_pad_to_stream_id(struct atomisp_sub_device *asd,
uint16_t source_pad);
/*
* Events. Only one event has to be exported for now.
*/
void atomisp_eof_event(struct atomisp_sub_device *asd, uint8_t exp_id);
mipi_port_ID_t __get_mipi_port(struct atomisp_device *isp,
enum atomisp_camera_port port);
bool atomisp_is_vf_pipe(struct atomisp_video_pipe *pipe);
void atomisp_apply_css_parameters(
struct atomisp_sub_device *asd,
struct atomisp_css_params *css_param);
void atomisp_free_css_parameters(struct atomisp_css_params *css_param);
void atomisp_handle_parameter_and_buffer(struct atomisp_video_pipe *pipe);
void atomisp_flush_params_queue(struct atomisp_video_pipe *asd);
/*
* Function to do Raw Buffer related operation, after enable Lock Unlock Raw Buffer
*/
int atomisp_exp_id_unlock(struct atomisp_sub_device *asd, int *exp_id);
int atomisp_exp_id_capture(struct atomisp_sub_device *asd, int *exp_id);
/*
* Function to update Raw Buffer bitmap
*/
int atomisp_set_raw_buffer_bitmap(struct atomisp_sub_device *asd, int exp_id);
void atomisp_init_raw_buffer_bitmap(struct atomisp_sub_device *asd);
/*
* Function to enable/disable zoom for capture pipe
*/
int atomisp_enable_dz_capt_pipe(struct atomisp_sub_device *asd,
unsigned int *enable);
/*
* Function to get metadata type bu pipe id
*/
enum atomisp_metadata_type
atomisp_get_metadata_type(struct atomisp_sub_device *asd,
enum ia_css_pipe_id pipe_id);
/*
* Function for HAL to inject a fake event to wake up poll thread
*/
int atomisp_inject_a_fake_event(struct atomisp_sub_device *asd, int *event);
/*
* Function for HAL to query how many invalid frames at the beginning of ISP
* pipeline output
*/
int atomisp_get_invalid_frame_num(struct video_device *vdev,
int *invalid_frame_num);
int atomisp_mrfld_power_up(struct atomisp_device *isp);
int atomisp_mrfld_power_down(struct atomisp_device *isp);
int atomisp_runtime_suspend(struct device *dev);
int atomisp_runtime_resume(struct device *dev);
#endif /* __ATOMISP_CMD_H__ */

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_COMMON_H__
#define __ATOMISP_COMMON_H__
#include <linux/atomisp.h>
#include <linux/v4l2-mediabus.h>
#include <media/videobuf-core.h>
#include "atomisp_compat.h"
#include "ia_css.h"
extern int dbg_level;
extern int dbg_func;
extern int mipicsi_flag;
extern int pad_w;
extern int pad_h;
#define CSS_DTRACE_VERBOSITY_LEVEL 5 /* Controls trace verbosity */
#define CSS_DTRACE_VERBOSITY_TIMEOUT 9 /* Verbosity on ISP timeout */
#define MRFLD_MAX_ZOOM_FACTOR 1024
#ifdef ISP2401
#define ATOMISP_CSS_ISP_PIPE_VERSION_2_2 0
#define ATOMISP_CSS_ISP_PIPE_VERSION_2_7 1
#endif
#define IS_ISP2401(isp) \
(((isp)->media_dev.hw_revision & ATOMISP_HW_REVISION_MASK) \
>= (ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT))
struct atomisp_format_bridge {
unsigned int pixelformat;
unsigned int depth;
u32 mbus_code;
enum atomisp_css_frame_format sh_fmt;
unsigned char description[32]; /* the same as struct v4l2_fmtdesc */
bool planar;
};
struct atomisp_fmt {
u32 pixelformat;
u32 depth;
u32 bytesperline;
u32 framesize;
u32 imagesize;
u32 width;
u32 height;
u32 bayer_order;
};
struct atomisp_buffer {
struct videobuf_buffer vb;
};
#endif

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/*
* Support for Clovertrail PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_COMPAT_H__
#define __ATOMISP_COMPAT_H__
#include "atomisp_compat_css20.h"
#include <linux/atomisp.h>
#include <media/videobuf-vmalloc.h>
#define CSS_RX_IRQ_INFO_BUFFER_OVERRUN \
CSS_ID(CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
#define CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE \
CSS_ID(CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE)
#define CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE \
CSS_ID(CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE)
#define CSS_RX_IRQ_INFO_ECC_CORRECTED \
CSS_ID(CSS_RX_IRQ_INFO_ECC_CORRECTED)
#define CSS_RX_IRQ_INFO_ERR_SOT \
CSS_ID(CSS_RX_IRQ_INFO_ERR_SOT)
#define CSS_RX_IRQ_INFO_ERR_SOT_SYNC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
#define CSS_RX_IRQ_INFO_ERR_CONTROL \
CSS_ID(CSS_RX_IRQ_INFO_ERR_CONTROL)
#define CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE \
CSS_ID(CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
#define CSS_RX_IRQ_INFO_ERR_CRC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_CRC)
#define CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID \
CSS_ID(CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
#define CSS_RX_IRQ_INFO_ERR_FRAME_SYNC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
#define CSS_RX_IRQ_INFO_ERR_FRAME_DATA \
CSS_ID(CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
#define CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT \
CSS_ID(CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
#define CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
#define CSS_RX_IRQ_INFO_ERR_LINE_SYNC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
#define CSS_RX_IRQ_INFO_INIT_TIMEOUT \
CSS_ID(CSS_RX_IRQ_INFO_INIT_TIMEOUT)
#define CSS_IRQ_INFO_CSS_RECEIVER_SOF CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_SOF)
#define CSS_IRQ_INFO_CSS_RECEIVER_EOF CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_EOF)
#define CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW \
CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW)
#define CSS_EVENT_OUTPUT_FRAME_DONE CSS_EVENT(OUTPUT_FRAME_DONE)
#define CSS_EVENT_SEC_OUTPUT_FRAME_DONE CSS_EVENT(SECOND_OUTPUT_FRAME_DONE)
#define CSS_EVENT_VF_OUTPUT_FRAME_DONE CSS_EVENT(VF_OUTPUT_FRAME_DONE)
#define CSS_EVENT_SEC_VF_OUTPUT_FRAME_DONE CSS_EVENT(SECOND_VF_OUTPUT_FRAME_DONE)
#define CSS_EVENT_3A_STATISTICS_DONE CSS_EVENT(3A_STATISTICS_DONE)
#define CSS_EVENT_DIS_STATISTICS_DONE CSS_EVENT(DIS_STATISTICS_DONE)
#define CSS_EVENT_PIPELINE_DONE CSS_EVENT(PIPELINE_DONE)
#define CSS_EVENT_METADATA_DONE CSS_EVENT(METADATA_DONE)
#define CSS_EVENT_ACC_STAGE_COMPLETE CSS_EVENT(ACC_STAGE_COMPLETE)
#define CSS_EVENT_TIMER CSS_EVENT(TIMER)
#define CSS_BUFFER_TYPE_METADATA CSS_ID(CSS_BUFFER_TYPE_METADATA)
#define CSS_BUFFER_TYPE_3A_STATISTICS CSS_ID(CSS_BUFFER_TYPE_3A_STATISTICS)
#define CSS_BUFFER_TYPE_DIS_STATISTICS CSS_ID(CSS_BUFFER_TYPE_DIS_STATISTICS)
#define CSS_BUFFER_TYPE_INPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_INPUT_FRAME)
#define CSS_BUFFER_TYPE_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_OUTPUT_FRAME)
#define CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME)
#define CSS_BUFFER_TYPE_VF_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_VF_OUTPUT_FRAME)
#define CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME)
#define CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME \
CSS_ID(CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME)
#define CSS_FORMAT_RAW_8 CSS_FORMAT(RAW_8)
#define CSS_FORMAT_RAW_10 CSS_FORMAT(RAW_10)
#define CSS_FORMAT_RAW_12 CSS_FORMAT(RAW_12)
#define CSS_FORMAT_RAW_16 CSS_FORMAT(RAW_16)
#define CSS_CAPTURE_MODE_RAW CSS_ID(CSS_CAPTURE_MODE_RAW)
#define CSS_CAPTURE_MODE_BAYER CSS_ID(CSS_CAPTURE_MODE_BAYER)
#define CSS_CAPTURE_MODE_PRIMARY CSS_ID(CSS_CAPTURE_MODE_PRIMARY)
#define CSS_CAPTURE_MODE_ADVANCED CSS_ID(CSS_CAPTURE_MODE_ADVANCED)
#define CSS_CAPTURE_MODE_LOW_LIGHT CSS_ID(CSS_CAPTURE_MODE_LOW_LIGHT)
#define CSS_MORPH_TABLE_NUM_PLANES CSS_ID(CSS_MORPH_TABLE_NUM_PLANES)
#define CSS_FRAME_FORMAT_NV11 CSS_ID(CSS_FRAME_FORMAT_NV11)
#define CSS_FRAME_FORMAT_NV12 CSS_ID(CSS_FRAME_FORMAT_NV12)
#define CSS_FRAME_FORMAT_NV16 CSS_ID(CSS_FRAME_FORMAT_NV16)
#define CSS_FRAME_FORMAT_NV21 CSS_ID(CSS_FRAME_FORMAT_NV21)
#define CSS_FRAME_FORMAT_NV61 CSS_ID(CSS_FRAME_FORMAT_NV61)
#define CSS_FRAME_FORMAT_YV12 CSS_ID(CSS_FRAME_FORMAT_YV12)
#define CSS_FRAME_FORMAT_YV16 CSS_ID(CSS_FRAME_FORMAT_YV16)
#define CSS_FRAME_FORMAT_YUV420 CSS_ID(CSS_FRAME_FORMAT_YUV420)
#define CSS_FRAME_FORMAT_YUV420_16 CSS_ID(CSS_FRAME_FORMAT_YUV420_16)
#define CSS_FRAME_FORMAT_YUV422 CSS_ID(CSS_FRAME_FORMAT_YUV422)
#define CSS_FRAME_FORMAT_YUV422_16 CSS_ID(CSS_FRAME_FORMAT_YUV422_16)
#define CSS_FRAME_FORMAT_UYVY CSS_ID(CSS_FRAME_FORMAT_UYVY)
#define CSS_FRAME_FORMAT_YUYV CSS_ID(CSS_FRAME_FORMAT_YUYV)
#define CSS_FRAME_FORMAT_YUV444 CSS_ID(CSS_FRAME_FORMAT_YUV444)
#define CSS_FRAME_FORMAT_YUV_LINE CSS_ID(CSS_FRAME_FORMAT_YUV_LINE)
#define CSS_FRAME_FORMAT_RAW CSS_ID(CSS_FRAME_FORMAT_RAW)
#define CSS_FRAME_FORMAT_RGB565 CSS_ID(CSS_FRAME_FORMAT_RGB565)
#define CSS_FRAME_FORMAT_PLANAR_RGB888 CSS_ID(CSS_FRAME_FORMAT_PLANAR_RGB888)
#define CSS_FRAME_FORMAT_RGBA888 CSS_ID(CSS_FRAME_FORMAT_RGBA888)
#define CSS_FRAME_FORMAT_QPLANE6 CSS_ID(CSS_FRAME_FORMAT_QPLANE6)
#define CSS_FRAME_FORMAT_BINARY_8 CSS_ID(CSS_FRAME_FORMAT_BINARY_8)
struct atomisp_device;
struct atomisp_sub_device;
struct video_device;
enum atomisp_input_stream_id;
struct atomisp_metadata_buf {
struct ia_css_metadata *metadata;
void *md_vptr;
struct list_head list;
};
void atomisp_css_debug_dump_sp_sw_debug_info(void);
void atomisp_css_debug_dump_debug_info(const char *context);
void atomisp_css_debug_set_dtrace_level(const unsigned int trace_level);
void atomisp_store_uint32(hrt_address addr, uint32_t data);
void atomisp_load_uint32(hrt_address addr, uint32_t *data);
int atomisp_css_init(struct atomisp_device *isp);
void atomisp_css_uninit(struct atomisp_device *isp);
void atomisp_css_suspend(struct atomisp_device *isp);
int atomisp_css_resume(struct atomisp_device *isp);
void atomisp_css_init_struct(struct atomisp_sub_device *asd);
int atomisp_css_irq_translate(struct atomisp_device *isp,
unsigned int *infos);
void atomisp_css_rx_get_irq_info(enum ia_css_csi2_port port,
unsigned int *infos);
void atomisp_css_rx_clear_irq_info(enum ia_css_csi2_port port,
unsigned int infos);
int atomisp_css_irq_enable(struct atomisp_device *isp,
enum atomisp_css_irq_info info, bool enable);
int atomisp_q_video_buffer_to_css(struct atomisp_sub_device *asd,
struct videobuf_vmalloc_memory *vm_mem,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_buffer_type css_buf_type,
enum atomisp_css_pipe_id css_pipe_id);
int atomisp_q_s3a_buffer_to_css(struct atomisp_sub_device *asd,
struct atomisp_s3a_buf *s3a_buf,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id css_pipe_id);
int atomisp_q_metadata_buffer_to_css(struct atomisp_sub_device *asd,
struct atomisp_metadata_buf *metadata_buf,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id css_pipe_id);
int atomisp_q_dis_buffer_to_css(struct atomisp_sub_device *asd,
struct atomisp_dis_buf *dis_buf,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id css_pipe_id);
void atomisp_css_mmu_invalidate_cache(void);
void atomisp_css_mmu_invalidate_tlb(void);
void atomisp_css_mmu_set_page_table_base_index(unsigned long base_index);
int atomisp_css_start(struct atomisp_sub_device *asd,
enum atomisp_css_pipe_id pipe_id, bool in_reset);
void atomisp_css_update_isp_params(struct atomisp_sub_device *asd);
void atomisp_css_update_isp_params_on_pipe(struct atomisp_sub_device *asd,
struct ia_css_pipe *pipe);
int atomisp_css_queue_buffer(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id pipe_id,
enum atomisp_css_buffer_type buf_type,
struct atomisp_css_buffer *isp_css_buffer);
int atomisp_css_dequeue_buffer(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id pipe_id,
enum atomisp_css_buffer_type buf_type,
struct atomisp_css_buffer *isp_css_buffer);
int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd,
uint16_t stream_id,
struct atomisp_s3a_buf *s3a_buf,
struct atomisp_dis_buf *dis_buf,
struct atomisp_metadata_buf *md_buf);
void atomisp_css_free_stat_buffers(struct atomisp_sub_device *asd);
void atomisp_css_free_3a_buffer(struct atomisp_s3a_buf *s3a_buf);
void atomisp_css_free_dis_buffer(struct atomisp_dis_buf *dis_buf);
void atomisp_css_free_metadata_buffer(struct atomisp_metadata_buf *metadata_buf);
int atomisp_css_get_grid_info(struct atomisp_sub_device *asd,
enum atomisp_css_pipe_id pipe_id,
int source_pad);
int atomisp_alloc_3a_output_buf(struct atomisp_sub_device *asd);
int atomisp_alloc_dis_coef_buf(struct atomisp_sub_device *asd);
int atomisp_alloc_metadata_output_buf(struct atomisp_sub_device *asd);
void atomisp_free_metadata_output_buf(struct atomisp_sub_device *asd);
void atomisp_css_get_dis_statistics(struct atomisp_sub_device *asd,
struct atomisp_css_buffer *isp_css_buffer,
struct ia_css_isp_dvs_statistics_map *dvs_map);
int atomisp_css_dequeue_event(struct atomisp_css_event *current_event);
void atomisp_css_temp_pipe_to_pipe_id(struct atomisp_sub_device *asd,
struct atomisp_css_event *current_event);
int atomisp_css_isys_set_resolution(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
struct v4l2_mbus_framefmt *ffmt,
int isys_stream);
void atomisp_css_isys_set_link(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
int link,
int isys_stream);
void atomisp_css_isys_set_valid(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
bool valid,
int isys_stream);
void atomisp_css_isys_set_format(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_stream_format format,
int isys_stream);
int atomisp_css_set_default_isys_config(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
struct v4l2_mbus_framefmt *ffmt);
int atomisp_css_isys_two_stream_cfg(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_stream_format input_format);
void atomisp_css_isys_two_stream_cfg_update_stream1(
struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_stream_format input_format,
unsigned int width, unsigned int height);
void atomisp_css_isys_two_stream_cfg_update_stream2(
struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_stream_format input_format,
unsigned int width, unsigned int height);
int atomisp_css_input_set_resolution(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
struct v4l2_mbus_framefmt *ffmt);
void atomisp_css_input_set_binning_factor(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
unsigned int bin_factor);
void atomisp_css_input_set_bayer_order(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_bayer_order bayer_order);
void atomisp_css_input_set_format(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_stream_format format);
int atomisp_css_input_set_effective_resolution(
struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
unsigned int width,
unsigned int height);
void atomisp_css_video_set_dis_envelope(struct atomisp_sub_device *asd,
unsigned int dvs_w, unsigned int dvs_h);
void atomisp_css_input_set_two_pixels_per_clock(
struct atomisp_sub_device *asd,
bool two_ppc);
void atomisp_css_enable_raw_binning(struct atomisp_sub_device *asd,
bool enable);
void atomisp_css_enable_dz(struct atomisp_sub_device *asd, bool enable);
void atomisp_css_capture_set_mode(struct atomisp_sub_device *asd,
enum atomisp_css_capture_mode mode);
void atomisp_css_input_set_mode(struct atomisp_sub_device *asd,
enum atomisp_css_input_mode mode);
void atomisp_css_capture_enable_online(struct atomisp_sub_device *asd,
unsigned short stream_index, bool enable);
void atomisp_css_preview_enable_online(struct atomisp_sub_device *asd,
unsigned short stream_index, bool enable);
void atomisp_css_video_enable_online(struct atomisp_sub_device *asd,
bool enable);
void atomisp_css_enable_continuous(struct atomisp_sub_device *asd,
bool enable);
void atomisp_css_enable_cvf(struct atomisp_sub_device *asd,
bool enable);
int atomisp_css_input_configure_port(struct atomisp_sub_device *asd,
mipi_port_ID_t port,
unsigned int num_lanes,
unsigned int timeout,
unsigned int mipi_freq,
enum atomisp_css_stream_format metadata_format,
unsigned int metadata_width,
unsigned int metadata_height);
int atomisp_css_frame_allocate(struct atomisp_css_frame **frame,
unsigned int width, unsigned int height,
enum atomisp_css_frame_format format,
unsigned int padded_width,
unsigned int raw_bit_depth);
int atomisp_css_frame_allocate_from_info(struct atomisp_css_frame **frame,
const struct atomisp_css_frame_info *info);
void atomisp_css_frame_free(struct atomisp_css_frame *frame);
int atomisp_css_frame_map(struct atomisp_css_frame **frame,
const struct atomisp_css_frame_info *info,
const void *data, uint16_t attribute,
void *context);
int atomisp_css_set_black_frame(struct atomisp_sub_device *asd,
const struct atomisp_css_frame *raw_black_frame);
int atomisp_css_allocate_continuous_frames(bool init_time,
struct atomisp_sub_device *asd);
void atomisp_css_update_continuous_frames(struct atomisp_sub_device *asd);
void atomisp_create_pipes_stream(struct atomisp_sub_device *asd);
void atomisp_destroy_pipes_stream_force(struct atomisp_sub_device *asd);
int atomisp_css_stop(struct atomisp_sub_device *asd,
enum atomisp_css_pipe_id pipe_id, bool in_reset);
int atomisp_css_continuous_set_num_raw_frames(
struct atomisp_sub_device *asd,
int num_frames);
void atomisp_css_disable_vf_pp(struct atomisp_sub_device *asd,
bool disable);
int atomisp_css_copy_configure_output(struct atomisp_sub_device *asd,
unsigned int stream_index,
unsigned int width, unsigned int height,
unsigned int padded_width,
enum atomisp_css_frame_format format);
int atomisp_css_yuvpp_configure_output(struct atomisp_sub_device *asd,
unsigned int stream_index,
unsigned int width, unsigned int height,
unsigned int padded_width,
enum atomisp_css_frame_format format);
int atomisp_css_yuvpp_configure_viewfinder(
struct atomisp_sub_device *asd,
unsigned int stream_index,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_yuvpp_get_output_frame_info(
struct atomisp_sub_device *asd,
unsigned int stream_index,
struct atomisp_css_frame_info *info);
int atomisp_css_yuvpp_get_viewfinder_frame_info(
struct atomisp_sub_device *asd,
unsigned int stream_index,
struct atomisp_css_frame_info *info);
int atomisp_css_preview_configure_output(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_capture_configure_output(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_video_configure_output(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_get_css_frame_info(struct atomisp_sub_device *asd,
uint16_t source_pad,
struct atomisp_css_frame_info *frame_info);
int atomisp_css_video_configure_viewfinder(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_capture_configure_viewfinder(
struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_video_get_viewfinder_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_capture_get_viewfinder_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_copy_get_output_frame_info(
struct atomisp_sub_device *asd,
unsigned int stream_index,
struct atomisp_css_frame_info *info);
int atomisp_css_capture_get_output_raw_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_preview_get_output_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_capture_get_output_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_video_get_output_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_preview_configure_pp_input(
struct atomisp_sub_device *asd,
unsigned int width, unsigned int height);
int atomisp_css_capture_configure_pp_input(
struct atomisp_sub_device *asd,
unsigned int width, unsigned int height);
int atomisp_css_video_configure_pp_input(
struct atomisp_sub_device *asd,
unsigned int width, unsigned int height);
int atomisp_css_offline_capture_configure(struct atomisp_sub_device *asd,
int num_captures, unsigned int skip, int offset);
int atomisp_css_exp_id_capture(struct atomisp_sub_device *asd, int exp_id);
int atomisp_css_exp_id_unlock(struct atomisp_sub_device *asd, int exp_id);
int atomisp_css_capture_enable_xnr(struct atomisp_sub_device *asd,
bool enable);
void atomisp_css_send_input_frame(struct atomisp_sub_device *asd,
unsigned short *data, unsigned int width,
unsigned int height);
bool atomisp_css_isp_has_started(void);
void atomisp_css_request_flash(struct atomisp_sub_device *asd);
void atomisp_css_set_wb_config(struct atomisp_sub_device *asd,
struct atomisp_css_wb_config *wb_config);
void atomisp_css_set_ob_config(struct atomisp_sub_device *asd,
struct atomisp_css_ob_config *ob_config);
void atomisp_css_set_dp_config(struct atomisp_sub_device *asd,
struct atomisp_css_dp_config *dp_config);
void atomisp_css_set_de_config(struct atomisp_sub_device *asd,
struct atomisp_css_de_config *de_config);
void atomisp_css_set_dz_config(struct atomisp_sub_device *asd,
struct atomisp_css_dz_config *dz_config);
void atomisp_css_set_default_de_config(struct atomisp_sub_device *asd);
void atomisp_css_set_ce_config(struct atomisp_sub_device *asd,
struct atomisp_css_ce_config *ce_config);
void atomisp_css_set_nr_config(struct atomisp_sub_device *asd,
struct atomisp_css_nr_config *nr_config);
void atomisp_css_set_ee_config(struct atomisp_sub_device *asd,
struct atomisp_css_ee_config *ee_config);
void atomisp_css_set_tnr_config(struct atomisp_sub_device *asd,
struct atomisp_css_tnr_config *tnr_config);
void atomisp_css_set_cc_config(struct atomisp_sub_device *asd,
struct atomisp_css_cc_config *cc_config);
void atomisp_css_set_macc_table(struct atomisp_sub_device *asd,
struct atomisp_css_macc_table *macc_table);
void atomisp_css_set_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_css_gamma_table *gamma_table);
void atomisp_css_set_ctc_table(struct atomisp_sub_device *asd,
struct atomisp_css_ctc_table *ctc_table);
void atomisp_css_set_gc_config(struct atomisp_sub_device *asd,
struct atomisp_css_gc_config *gc_config);
void atomisp_css_set_3a_config(struct atomisp_sub_device *asd,
struct atomisp_css_3a_config *s3a_config);
void atomisp_css_video_set_dis_vector(struct atomisp_sub_device *asd,
struct atomisp_dis_vector *vector);
void atomisp_css_set_dvs2_coefs(struct atomisp_sub_device *asd,
struct ia_css_dvs2_coefficients *coefs);
int atomisp_css_set_dis_coefs(struct atomisp_sub_device *asd,
struct atomisp_dis_coefficients *coefs);
void atomisp_css_set_zoom_factor(struct atomisp_sub_device *asd,
unsigned int zoom);
int atomisp_css_get_wb_config(struct atomisp_sub_device *asd,
struct atomisp_wb_config *config);
int atomisp_css_get_ob_config(struct atomisp_sub_device *asd,
struct atomisp_ob_config *config);
int atomisp_css_get_dp_config(struct atomisp_sub_device *asd,
struct atomisp_dp_config *config);
int atomisp_css_get_de_config(struct atomisp_sub_device *asd,
struct atomisp_de_config *config);
int atomisp_css_get_nr_config(struct atomisp_sub_device *asd,
struct atomisp_nr_config *config);
int atomisp_css_get_ee_config(struct atomisp_sub_device *asd,
struct atomisp_ee_config *config);
int atomisp_css_get_tnr_config(struct atomisp_sub_device *asd,
struct atomisp_tnr_config *config);
int atomisp_css_get_ctc_table(struct atomisp_sub_device *asd,
struct atomisp_ctc_table *config);
int atomisp_css_get_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_gamma_table *config);
int atomisp_css_get_gc_config(struct atomisp_sub_device *asd,
struct atomisp_gc_config *config);
int atomisp_css_get_3a_config(struct atomisp_sub_device *asd,
struct atomisp_3a_config *config);
int atomisp_css_get_formats_config(struct atomisp_sub_device *asd,
struct atomisp_formats_config *formats_config);
void atomisp_css_set_formats_config(struct atomisp_sub_device *asd,
struct atomisp_css_formats_config *formats_config);
int atomisp_css_get_zoom_factor(struct atomisp_sub_device *asd,
unsigned int *zoom);
struct atomisp_css_shading_table *atomisp_css_shading_table_alloc(
unsigned int width, unsigned int height);
void atomisp_css_set_shading_table(struct atomisp_sub_device *asd,
struct atomisp_css_shading_table *table);
void atomisp_css_shading_table_free(struct atomisp_css_shading_table *table);
struct atomisp_css_morph_table *atomisp_css_morph_table_allocate(
unsigned int width, unsigned int height);
void atomisp_css_set_morph_table(struct atomisp_sub_device *asd,
struct atomisp_css_morph_table *table);
void atomisp_css_get_morph_table(struct atomisp_sub_device *asd,
struct atomisp_css_morph_table *table);
void atomisp_css_morph_table_free(struct atomisp_css_morph_table *table);
void atomisp_css_set_cont_prev_start_time(struct atomisp_device *isp,
unsigned int overlap);
int atomisp_css_get_dis_stat(struct atomisp_sub_device *asd,
struct atomisp_dis_statistics *stats);
int atomisp_css_update_stream(struct atomisp_sub_device *asd);
int atomisp_css_create_acc_pipe(struct atomisp_sub_device *asd);
int atomisp_css_start_acc_pipe(struct atomisp_sub_device *asd);
int atomisp_css_stop_acc_pipe(struct atomisp_sub_device *asd);
void atomisp_css_destroy_acc_pipe(struct atomisp_sub_device *asd);
int atomisp_css_load_acc_extension(struct atomisp_sub_device *asd,
struct atomisp_css_fw_info *fw,
enum atomisp_css_pipe_id pipe_id,
unsigned int type);
void atomisp_css_unload_acc_extension(struct atomisp_sub_device *asd,
struct atomisp_css_fw_info *fw,
enum atomisp_css_pipe_id pipe_id);
int atomisp_css_wait_acc_finish(struct atomisp_sub_device *asd);
void atomisp_css_acc_done(struct atomisp_sub_device *asd);
int atomisp_css_load_acc_binary(struct atomisp_sub_device *asd,
struct atomisp_css_fw_info *fw,
unsigned int index);
void atomisp_css_unload_acc_binary(struct atomisp_sub_device *asd);
struct atomisp_acc_fw;
int atomisp_css_set_acc_parameters(struct atomisp_acc_fw *acc_fw);
int atomisp_css_isr_thread(struct atomisp_device *isp,
bool *frame_done_found,
bool *css_pipe_done);
void atomisp_set_stop_timeout(unsigned int timeout);
bool atomisp_css_valid_sof(struct atomisp_device *isp);
void atomisp_en_dz_capt_pipe(struct atomisp_sub_device *asd, bool enable);
#endif

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/*
* Support for Clovertrail PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_COMPAT_CSS20_H__
#define __ATOMISP_COMPAT_CSS20_H__
#include <media/v4l2-mediabus.h>
#include "ia_css.h"
#include "ia_css_types.h"
#include "ia_css_acc_types.h"
#include "sh_css_legacy.h"
#define ATOMISP_CSS2_PIPE_MAX 2
#define ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES 3
#define ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES_LOCK_EN 4
#define ATOMISP_CSS2_NUM_DVS_FRAME_DELAY 2
#define atomisp_css_pipe_id ia_css_pipe_id
#define atomisp_css_pipeline ia_css_pipe
#define atomisp_css_buffer_type ia_css_buffer_type
#define atomisp_css_dis_data ia_css_isp_dvs_statistics
#define atomisp_css_irq_info ia_css_irq_info
#define atomisp_css_isp_config ia_css_isp_config
#define atomisp_css_bayer_order ia_css_bayer_order
#define atomisp_css_stream_format ia_css_stream_format
#define atomisp_css_capture_mode ia_css_capture_mode
#define atomisp_css_input_mode ia_css_input_mode
#define atomisp_css_frame ia_css_frame
#define atomisp_css_frame_format ia_css_frame_format
#define atomisp_css_frame_info ia_css_frame_info
#define atomisp_css_dp_config ia_css_dp_config
#define atomisp_css_wb_config ia_css_wb_config
#define atomisp_css_cc_config ia_css_cc_config
#define atomisp_css_nr_config ia_css_nr_config
#define atomisp_css_ee_config ia_css_ee_config
#define atomisp_css_ob_config ia_css_ob_config
#define atomisp_css_de_config ia_css_de_config
#define atomisp_css_dz_config ia_css_dz_config
#define atomisp_css_ce_config ia_css_ce_config
#define atomisp_css_gc_config ia_css_gc_config
#define atomisp_css_tnr_config ia_css_tnr_config
#define atomisp_css_cnr_config ia_css_cnr_config
#define atomisp_css_ctc_config ia_css_ctc_config
#define atomisp_css_3a_config ia_css_3a_config
#define atomisp_css_ecd_config ia_css_ecd_config
#define atomisp_css_ynr_config ia_css_ynr_config
#define atomisp_css_fc_config ia_css_fc_config
#define atomisp_css_aa_config ia_css_aa_config
#define atomisp_css_baa_config ia_css_aa_config
#define atomisp_css_anr_config ia_css_anr_config
#define atomisp_css_xnr_config ia_css_xnr_config
#define atomisp_css_macc_config ia_css_macc_config
#define atomisp_css_gamma_table ia_css_gamma_table
#define atomisp_css_ctc_table ia_css_ctc_table
#define atomisp_css_macc_table ia_css_macc_table
#define atomisp_css_xnr_table ia_css_xnr_table
#define atomisp_css_rgb_gamma_table ia_css_rgb_gamma_table
#define atomisp_css_anr_thres ia_css_anr_thres
#define atomisp_css_dvs_6axis ia_css_dvs_6axis_config
#define atomisp_css_grid_info ia_css_grid_info
#define atomisp_css_3a_grid_info ia_css_3a_grid_info
#define atomisp_css_dvs_grid_info ia_css_dvs_grid_info
#define atomisp_css_shading_table ia_css_shading_table
#define atomisp_css_morph_table ia_css_morph_table
#define atomisp_css_dvs_6axis_config ia_css_dvs_6axis_config
#define atomisp_css_fw_info ia_css_fw_info
#define atomisp_css_formats_config ia_css_formats_config
#define CSS_PIPE_ID_PREVIEW IA_CSS_PIPE_ID_PREVIEW
#define CSS_PIPE_ID_COPY IA_CSS_PIPE_ID_COPY
#define CSS_PIPE_ID_VIDEO IA_CSS_PIPE_ID_VIDEO
#define CSS_PIPE_ID_CAPTURE IA_CSS_PIPE_ID_CAPTURE
#define CSS_PIPE_ID_ACC IA_CSS_PIPE_ID_ACC
#define CSS_PIPE_ID_YUVPP IA_CSS_PIPE_ID_YUVPP
#define CSS_PIPE_ID_NUM IA_CSS_PIPE_ID_NUM
#define CSS_INPUT_MODE_SENSOR IA_CSS_INPUT_MODE_BUFFERED_SENSOR
#define CSS_INPUT_MODE_FIFO IA_CSS_INPUT_MODE_FIFO
#define CSS_INPUT_MODE_TPG IA_CSS_INPUT_MODE_TPG
#define CSS_INPUT_MODE_PRBS IA_CSS_INPUT_MODE_PRBS
#define CSS_INPUT_MODE_MEMORY IA_CSS_INPUT_MODE_MEMORY
#define CSS_IRQ_INFO_CSS_RECEIVER_ERROR IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR
#define CSS_IRQ_INFO_EVENTS_READY IA_CSS_IRQ_INFO_EVENTS_READY
#define CSS_IRQ_INFO_INPUT_SYSTEM_ERROR \
IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR
#define CSS_IRQ_INFO_IF_ERROR IA_CSS_IRQ_INFO_IF_ERROR
#define CSS_BUFFER_TYPE_NUM IA_CSS_BUFFER_TYPE_NUM
#define CSS_FRAME_FLASH_STATE_NONE IA_CSS_FRAME_FLASH_STATE_NONE
#define CSS_FRAME_FLASH_STATE_PARTIAL IA_CSS_FRAME_FLASH_STATE_PARTIAL
#define CSS_FRAME_FLASH_STATE_FULL IA_CSS_FRAME_FLASH_STATE_FULL
#define CSS_BAYER_ORDER_GRBG IA_CSS_BAYER_ORDER_GRBG
#define CSS_BAYER_ORDER_RGGB IA_CSS_BAYER_ORDER_RGGB
#define CSS_BAYER_ORDER_BGGR IA_CSS_BAYER_ORDER_BGGR
#define CSS_BAYER_ORDER_GBRG IA_CSS_BAYER_ORDER_GBRG
/*
* Hide IA_ naming difference in otherwise common CSS macros.
*/
#define CSS_ID(val) (IA_ ## val)
#define CSS_EVENT(val) (IA_CSS_EVENT_TYPE_ ## val)
#define CSS_FORMAT(val) (IA_CSS_STREAM_FORMAT_ ## val)
#define CSS_EVENT_PORT_EOF CSS_EVENT(PORT_EOF)
#define CSS_EVENT_FRAME_TAGGED CSS_EVENT(FRAME_TAGGED)
#define CSS_MIPI_FRAME_BUFFER_SIZE_1 0x60000
#define CSS_MIPI_FRAME_BUFFER_SIZE_2 0x80000
struct atomisp_device;
struct atomisp_sub_device;
#define MAX_STREAMS_PER_CHANNEL 2
/*
* These are used to indicate the css stream state, corresponding
* stream handling can be done via judging the different state.
*/
enum atomisp_css_stream_state {
CSS_STREAM_UNINIT,
CSS_STREAM_CREATED,
CSS_STREAM_STARTED,
CSS_STREAM_STOPPED,
};
/*
* Sensor of external ISP can send multiple steams with different mipi data
* type in the same virtual channel. This information needs to come from the
* sensor or external ISP
*/
struct atomisp_css_isys_config_info {
unsigned int input_format;
unsigned int width;
unsigned int height;
};
struct atomisp_stream_env {
struct ia_css_stream *stream;
struct ia_css_stream_config stream_config;
struct ia_css_stream_info stream_info;
struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM];
struct ia_css_pipe *multi_pipes[IA_CSS_PIPE_ID_NUM];
struct ia_css_pipe_config pipe_configs[IA_CSS_PIPE_ID_NUM];
struct ia_css_pipe_extra_config pipe_extra_configs[IA_CSS_PIPE_ID_NUM];
bool update_pipe[IA_CSS_PIPE_ID_NUM];
enum atomisp_css_stream_state stream_state;
struct ia_css_stream *acc_stream;
enum atomisp_css_stream_state acc_stream_state;
struct ia_css_stream_config acc_stream_config;
unsigned int ch_id; /* virtual channel ID */
unsigned int isys_configs;
struct atomisp_css_isys_config_info isys_info[MAX_STREAMS_PER_CHANNEL];
};
struct atomisp_css_env {
struct ia_css_env isp_css_env;
struct ia_css_fw isp_css_fw;
};
struct atomisp_s3a_buf {
struct ia_css_isp_3a_statistics *s3a_data;
struct ia_css_isp_3a_statistics_map *s3a_map;
struct list_head list;
};
struct atomisp_dis_buf {
struct atomisp_css_dis_data *dis_data;
struct ia_css_isp_dvs_statistics_map *dvs_map;
struct list_head list;
};
struct atomisp_css_buffer {
struct ia_css_buffer css_buffer;
};
struct atomisp_css_event {
enum atomisp_css_pipe_id pipe;
struct ia_css_event event;
};
void atomisp_css_set_macc_config(struct atomisp_sub_device *asd,
struct atomisp_css_macc_config *macc_config);
void atomisp_css_set_ecd_config(struct atomisp_sub_device *asd,
struct atomisp_css_ecd_config *ecd_config);
void atomisp_css_set_ynr_config(struct atomisp_sub_device *asd,
struct atomisp_css_ynr_config *ynr_config);
void atomisp_css_set_fc_config(struct atomisp_sub_device *asd,
struct atomisp_css_fc_config *fc_config);
void atomisp_css_set_aa_config(struct atomisp_sub_device *asd,
struct atomisp_css_aa_config *aa_config);
void atomisp_css_set_baa_config(struct atomisp_sub_device *asd,
struct atomisp_css_baa_config *baa_config);
void atomisp_css_set_anr_config(struct atomisp_sub_device *asd,
struct atomisp_css_anr_config *anr_config);
void atomisp_css_set_xnr_config(struct atomisp_sub_device *asd,
struct atomisp_css_xnr_config *xnr_config);
void atomisp_css_set_cnr_config(struct atomisp_sub_device *asd,
struct atomisp_css_cnr_config *cnr_config);
void atomisp_css_set_ctc_config(struct atomisp_sub_device *asd,
struct atomisp_css_ctc_config *ctc_config);
void atomisp_css_set_yuv2rgb_cc_config(struct atomisp_sub_device *asd,
struct atomisp_css_cc_config *yuv2rgb_cc_config);
void atomisp_css_set_rgb2yuv_cc_config(struct atomisp_sub_device *asd,
struct atomisp_css_cc_config *rgb2yuv_cc_config);
void atomisp_css_set_xnr_table(struct atomisp_sub_device *asd,
struct atomisp_css_xnr_table *xnr_table);
void atomisp_css_set_r_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_css_rgb_gamma_table *r_gamma_table);
void atomisp_css_set_g_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_css_rgb_gamma_table *g_gamma_table);
void atomisp_css_set_b_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_css_rgb_gamma_table *b_gamma_table);
void atomisp_css_set_anr_thres(struct atomisp_sub_device *asd,
struct atomisp_css_anr_thres *anr_thres);
int atomisp_css_check_firmware_version(struct atomisp_device *isp);
int atomisp_css_load_firmware(struct atomisp_device *isp);
void atomisp_css_unload_firmware(struct atomisp_device *isp);
void atomisp_css_set_dvs_6axis(struct atomisp_sub_device *asd,
struct atomisp_css_dvs_6axis *dvs_6axis);
unsigned int atomisp_css_debug_get_dtrace_level(void);
int atomisp_css_debug_dump_isp_binary(void);
int atomisp_css_dump_sp_raw_copy_linecount(bool reduced);
int atomisp_css_dump_blob_infor(void);
void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd,
uint32_t isp_config_id);
void atomisp_css_set_isp_config_applied_frame(struct atomisp_sub_device *asd,
struct atomisp_css_frame *output_frame);
int atomisp_get_css_dbgfunc(void);
int atomisp_set_css_dbgfunc(struct atomisp_device *isp, int opt);
struct atomisp_css_dvs_grid_info *atomisp_css_get_dvs_grid_info(
struct atomisp_css_grid_info *grid_info);
#endif

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/*
* Support for Intel Camera Imaging ISP subsystem.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_COMPAT_IOCTL32_H__
#define __ATOMISP_COMPAT_IOCTL32_H__
#include <linux/compat.h>
#include <linux/videodev2.h>
#include "atomisp_compat.h"
struct atomisp_histogram32 {
unsigned int num_elements;
compat_uptr_t data;
};
struct atomisp_dvs2_stat_types32 {
compat_uptr_t odd_real; /**< real part of the odd statistics*/
compat_uptr_t odd_imag; /**< imaginary part of the odd statistics*/
compat_uptr_t even_real;/**< real part of the even statistics*/
compat_uptr_t even_imag;/**< imaginary part of the even statistics*/
};
struct atomisp_dvs2_coef_types32 {
compat_uptr_t odd_real; /**< real part of the odd coefficients*/
compat_uptr_t odd_imag; /**< imaginary part of the odd coefficients*/
compat_uptr_t even_real;/**< real part of the even coefficients*/
compat_uptr_t even_imag;/**< imaginary part of the even coefficients*/
};
struct atomisp_dvs2_statistics32 {
struct atomisp_dvs_grid_info grid_info;
struct atomisp_dvs2_stat_types32 hor_prod;
struct atomisp_dvs2_stat_types32 ver_prod;
};
struct atomisp_dis_statistics32 {
struct atomisp_dvs2_statistics32 dvs2_stat;
uint32_t exp_id;
};
struct atomisp_dis_coefficients32 {
struct atomisp_dvs_grid_info grid_info;
struct atomisp_dvs2_coef_types32 hor_coefs;
struct atomisp_dvs2_coef_types32 ver_coefs;
};
struct atomisp_3a_statistics32 {
struct atomisp_grid_info grid_info;
compat_uptr_t data;
compat_uptr_t rgby_data;
uint32_t exp_id;
uint32_t isp_config_id;
};
struct atomisp_metadata_with_type32 {
/* to specify which type of metadata to get */
enum atomisp_metadata_type type;
compat_uptr_t data;
uint32_t width;
uint32_t height;
uint32_t stride; /* in bytes */
uint32_t exp_id; /* exposure ID */
compat_uptr_t effective_width;
};
struct atomisp_metadata32 {
compat_uptr_t data;
uint32_t width;
uint32_t height;
uint32_t stride;
uint32_t exp_id;
compat_uptr_t effective_width;
};
struct atomisp_morph_table32 {
unsigned int enabled;
unsigned int height;
unsigned int width; /* number of valid elements per line */
compat_uptr_t coordinates_x[ATOMISP_MORPH_TABLE_NUM_PLANES];
compat_uptr_t coordinates_y[ATOMISP_MORPH_TABLE_NUM_PLANES];
};
struct v4l2_framebuffer32 {
__u32 capability;
__u32 flags;
compat_uptr_t base;
struct v4l2_pix_format fmt;
};
struct atomisp_overlay32 {
/* the frame containing the overlay data The overlay frame width should
* be the multiples of 2*ISP_VEC_NELEMS. The overlay frame height
* should be the multiples of 2.
*/
compat_uptr_t frame;
/* Y value of overlay background */
unsigned char bg_y;
/* U value of overlay background */
char bg_u;
/* V value of overlay background */
char bg_v;
/* the blending percent of input data for Y subpixels */
unsigned char blend_input_perc_y;
/* the blending percent of input data for U subpixels */
unsigned char blend_input_perc_u;
/* the blending percent of input data for V subpixels */
unsigned char blend_input_perc_v;
/* the blending percent of overlay data for Y subpixels */
unsigned char blend_overlay_perc_y;
/* the blending percent of overlay data for U subpixels */
unsigned char blend_overlay_perc_u;
/* the blending percent of overlay data for V subpixels */
unsigned char blend_overlay_perc_v;
/* the overlay start x pixel position on output frame It should be the
multiples of 2*ISP_VEC_NELEMS. */
unsigned int overlay_start_x;
/* the overlay start y pixel position on output frame It should be the
multiples of 2. */
unsigned int overlay_start_y;
};
struct atomisp_calibration_group32 {
unsigned int size;
unsigned int type;
compat_uptr_t calb_grp_values;
};
struct atomisp_acc_fw_load32 {
unsigned int size;
unsigned int fw_handle;
compat_uptr_t data;
};
struct atomisp_acc_fw_arg32 {
unsigned int fw_handle;
unsigned int index;
compat_uptr_t value;
compat_size_t size;
};
struct v4l2_private_int_data32 {
__u32 size;
compat_uptr_t data;
__u32 reserved[2];
};
struct atomisp_shading_table32 {
__u32 enable;
__u32 sensor_width;
__u32 sensor_height;
__u32 width;
__u32 height;
__u32 fraction_bits;
compat_uptr_t data[ATOMISP_NUM_SC_COLORS];
};
struct atomisp_acc_map32 {
__u32 flags; /* Flags, see list below */
__u32 length; /* Length of data in bytes */
compat_uptr_t user_ptr; /* Pointer into user space */
compat_ulong_t css_ptr; /* Pointer into CSS address space */
__u32 reserved[4]; /* Set to zero */
};
struct atomisp_acc_s_mapped_arg32 {
unsigned int fw_handle;
__u32 memory; /* one of enum atomisp_acc_memory */
compat_size_t length;
compat_ulong_t css_ptr;
};
struct atomisp_parameters32 {
compat_uptr_t wb_config; /* White Balance config */
compat_uptr_t cc_config; /* Color Correction config */
compat_uptr_t tnr_config; /* Temporal Noise Reduction */
compat_uptr_t ecd_config; /* Eigen Color Demosaicing */
compat_uptr_t ynr_config; /* Y(Luma) Noise Reduction */
compat_uptr_t fc_config; /* Fringe Control */
compat_uptr_t formats_config; /* Formats Control */
compat_uptr_t cnr_config; /* Chroma Noise Reduction */
compat_uptr_t macc_config; /* MACC */
compat_uptr_t ctc_config; /* Chroma Tone Control */
compat_uptr_t aa_config; /* Anti-Aliasing */
compat_uptr_t baa_config; /* Anti-Aliasing */
compat_uptr_t ce_config;
compat_uptr_t dvs_6axis_config;
compat_uptr_t ob_config; /* Objective Black config */
compat_uptr_t dp_config; /* Dead Pixel config */
compat_uptr_t nr_config; /* Noise Reduction config */
compat_uptr_t ee_config; /* Edge Enhancement config */
compat_uptr_t de_config; /* Demosaic config */
compat_uptr_t gc_config; /* Gamma Correction config */
compat_uptr_t anr_config; /* Advanced Noise Reduction */
compat_uptr_t a3a_config; /* 3A Statistics config */
compat_uptr_t xnr_config; /* eXtra Noise Reduction */
compat_uptr_t dz_config; /* Digital Zoom */
compat_uptr_t yuv2rgb_cc_config; /* Color
Correction config */
compat_uptr_t rgb2yuv_cc_config; /* Color
Correction config */
compat_uptr_t macc_table;
compat_uptr_t gamma_table;
compat_uptr_t ctc_table;
compat_uptr_t xnr_table;
compat_uptr_t r_gamma_table;
compat_uptr_t g_gamma_table;
compat_uptr_t b_gamma_table;
compat_uptr_t motion_vector; /* For 2-axis DVS */
compat_uptr_t shading_table;
compat_uptr_t morph_table;
compat_uptr_t dvs_coefs; /* DVS 1.0 coefficients */
compat_uptr_t dvs2_coefs; /* DVS 2.0 coefficients */
compat_uptr_t capture_config;
compat_uptr_t anr_thres;
compat_uptr_t lin_2500_config; /* Skylake: Linearization config */
compat_uptr_t obgrid_2500_config; /* Skylake: OBGRID config */
compat_uptr_t bnr_2500_config; /* Skylake: bayer denoise config */
compat_uptr_t shd_2500_config; /* Skylake: shading config */
compat_uptr_t dm_2500_config; /* Skylake: demosaic config */
compat_uptr_t rgbpp_2500_config; /* Skylake: RGBPP config */
compat_uptr_t dvs_stat_2500_config; /* Skylake: DVS STAT config */
compat_uptr_t lace_stat_2500_config; /* Skylake: LACE STAT config */
compat_uptr_t yuvp1_2500_config; /* Skylake: yuvp1 config */
compat_uptr_t yuvp2_2500_config; /* Skylake: yuvp2 config */
compat_uptr_t tnr_2500_config; /* Skylake: TNR config */
compat_uptr_t dpc_2500_config; /* Skylake: DPC config */
compat_uptr_t awb_2500_config; /* Skylake: auto white balance config */
compat_uptr_t awb_fr_2500_config; /* Skylake: auto white balance filter response config */
compat_uptr_t anr_2500_config; /* Skylake: ANR config */
compat_uptr_t af_2500_config; /* Skylake: auto focus config */
compat_uptr_t ae_2500_config; /* Skylake: auto exposure config */
compat_uptr_t bds_2500_config; /* Skylake: bayer downscaler config */
compat_uptr_t dvs_2500_config; /* Skylake: digital video stabilization config */
compat_uptr_t res_mgr_2500_config;
/*
* Output frame pointer the config is to be applied to (optional),
* set to NULL to make this config is applied as global.
*/
compat_uptr_t output_frame;
/*
* Unique ID to track which config was actually applied to a particular
* frame, driver will send this id back with output frame together.
*/
uint32_t isp_config_id;
uint32_t per_frame_setting;
};
struct atomisp_acc_fw_load_to_pipe32 {
__u32 flags; /* Flags, see below for valid values */
unsigned int fw_handle; /* Handle, filled by kernel. */
__u32 size; /* Firmware binary size */
compat_uptr_t data; /* Pointer to firmware */
__u32 type; /* Binary type */
__u32 reserved[3]; /* Set to zero */
};
struct atomisp_dvs_6axis_config32 {
uint32_t exp_id;
uint32_t width_y;
uint32_t height_y;
uint32_t width_uv;
uint32_t height_uv;
compat_uptr_t xcoords_y;
compat_uptr_t ycoords_y;
compat_uptr_t xcoords_uv;
compat_uptr_t ycoords_uv;
};
struct atomisp_sensor_ae_bracketing_lut32 {
compat_uptr_t lut;
unsigned int lut_size;
};
#define ATOMISP_IOC_G_HISTOGRAM32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram32)
#define ATOMISP_IOC_S_HISTOGRAM32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram32)
#define ATOMISP_IOC_G_DIS_STAT32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_statistics32)
#define ATOMISP_IOC_S_DIS_COEFS32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_coefficients32)
#define ATOMISP_IOC_S_DIS_VECTOR32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dvs_6axis_config32)
#define ATOMISP_IOC_G_3A_STAT32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 7, struct atomisp_3a_statistics32)
#define ATOMISP_IOC_G_ISP_GDC_TAB32 \
_IOR('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table32)
#define ATOMISP_IOC_S_ISP_GDC_TAB32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table32)
#define ATOMISP_IOC_S_ISP_FPN_TABLE32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 17, struct v4l2_framebuffer32)
#define ATOMISP_IOC_G_ISP_OVERLAY32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay32)
#define ATOMISP_IOC_S_ISP_OVERLAY32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay32)
#define ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 22, struct atomisp_calibration_group32)
#define ATOMISP_IOC_ACC_LOAD32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 24, struct atomisp_acc_fw_load32)
#define ATOMISP_IOC_ACC_S_ARG32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 24, struct atomisp_acc_fw_arg32)
#define ATOMISP_IOC_ACC_DESTAB32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 25, struct atomisp_acc_fw_arg32)
#define ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 26, struct v4l2_private_int_data32)
#define ATOMISP_IOC_S_ISP_SHD_TAB32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 27, struct atomisp_shading_table32)
#define ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 29, struct v4l2_private_int_data32)
#define ATOMISP_IOC_ACC_MAP32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_map32)
#define ATOMISP_IOC_ACC_UNMAP32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_map32)
#define ATOMISP_IOC_ACC_S_MAPPED_ARG32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_s_mapped_arg32)
#define ATOMISP_IOC_ACC_LOAD_TO_PIPE32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 31, struct atomisp_acc_fw_load_to_pipe32)
#define ATOMISP_IOC_S_PARAMETERS32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 32, struct atomisp_parameters32)
#define ATOMISP_IOC_G_METADATA32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata32)
#define ATOMISP_IOC_G_METADATA_BY_TYPE32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata_with_type32)
#define ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 43, struct atomisp_sensor_ae_bracketing_lut32)
#endif /* __ATOMISP_COMPAT_IOCTL32_H__ */

446
drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.c Normal file
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@ -0,0 +1,446 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <media/v4l2-event.h>
#include <media/v4l2-mediabus.h>
#include "atomisp_cmd.h"
#include "atomisp_internal.h"
#include "atomisp-regs.h"
static struct v4l2_mbus_framefmt *__csi2_get_format(struct
atomisp_mipi_csi2_device
*csi2,
struct
v4l2_subdev_pad_config *cfg,
enum
v4l2_subdev_format_whence
which, unsigned int pad)
{
if (which == V4L2_SUBDEV_FORMAT_TRY)
return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
else
return &csi2->formats[pad];
}
/*
* csi2_enum_mbus_code - Handle pixel format enumeration
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @code : pointer to v4l2_subdev_pad_mbus_code_enum structure
* return -EINVAL or zero on success
*/
static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
const struct atomisp_in_fmt_conv *ic = atomisp_in_fmt_conv;
unsigned int i = 0;
while (ic->code) {
if (i == code->index) {
code->code = ic->code;
return 0;
}
i++, ic++;
}
return -EINVAL;
}
/*
* csi2_get_format - Handle get format by pads subdev method
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @pad: pad num
* @fmt: pointer to v4l2 format structure
* return -EINVAL or zero on sucess
*/
static int csi2_get_format(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *fmt)
{
struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *format;
format = __csi2_get_format(csi2, cfg, fmt->which, fmt->pad);
fmt->format = *format;
return 0;
}
int atomisp_csi2_set_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
unsigned int which, uint16_t pad,
struct v4l2_mbus_framefmt *ffmt)
{
struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *actual_ffmt =
#ifndef ISP2401
__csi2_get_format(csi2, cfg, which, pad);
#else
__csi2_get_format(csi2, cfg, which, pad);
#endif
if (pad == CSI2_PAD_SINK) {
const struct atomisp_in_fmt_conv *ic;
struct v4l2_mbus_framefmt tmp_ffmt;
ic = atomisp_find_in_fmt_conv(ffmt->code);
if (ic)
actual_ffmt->code = ic->code;
else
actual_ffmt->code = atomisp_in_fmt_conv[0].code;
actual_ffmt->width = clamp_t(
u32, ffmt->width, ATOM_ISP_MIN_WIDTH,
ATOM_ISP_MAX_WIDTH);
actual_ffmt->height = clamp_t(
u32, ffmt->height, ATOM_ISP_MIN_HEIGHT,
ATOM_ISP_MAX_HEIGHT);
tmp_ffmt = *ffmt = *actual_ffmt;
return atomisp_csi2_set_ffmt(sd, cfg, which, CSI2_PAD_SOURCE,
&tmp_ffmt);
}
/* FIXME: DPCM decompression */
*actual_ffmt = *ffmt =
#ifndef ISP2401
*__csi2_get_format(csi2, cfg, which, CSI2_PAD_SINK);
#else
*__csi2_get_format(csi2, cfg, which, CSI2_PAD_SINK);
#endif
return 0;
}
/*
* csi2_set_format - Handle set format by pads subdev method
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @pad: pad num
* @fmt: pointer to v4l2 format structure
* return -EINVAL or zero on success
*/
static int csi2_set_format(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *fmt)
{
return atomisp_csi2_set_ffmt(sd, cfg, fmt->which, fmt->pad,
&fmt->format);
}
/*
* csi2_set_stream - Enable/Disable streaming on the CSI2 module
* @sd: ISP CSI2 V4L2 subdevice
* @enable: Enable/disable stream (1/0)
*
* Return 0 on success or a negative error code otherwise.
*/
static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
{
return 0;
}
/* subdev core operations */
static const struct v4l2_subdev_core_ops csi2_core_ops = {
};
/* subdev video operations */
static const struct v4l2_subdev_video_ops csi2_video_ops = {
.s_stream = csi2_set_stream,
};
/* subdev pad operations */
static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
.enum_mbus_code = csi2_enum_mbus_code,
.get_fmt = csi2_get_format,
.set_fmt = csi2_set_format,
.link_validate = v4l2_subdev_link_validate_default,
};
/* subdev operations */
static const struct v4l2_subdev_ops csi2_ops = {
.core = &csi2_core_ops,
.video = &csi2_video_ops,
.pad = &csi2_pad_ops,
};
#ifndef ISP2401
#endif
/*
* csi2_link_setup - Setup CSI2 connections.
* @entity : Pointer to media entity structure
* @local : Pointer to local pad array
* @remote : Pointer to remote pad array
* @flags : Link flags
* return -EINVAL or zero on success
*/
static int csi2_link_setup(struct media_entity *entity,
const struct media_pad *local,
const struct media_pad *remote, u32 flags)
{
struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd);
u32 result = local->index | is_media_entity_v4l2_subdev(remote->entity);
switch (result) {
case CSI2_PAD_SOURCE | MEDIA_ENT_F_OLD_BASE:
/* not supported yet */
return -EINVAL;
case CSI2_PAD_SOURCE | MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN:
if (flags & MEDIA_LNK_FL_ENABLED) {
if (csi2->output & ~CSI2_OUTPUT_ISP_SUBDEV)
return -EBUSY;
csi2->output |= CSI2_OUTPUT_ISP_SUBDEV;
} else {
csi2->output &= ~CSI2_OUTPUT_ISP_SUBDEV;
}
break;
default:
/* Link from camera to CSI2 is fixed... */
return -EINVAL;
}
return 0;
}
/* media operations */
static const struct media_entity_operations csi2_media_ops = {
.link_setup = csi2_link_setup,
.link_validate = v4l2_subdev_link_validate,
};
/*
* ispcsi2_init_entities - Initialize subdev and media entity.
* @csi2: Pointer to ispcsi2 structure.
* return -ENOMEM or zero on success
*/
static int mipi_csi2_init_entities(struct atomisp_mipi_csi2_device *csi2,
int port)
{
struct v4l2_subdev *sd = &csi2->subdev;
struct media_pad *pads = csi2->pads;
struct media_entity *me = &sd->entity;
int ret;
v4l2_subdev_init(sd, &csi2_ops);
snprintf(sd->name, sizeof(sd->name), "ATOM ISP CSI2-port%d", port);
v4l2_set_subdevdata(sd, csi2);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
me->ops = &csi2_media_ops;
me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads);
if (ret < 0)
return ret;
csi2->formats[CSI2_PAD_SINK].code =
csi2->formats[CSI2_PAD_SOURCE].code =
atomisp_in_fmt_conv[0].code;
return 0;
}
void
atomisp_mipi_csi2_unregister_entities(struct atomisp_mipi_csi2_device *csi2)
{
media_entity_cleanup(&csi2->subdev.entity);
v4l2_device_unregister_subdev(&csi2->subdev);
}
int atomisp_mipi_csi2_register_entities(struct atomisp_mipi_csi2_device *csi2,
struct v4l2_device *vdev)
{
int ret;
/* Register the subdev and video nodes. */
ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
if (ret < 0)
goto error;
return 0;
error:
atomisp_mipi_csi2_unregister_entities(csi2);
return ret;
}
static const int LIMIT_SHIFT = 6; /* Limit numeric range into 31 bits */
static int
atomisp_csi2_configure_calc(const short int coeffs[2], int mipi_freq, int def)
{
/* Delay counter accuracy, 1/0.0625 for ANN/CHT, 1/0.125 for BXT */
static const int accinv = 16; /* 1 / COUNT_ACC */
int r;
if (mipi_freq >> LIMIT_SHIFT <= 0)
return def;
r = accinv * coeffs[1] * (500000000 >> LIMIT_SHIFT);
r /= mipi_freq >> LIMIT_SHIFT;
r += accinv * coeffs[0];
return r;
}
static void atomisp_csi2_configure_isp2401(struct atomisp_sub_device *asd)
{
/*
* The ISP2401 new input system CSI2+ receiver has several
* parameters affecting the receiver timings. These depend
* on the MIPI bus frequency F in Hz (sensor transmitter rate)
* as follows:
* register value = (A/1e9 + B * UI) / COUNT_ACC
* where
* UI = 1 / (2 * F) in seconds
* COUNT_ACC = counter accuracy in seconds
* For ANN and CHV, COUNT_ACC = 0.0625 ns
* For BXT, COUNT_ACC = 0.125 ns
* A and B are coefficients from the table below,
* depending whether the register minimum or maximum value is
* calculated.
* Minimum Maximum
* Clock lane A B A B
* reg_rx_csi_dly_cnt_termen_clane 0 0 38 0
* reg_rx_csi_dly_cnt_settle_clane 95 -8 300 -16
* Data lanes
* reg_rx_csi_dly_cnt_termen_dlane0 0 0 35 4
* reg_rx_csi_dly_cnt_settle_dlane0 85 -2 145 -6
* reg_rx_csi_dly_cnt_termen_dlane1 0 0 35 4
* reg_rx_csi_dly_cnt_settle_dlane1 85 -2 145 -6
* reg_rx_csi_dly_cnt_termen_dlane2 0 0 35 4
* reg_rx_csi_dly_cnt_settle_dlane2 85 -2 145 -6
* reg_rx_csi_dly_cnt_termen_dlane3 0 0 35 4
* reg_rx_csi_dly_cnt_settle_dlane3 85 -2 145 -6
*
* We use the minimum values in the calculations below.
*/
static const short int coeff_clk_termen[] = { 0, 0 };
static const short int coeff_clk_settle[] = { 95, -8 };
static const short int coeff_dat_termen[] = { 0, 0 };
static const short int coeff_dat_settle[] = { 85, -2 };
static const int TERMEN_DEFAULT = 0 * 0;
static const int SETTLE_DEFAULT = 0x480;
static const hrt_address csi2_port_base[] = {
[ATOMISP_CAMERA_PORT_PRIMARY] = CSI2_PORT_A_BASE,
[ATOMISP_CAMERA_PORT_SECONDARY] = CSI2_PORT_B_BASE,
[ATOMISP_CAMERA_PORT_TERTIARY] = CSI2_PORT_C_BASE,
};
/* Number of lanes on each port, excluding clock lane */
static const unsigned char csi2_port_lanes[] = {
[ATOMISP_CAMERA_PORT_PRIMARY] = 4,
[ATOMISP_CAMERA_PORT_SECONDARY] = 2,
[ATOMISP_CAMERA_PORT_TERTIARY] = 2,
};
static const hrt_address csi2_lane_base[] = {
CSI2_LANE_CL_BASE,
CSI2_LANE_D0_BASE,
CSI2_LANE_D1_BASE,
CSI2_LANE_D2_BASE,
CSI2_LANE_D3_BASE,
};
int clk_termen;
int clk_settle;
int dat_termen;
int dat_settle;
struct v4l2_control ctrl;
struct atomisp_device *isp = asd->isp;
struct camera_mipi_info *mipi_info;
int mipi_freq = 0;
enum atomisp_camera_port port;
int n;
mipi_info = atomisp_to_sensor_mipi_info(
isp->inputs[asd->input_curr].camera);
port = mipi_info->port;
ctrl.id = V4L2_CID_LINK_FREQ;
if (v4l2_g_ctrl
(isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl) == 0)
mipi_freq = ctrl.value;
clk_termen = atomisp_csi2_configure_calc(coeff_clk_termen,
mipi_freq, TERMEN_DEFAULT);
clk_settle = atomisp_csi2_configure_calc(coeff_clk_settle,
mipi_freq, SETTLE_DEFAULT);
dat_termen = atomisp_csi2_configure_calc(coeff_dat_termen,
mipi_freq, TERMEN_DEFAULT);
dat_settle = atomisp_csi2_configure_calc(coeff_dat_settle,
mipi_freq, SETTLE_DEFAULT);
for (n = 0; n < csi2_port_lanes[port] + 1; n++) {
hrt_address base = csi2_port_base[port] + csi2_lane_base[n];
atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_TERMEN,
n == 0 ? clk_termen : dat_termen);
atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_SETTLE,
n == 0 ? clk_settle : dat_settle);
}
}
void atomisp_csi2_configure(struct atomisp_sub_device *asd)
{
if (IS_HWREVISION(asd->isp, ATOMISP_HW_REVISION_ISP2401))
atomisp_csi2_configure_isp2401(asd);
}
/*
* atomisp_mipi_csi2_cleanup - Routine for module driver cleanup
*/
void atomisp_mipi_csi2_cleanup(struct atomisp_device *isp)
{
}
#ifndef ISP2401
#endif
int atomisp_mipi_csi2_init(struct atomisp_device *isp)
{
struct atomisp_mipi_csi2_device *csi2_port;
unsigned int i;
int ret;
for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
csi2_port = &isp->csi2_port[i];
csi2_port->isp = isp;
ret = mipi_csi2_init_entities(csi2_port, i);
if (ret < 0)
goto fail;
}
return 0;
fail:
atomisp_mipi_csi2_cleanup(isp);
return ret;
}

61
drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.h Normal file
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_CSI2_H__
#define __ATOMISP_CSI2_H__
#include <media/v4l2-subdev.h>
#include <media/v4l2-ctrls.h>
#define CSI2_PAD_SINK 0
#define CSI2_PAD_SOURCE 1
#define CSI2_PADS_NUM 2
#define CSI2_OUTPUT_ISP_SUBDEV (1 << 0)
#define CSI2_OUTPUT_MEMORY (1 << 1)
struct atomisp_device;
struct v4l2_device;
struct atomisp_sub_device;
struct atomisp_mipi_csi2_device {
struct v4l2_subdev subdev;
struct media_pad pads[CSI2_PADS_NUM];
struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
struct v4l2_ctrl_handler ctrls;
struct atomisp_device *isp;
u32 output; /* output direction */
};
int atomisp_csi2_set_ffmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
unsigned int which, uint16_t pad,
struct v4l2_mbus_framefmt *ffmt);
int atomisp_mipi_csi2_init(struct atomisp_device *isp);
void atomisp_mipi_csi2_cleanup(struct atomisp_device *isp);
void atomisp_mipi_csi2_unregister_entities(
struct atomisp_mipi_csi2_device *csi2);
int atomisp_mipi_csi2_register_entities(struct atomisp_mipi_csi2_device *csi2,
struct v4l2_device *vdev);
void atomisp_csi2_configure(struct atomisp_sub_device *asd);
#endif /* __ATOMISP_CSI2_H__ */

416
drivers/staging/media/atomisp/pci/atomisp2/atomisp_dfs_tables.h Normal file
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/*
* Support for Intel Camera Imaging ISP subsystem.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_DFS_TABLES_H__
#define __ATOMISP_DFS_TABLES_H__
#include <linux/kernel.h>
struct atomisp_freq_scaling_rule {
unsigned int width;
unsigned int height;
unsigned short fps;
unsigned int isp_freq;
unsigned int run_mode;
};
struct atomisp_dfs_config {
unsigned int lowest_freq;
unsigned int max_freq_at_vmin;
unsigned int highest_freq;
const struct atomisp_freq_scaling_rule *dfs_table;
unsigned int dfs_table_size;
};
static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_457MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
/* Merrifield and Moorefield DFS rules */
static const struct atomisp_dfs_config dfs_config_merr = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_400MHZ,
.highest_freq = ISP_FREQ_457MHZ,
.dfs_table = dfs_rules_merr,
.dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
};
static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_merr_1179 = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_400MHZ,
.highest_freq = ISP_FREQ_400MHZ,
.dfs_table = dfs_rules_merr_1179,
.dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
};
static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
{
.width = 1920,
.height = 1080,
.fps = 30,
.isp_freq = ISP_FREQ_266MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = 1080,
.height = 1920,
.fps = 30,
#ifndef ISP2401
.isp_freq = ISP_FREQ_266MHZ,
#else
.isp_freq = ISP_FREQ_400MHZ,
#endif
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = 1920,
.height = 1080,
.fps = 45,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = 1080,
.height = 1920,
.fps = 45,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = 60,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_200MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_200MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_merr_117a = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_200MHZ,
.highest_freq = ISP_FREQ_400MHZ,
.dfs_table = dfs_rules_merr_117a,
.dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
};
static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_byt = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_400MHZ,
.highest_freq = ISP_FREQ_400MHZ,
.dfs_table = dfs_rules_byt,
.dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
};
static const struct atomisp_freq_scaling_rule dfs_rules_byt_cr[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_byt_cr = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_320MHZ,
.highest_freq = ISP_FREQ_320MHZ,
.dfs_table = dfs_rules_byt_cr,
.dfs_table_size = ARRAY_SIZE(dfs_rules_byt_cr),
};
static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
#ifdef ISP2401
.width = 1280,
.height = 720,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
#endif
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_cht = {
.lowest_freq = ISP_FREQ_100MHZ,
.max_freq_at_vmin = ISP_FREQ_356MHZ,
.highest_freq = ISP_FREQ_356MHZ,
.dfs_table = dfs_rules_cht,
.dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
};
#ifdef ISP2401
static const struct atomisp_dfs_config dfs_config_cht_soc = {
.lowest_freq = ISP_FREQ_100MHZ,
.max_freq_at_vmin = ISP_FREQ_356MHZ,
.highest_freq = ISP_FREQ_356MHZ,
.dfs_table = dfs_rules_cht_soc,
.dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
};
#endif
#endif /* __ATOMISP_DFS_TABLES_H__ */

218
drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.c Normal file
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/*
* Support for atomisp driver sysfs interface
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include "atomisp_compat.h"
#include "atomisp_internal.h"
#include "atomisp_ioctl.h"
#include "hmm/hmm.h"
/*
* _iunit_debug:
* dbglvl: iunit css driver trace level
* dbgopt: iunit debug option:
* bit 0: binary list
* bit 1: running binary
* bit 2: memory statistic
*/
struct _iunit_debug {
struct pci_driver *drv;
struct atomisp_device *isp;
unsigned int dbglvl;
unsigned int dbgfun;
unsigned int dbgopt;
};
#define OPTION_BIN_LIST (1<<0)
#define OPTION_BIN_RUN (1<<1)
#define OPTION_MEM_STAT (1<<2)
#define OPTION_VALID (OPTION_BIN_LIST \
| OPTION_BIN_RUN \
| OPTION_MEM_STAT)
static struct _iunit_debug iunit_debug = {
.dbglvl = 0,
.dbgopt = OPTION_BIN_LIST,
};
static inline int iunit_dump_dbgopt(struct atomisp_device *isp,
unsigned int opt)
{
int ret = 0;
if (opt & OPTION_VALID) {
if (opt & OPTION_BIN_LIST) {
ret = atomisp_css_dump_blob_infor();
if (ret) {
dev_err(atomisp_dev, "%s dump blob infor err[ret:%d]\n",
__func__, ret);
goto opt_err;
}
}
if (opt & OPTION_BIN_RUN) {
if (atomisp_streaming_count(isp)) {
atomisp_css_dump_sp_raw_copy_linecount(true);
atomisp_css_debug_dump_isp_binary();
} else {
ret = -EPERM;
dev_err(atomisp_dev, "%s dump running bin err[ret:%d]\n",
__func__, ret);
goto opt_err;
}
}
if (opt & OPTION_MEM_STAT)
hmm_show_mem_stat(__func__, __LINE__);
} else {
ret = -EINVAL;
dev_err(atomisp_dev, "%s dump nothing[ret=%d]\n", __func__,
ret);
}
opt_err:
return ret;
}
static ssize_t iunit_dbglvl_show(struct device_driver *drv, char *buf)
{
iunit_debug.dbglvl = atomisp_css_debug_get_dtrace_level();
return sprintf(buf, "dtrace level:%u\n", iunit_debug.dbglvl);
}
static ssize_t iunit_dbglvl_store(struct device_driver *drv, const char *buf,
size_t size)
{
if (kstrtouint(buf, 10, &iunit_debug.dbglvl)
|| iunit_debug.dbglvl < 1
|| iunit_debug.dbglvl > 9) {
dev_err(atomisp_dev, "%s setting %d value invalid, should be [1,9]\n",
__func__, iunit_debug.dbglvl);
return -EINVAL;
}
atomisp_css_debug_set_dtrace_level(iunit_debug.dbglvl);
return size;
}
static ssize_t iunit_dbgfun_show(struct device_driver *drv, char *buf)
{
iunit_debug.dbgfun = atomisp_get_css_dbgfunc();
return sprintf(buf, "dbgfun opt:%u\n", iunit_debug.dbgfun);
}
static ssize_t iunit_dbgfun_store(struct device_driver *drv, const char *buf,
size_t size)
{
unsigned int opt;
int ret;
if (kstrtouint(buf, 10, &opt)) {
dev_err(atomisp_dev, "%s setting %d value invalid\n",
__func__, opt);
return -EINVAL;
}
ret = atomisp_set_css_dbgfunc(iunit_debug.isp, opt);
if (ret)
return ret;
iunit_debug.dbgfun = opt;
return size;
}
static ssize_t iunit_dbgopt_show(struct device_driver *drv, char *buf)
{
return sprintf(buf, "option:0x%x\n", iunit_debug.dbgopt);
}
static ssize_t iunit_dbgopt_store(struct device_driver *drv, const char *buf,
size_t size)
{
unsigned int opt;
int ret;
if (kstrtouint(buf, 10, &opt)) {
dev_err(atomisp_dev, "%s setting %d value invalid\n",
__func__, opt);
return -EINVAL;
}
iunit_debug.dbgopt = opt;
ret = iunit_dump_dbgopt(iunit_debug.isp, iunit_debug.dbgopt);
if (ret)
return ret;
return size;
}
static struct driver_attribute iunit_drvfs_attrs[] = {
__ATTR(dbglvl, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH, iunit_dbglvl_show,
iunit_dbglvl_store),
__ATTR(dbgfun, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH, iunit_dbgfun_show,
iunit_dbgfun_store),
__ATTR(dbgopt, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH, iunit_dbgopt_show,
iunit_dbgopt_store),
};
static int iunit_drvfs_create_files(struct pci_driver *drv)
{
int i, ret = 0;
for (i = 0; i < ARRAY_SIZE(iunit_drvfs_attrs); i++)
ret |= driver_create_file(&(drv->driver),
&iunit_drvfs_attrs[i]);
return ret;
}
static void iunit_drvfs_remove_files(struct pci_driver *drv)
{
int i;
for (i = 0; i < ARRAY_SIZE(iunit_drvfs_attrs); i++)
driver_remove_file(&(drv->driver), &iunit_drvfs_attrs[i]);
}
int atomisp_drvfs_init(struct pci_driver *drv, struct atomisp_device *isp)
{
int ret;
iunit_debug.isp = isp;
iunit_debug.drv = drv;
ret = iunit_drvfs_create_files(iunit_debug.drv);
if (ret) {
dev_err(atomisp_dev, "drvfs_create_files error: %d\n", ret);
iunit_drvfs_remove_files(drv);
}
return ret;
}
void atomisp_drvfs_exit(void)
{
iunit_drvfs_remove_files(iunit_debug.drv);
}

29
drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.h Normal file
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/*
* Support for atomisp driver sysfs interface.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_DRVFS_H__
#define __ATOMISP_DRVFS_H__
extern int atomisp_drvfs_init(struct pci_driver *drv, struct atomisp_device
*isp);
extern void atomisp_drvfs_exit(void);
#endif /* __ATOMISP_DRVFS_H__ */

245
drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.c Normal file
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <media/v4l2-event.h>
#include <media/v4l2-mediabus.h>
#include <media/videobuf-vmalloc.h>
#include <linux/delay.h>
#include "ia_css.h"
#include "atomisp_cmd.h"
#include "atomisp_common.h"
#include "atomisp_file.h"
#include "atomisp_internal.h"
#include "atomisp_ioctl.h"
static void file_work(struct work_struct *work)
{
struct atomisp_file_device *file_dev =
container_of(work, struct atomisp_file_device, work);
struct atomisp_device *isp = file_dev->isp;
/* only support file injection on subdev0 */
struct atomisp_sub_device *asd = &isp->asd[0];
struct atomisp_video_pipe *out_pipe = &asd->video_in;
unsigned short *buf = videobuf_to_vmalloc(out_pipe->outq.bufs[0]);
struct v4l2_mbus_framefmt isp_sink_fmt;
if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED)
return;
dev_dbg(isp->dev, ">%s: ready to start streaming\n", __func__);
isp_sink_fmt = *atomisp_subdev_get_ffmt(&asd->subdev, NULL,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK);
while (!atomisp_css_isp_has_started())
usleep_range(1000, 1500);
atomisp_css_send_input_frame(asd, buf, isp_sink_fmt.width,
isp_sink_fmt.height);
dev_dbg(isp->dev, "<%s: streaming done\n", __func__);
}
static int file_input_s_stream(struct v4l2_subdev *sd, int enable)
{
struct atomisp_file_device *file_dev = v4l2_get_subdevdata(sd);
struct atomisp_device *isp = file_dev->isp;
/* only support file injection on subdev0 */
struct atomisp_sub_device *asd = &isp->asd[0];
dev_dbg(isp->dev, "%s: enable %d\n", __func__, enable);
if (enable) {
if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED)
return 0;
queue_work(file_dev->work_queue, &file_dev->work);
return 0;
}
cancel_work_sync(&file_dev->work);
return 0;
}
static int file_input_g_parm(struct v4l2_subdev *sd,
struct v4l2_streamparm *param)
{
/*to fake*/
return 0;
}
static int file_input_s_parm(struct v4l2_subdev *sd,
struct v4l2_streamparm *param)
{
/*to fake*/
return 0;
}
static int file_input_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
struct atomisp_file_device *file_dev = v4l2_get_subdevdata(sd);
struct atomisp_device *isp = file_dev->isp;
/* only support file injection on subdev0 */
struct atomisp_sub_device *asd = &isp->asd[0];
struct v4l2_mbus_framefmt *isp_sink_fmt;
if (format->pad)
return -EINVAL;
isp_sink_fmt = atomisp_subdev_get_ffmt(&asd->subdev, NULL,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK);
fmt->width = isp_sink_fmt->width;
fmt->height = isp_sink_fmt->height;
fmt->code = isp_sink_fmt->code;
return 0;
}
static int file_input_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
if (format->pad)
return -EINVAL;
file_input_get_fmt(sd, cfg, format);
if (format->which == V4L2_SUBDEV_FORMAT_TRY)
cfg->try_fmt = *fmt;
return 0;
}
static int file_input_log_status(struct v4l2_subdev *sd)
{
/*to fake*/
return 0;
}
static int file_input_s_power(struct v4l2_subdev *sd, int on)
{
/* to fake */
return 0;
}
static int file_input_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
/*to fake*/
return 0;
}
static int file_input_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
/*to fake*/
return 0;
}
static int file_input_enum_frame_ival(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_interval_enum
*fie)
{
/*to fake*/
return 0;
}
static const struct v4l2_subdev_video_ops file_input_video_ops = {
.s_stream = file_input_s_stream,
.g_parm = file_input_g_parm,
.s_parm = file_input_s_parm,
};
static const struct v4l2_subdev_core_ops file_input_core_ops = {
.log_status = file_input_log_status,
.s_power = file_input_s_power,
};
static const struct v4l2_subdev_pad_ops file_input_pad_ops = {
.enum_mbus_code = file_input_enum_mbus_code,
.enum_frame_size = file_input_enum_frame_size,
.enum_frame_interval = file_input_enum_frame_ival,
.get_fmt = file_input_get_fmt,
.set_fmt = file_input_set_fmt,
};
static const struct v4l2_subdev_ops file_input_ops = {
.core = &file_input_core_ops,
.video = &file_input_video_ops,
.pad = &file_input_pad_ops,
};
void
atomisp_file_input_unregister_entities(struct atomisp_file_device *file_dev)
{
media_entity_cleanup(&file_dev->sd.entity);
v4l2_device_unregister_subdev(&file_dev->sd);
}
int atomisp_file_input_register_entities(struct atomisp_file_device *file_dev,
struct v4l2_device *vdev)
{
/* Register the subdev and video nodes. */
return v4l2_device_register_subdev(vdev, &file_dev->sd);
}
void atomisp_file_input_cleanup(struct atomisp_device *isp)
{
struct atomisp_file_device *file_dev = &isp->file_dev;
if (file_dev->work_queue) {
destroy_workqueue(file_dev->work_queue);
file_dev->work_queue = NULL;
}
}
int atomisp_file_input_init(struct atomisp_device *isp)
{
struct atomisp_file_device *file_dev = &isp->file_dev;
struct v4l2_subdev *sd = &file_dev->sd;
struct media_pad *pads = file_dev->pads;
struct media_entity *me = &sd->entity;
file_dev->isp = isp;
file_dev->work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
if (file_dev->work_queue == NULL) {
dev_err(isp->dev, "Failed to initialize file inject workq\n");
return -ENOMEM;
}
INIT_WORK(&file_dev->work, file_work);
v4l2_subdev_init(sd, &file_input_ops);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
strcpy(sd->name, "file_input_subdev");
v4l2_set_subdevdata(sd, file_dev);
pads[0].flags = MEDIA_PAD_FL_SINK;
me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
return media_entity_pads_init(me, 1, pads);
}

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_FILE_H__
#define __ATOMISP_FILE_H__
#include <media/media-entity.h>
#include <media/v4l2-subdev.h>
struct atomisp_device;
struct atomisp_file_device {
struct v4l2_subdev sd;
struct atomisp_device *isp;
struct media_pad pads[1];
struct workqueue_struct *work_queue;
struct work_struct work;
};
void atomisp_file_input_cleanup(struct atomisp_device *isp);
int atomisp_file_input_init(struct atomisp_device *isp);
void atomisp_file_input_unregister_entities(
struct atomisp_file_device *file_dev);
int atomisp_file_input_register_entities(struct atomisp_file_device *file_dev,
struct v4l2_device *vdev);
#endif /* __ATOMISP_FILE_H__ */

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_FOPS_H__
#define __ATOMISP_FOPS_H__
#include "atomisp_subdev.h"
int atomisp_q_video_buffers_to_css(struct atomisp_sub_device *asd,
struct atomisp_video_pipe *pipe,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_buffer_type css_buf_type,
enum atomisp_css_pipe_id css_pipe_id);
unsigned int atomisp_dev_users(struct atomisp_device *isp);
unsigned int atomisp_sub_dev_users(struct atomisp_sub_device *asd);
/*
* Memory help functions for image frame and private parameters
*/
int atomisp_videobuf_mmap_mapper(struct videobuf_queue *q,
struct vm_area_struct *vma);
int atomisp_qbuf_to_css(struct atomisp_device *isp,
struct atomisp_video_pipe *pipe,
struct videobuf_buffer *vb);
int atomisp_qbuffers_to_css(struct atomisp_sub_device *asd);
extern const struct v4l2_file_operations atomisp_fops;
extern bool defer_fw_load;
#endif /* __ATOMISP_FOPS_H__ */

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef _atomisp_helper_h_
#define _atomisp_helper_h_
extern void __iomem *atomisp_io_base;
static inline void __iomem *atomisp_get_io_virt_addr(unsigned int address)
{
void __iomem *ret = atomisp_io_base + (address & 0x003FFFFF);
return ret;
}
#endif

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_INTERNAL_H__
#define __ATOMISP_INTERNAL_H__
#include <linux/atomisp_platform.h>
#include <linux/firmware.h>
#include <linux/kernel.h>
#include <linux/pm_qos.h>
#include <linux/idr.h>
#include <asm/intel-mid.h>
#include <asm/intel_mid_pcihelpers.h>
#include <media/media-device.h>
#include <media/v4l2-subdev.h>
#ifndef ISP2401
#include "ia_css_types.h"
#include "sh_css_legacy.h"
#else
/*#include "ia_css_types.h"*/
/*#include "sh_css_legacy.h"*/
#endif
#include "atomisp_csi2.h"
#include "atomisp_file.h"
#include "atomisp_subdev.h"
#include "atomisp_tpg.h"
#include "atomisp_compat.h"
#include "gp_device.h"
#include "irq.h"
#include <linux/vmalloc.h>
#define V4L2_EVENT_FRAME_END 5
#define IS_HWREVISION(isp, rev) \
(((isp)->media_dev.hw_revision & ATOMISP_HW_REVISION_MASK) == \
((rev) << ATOMISP_HW_REVISION_SHIFT))
#define MAX_STREAM_NUM 2
#define ATOMISP_PCI_DEVICE_SOC_MASK 0xfff8
/* MRFLD with 0x1178: ISP freq can burst to 457MHz */
#define ATOMISP_PCI_DEVICE_SOC_MRFLD 0x1178
/* MRFLD with 0x1179: max ISP freq limited to 400MHz */
#define ATOMISP_PCI_DEVICE_SOC_MRFLD_1179 0x1179
/* MRFLD with 0x117a: max ISP freq is 400MHz and max freq at Vmin is 200MHz */
#define ATOMISP_PCI_DEVICE_SOC_MRFLD_117A 0x117a
#define ATOMISP_PCI_DEVICE_SOC_BYT 0x0f38
#define ATOMISP_PCI_DEVICE_SOC_ANN 0x1478
#define ATOMISP_PCI_DEVICE_SOC_CHT 0x22b8
#define ATOMISP_PCI_REV_MRFLD_A0_MAX 0
#define ATOMISP_PCI_REV_BYT_A0_MAX 4
#define ATOMISP_MAJOR 0
#define ATOMISP_MINOR 5
#define ATOMISP_PATCHLEVEL 1
#define DRIVER_VERSION_STR __stringify(ATOMISP_MAJOR) \
"." __stringify(ATOMISP_MINOR) "." __stringify(ATOMISP_PATCHLEVEL)
#define DRIVER_VERSION KERNEL_VERSION(ATOMISP_MAJOR, \
ATOMISP_MINOR, ATOMISP_PATCHLEVEL)
#define ATOM_ISP_STEP_WIDTH 2
#define ATOM_ISP_STEP_HEIGHT 2
#define ATOM_ISP_MIN_WIDTH 4
#define ATOM_ISP_MIN_HEIGHT 4
#define ATOM_ISP_MAX_WIDTH UINT_MAX
#define ATOM_ISP_MAX_HEIGHT UINT_MAX
/* sub-QCIF resolution */
#define ATOM_RESOLUTION_SUBQCIF_WIDTH 128
#define ATOM_RESOLUTION_SUBQCIF_HEIGHT 96
#define ATOM_ISP_MAX_WIDTH_TMP 1280
#define ATOM_ISP_MAX_HEIGHT_TMP 720
#define ATOM_ISP_I2C_BUS_1 4
#define ATOM_ISP_I2C_BUS_2 5
#define ATOM_ISP_POWER_DOWN 0
#define ATOM_ISP_POWER_UP 1
#define ATOM_ISP_MAX_INPUTS 4
#define ATOMISP_SC_TYPE_SIZE 2
#define ATOMISP_ISP_TIMEOUT_DURATION (2 * HZ)
#define ATOMISP_EXT_ISP_TIMEOUT_DURATION (6 * HZ)
#define ATOMISP_ISP_FILE_TIMEOUT_DURATION (60 * HZ)
#define ATOMISP_WDT_KEEP_CURRENT_DELAY 0
#define ATOMISP_ISP_MAX_TIMEOUT_COUNT 2
#define ATOMISP_CSS_STOP_TIMEOUT_US 200000
#define ATOMISP_CSS_Q_DEPTH 3
#define ATOMISP_CSS_EVENTS_MAX 16
#define ATOMISP_CONT_RAW_FRAMES 15
#define ATOMISP_METADATA_QUEUE_DEPTH_FOR_HAL 8
#define ATOMISP_S3A_BUF_QUEUE_DEPTH_FOR_HAL 8
#define ATOMISP_DELAYED_INIT_NOT_QUEUED 0
#define ATOMISP_DELAYED_INIT_QUEUED 1
#define ATOMISP_DELAYED_INIT_DONE 2
#define ATOMISP_CALC_CSS_PREV_OVERLAP(lines) \
((lines) * 38 / 100 & 0xfffffe)
/*
* Define how fast CPU should be able to serve ISP interrupts.
* The bigger the value, the higher risk that the ISP is not
* triggered sufficiently fast for it to process image during
* vertical blanking time, increasing risk of dropped frames.
* 1000 us is a reasonable value considering that the processing
* time is typically ~2000 us.
*/
#define ATOMISP_MAX_ISR_LATENCY 1000
/* Add new YUVPP pipe for SOC sensor. */
#define ATOMISP_CSS_SUPPORT_YUVPP 1
#define ATOMISP_CSS_OUTPUT_SECOND_INDEX 1
#define ATOMISP_CSS_OUTPUT_DEFAULT_INDEX 0
/*
* ATOMISP_SOC_CAMERA
* This is to differentiate between ext-isp and soc camera in
* Moorefield/Baytrail platform.
*/
#define ATOMISP_SOC_CAMERA(asd) \
(asd->isp->inputs[asd->input_curr].type == SOC_CAMERA \
&& asd->isp->inputs[asd->input_curr].camera_caps-> \
sensor[asd->sensor_curr].stream_num == 1)
#define ATOMISP_USE_YUVPP(asd) \
(ATOMISP_SOC_CAMERA(asd) && ATOMISP_CSS_SUPPORT_YUVPP && \
!asd->copy_mode)
#define ATOMISP_DEPTH_SENSOR_STREAMON_COUNT 2
#define ATOMISP_DEPTH_DEFAULT_MASTER_SENSOR 0
#define ATOMISP_DEPTH_DEFAULT_SLAVE_SENSOR 1
#ifdef ISP2401
#define ATOMISP_ION_DEVICE_FD_OFFSET 16
#define ATOMISP_ION_SHARED_FD_MASK (0xFFFF)
#define ATOMISP_ION_DEVICE_FD_MASK (~ATOMISP_ION_SHARED_FD_MASK)
#define ION_FD_UNSET (-1)
#endif
#define DIV_NEAREST_STEP(n, d, step) \
round_down((2 * (n) + (d) * (step))/(2 * (d)), (step))
struct atomisp_input_subdev {
unsigned int type;
enum atomisp_camera_port port;
struct v4l2_subdev *camera;
struct v4l2_subdev *motor;
struct v4l2_frmsizeenum frame_size;
/*
* To show this resource is used by
* which stream, in ISP multiple stream mode
*/
struct atomisp_sub_device *asd;
const struct atomisp_camera_caps *camera_caps;
int sensor_index;
};
enum atomisp_dfs_mode {
ATOMISP_DFS_MODE_AUTO = 0,
ATOMISP_DFS_MODE_LOW,
ATOMISP_DFS_MODE_MAX,
};
struct atomisp_regs {
/* PCI config space info */
u16 pcicmdsts;
u32 ispmmadr;
u32 msicap;
u32 msi_addr;
u16 msi_data;
u8 intr;
u32 interrupt_control;
u32 pmcs;
u32 cg_dis;
u32 i_control;
/* I-Unit PHY related info */
u32 csi_rcomp_config;
u32 csi_afe_dly;
u32 csi_control;
/* New for MRFLD */
u32 csi_afe_rcomp_config;
u32 csi_afe_hs_control;
u32 csi_deadline_control;
u32 csi_access_viol;
};
struct atomisp_sw_contex {
bool file_input;
int power_state;
int running_freq;
};
#define ATOMISP_DEVICE_STREAMING_DISABLED 0
#define ATOMISP_DEVICE_STREAMING_ENABLED 1
#define ATOMISP_DEVICE_STREAMING_STOPPING 2
/*
* ci device struct
*/
struct atomisp_device {
struct pci_dev *pdev;
struct device *dev;
struct v4l2_device v4l2_dev;
struct media_device media_dev;
struct atomisp_platform_data *pdata;
void *mmu_l1_base;
struct pci_dev *pci_root;
const struct firmware *firmware;
struct pm_qos_request pm_qos;
s32 max_isr_latency;
/*
* ISP modules
* Multiple streams are represents by multiple
* atomisp_sub_device instances
*/
struct atomisp_sub_device *asd;
/*
* this will be assiged dyanamically.
* For Merr/BTY(ISP2400), 2 streams are supported.
*/
unsigned int num_of_streams;
struct atomisp_mipi_csi2_device csi2_port[ATOMISP_CAMERA_NR_PORTS];
struct atomisp_tpg_device tpg;
struct atomisp_file_device file_dev;
/* Purpose of mutex is to protect and serialize use of isp data
* structures and css API calls. */
struct rt_mutex mutex;
/*
* Serialise streamoff: mutex is dropped during streamoff to
* cancel the watchdog queue. MUST be acquired BEFORE
* "mutex".
*/
struct mutex streamoff_mutex;
int input_cnt;
struct atomisp_input_subdev inputs[ATOM_ISP_MAX_INPUTS];
struct v4l2_subdev *flash;
struct v4l2_subdev *motor;
struct atomisp_regs saved_regs;
struct atomisp_sw_contex sw_contex;
struct atomisp_css_env css_env;
/* isp timeout status flag */
bool isp_timeout;
bool isp_fatal_error;
struct workqueue_struct *wdt_work_queue;
struct work_struct wdt_work;
#ifndef ISP2401
atomic_t wdt_count;
#endif
atomic_t wdt_work_queued;
spinlock_t lock; /* Just for streaming below */
bool need_gfx_throttle;
unsigned int mipi_frame_size;
const struct atomisp_dfs_config *dfs;
unsigned int hpll_freq;
bool css_initialized;
};
#define v4l2_dev_to_atomisp_device(dev) \
container_of(dev, struct atomisp_device, v4l2_dev)
extern struct device *atomisp_dev;
extern void *atomisp_kernel_malloc(size_t bytes);
extern void atomisp_kernel_free(void *ptr);
#define atomisp_is_wdt_running(a) timer_pending(&(a)->wdt)
#ifdef ISP2401
extern void atomisp_wdt_refresh_pipe(struct atomisp_video_pipe *pipe,
unsigned int delay);
#endif
extern void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay);
#ifndef ISP2401
extern void atomisp_wdt_start(struct atomisp_sub_device *asd);
#else
extern void atomisp_wdt_start(struct atomisp_video_pipe *pipe);
extern void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync);
#endif
extern void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync);
#endif /* __ATOMISP_INTERNAL_H__ */

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_IOCTL_H__
#define __ATOMISP_IOCTL_H__
#include "ia_css.h"
struct atomisp_device;
struct atomisp_video_pipe;
extern const struct atomisp_format_bridge atomisp_output_fmts[];
const struct atomisp_format_bridge *atomisp_get_format_bridge(
unsigned int pixelformat);
#ifndef ISP2401
const struct atomisp_format_bridge *atomisp_get_format_bridge_from_mbus(
u32 mbus_code);
#else
const struct atomisp_format_bridge *atomisp_get_format_bridge_from_mbus(u32
mbus_code);
#endif
int atomisp_alloc_css_stat_bufs(struct atomisp_sub_device *asd,
uint16_t stream_id);
int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type);
int __atomisp_reqbufs(struct file *file, void *fh,
struct v4l2_requestbuffers *req);
int atomisp_reqbufs(struct file *file, void *fh,
struct v4l2_requestbuffers *req);
enum atomisp_css_pipe_id atomisp_get_css_pipe_id(struct atomisp_sub_device
*asd);
void atomisp_videobuf_free_buf(struct videobuf_buffer *vb);
extern const struct v4l2_file_operations atomisp_file_fops;
extern const struct v4l2_ioctl_ops atomisp_ioctl_ops;
extern const struct v4l2_ioctl_ops atomisp_file_ioctl_ops;
unsigned int atomisp_streaming_count(struct atomisp_device *isp);
unsigned int atomisp_is_acc_enabled(struct atomisp_device *isp);
/* compat_ioctl for 32bit userland app and 64bit kernel */
long atomisp_compat_ioctl32(struct file *file,
unsigned int cmd, unsigned long arg);
int atomisp_stream_on_master_slave_sensor(struct atomisp_device *isp, bool isp_timeout);
#endif /* __ATOMISP_IOCTL_H__ */

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_SUBDEV_H__
#define __ATOMISP_SUBDEV_H__
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include <media/videobuf-core.h>
#include "atomisp_common.h"
#include "atomisp_compat.h"
#include "atomisp_v4l2.h"
#include "ia_css.h"
/* EXP_ID's ranger is 1 ~ 250 */
#define ATOMISP_MAX_EXP_ID (250)
enum atomisp_subdev_input_entity {
ATOMISP_SUBDEV_INPUT_NONE,
ATOMISP_SUBDEV_INPUT_MEMORY,
ATOMISP_SUBDEV_INPUT_CSI2,
/*
* The following enum for CSI2 port must go together in one row.
* Otherwise it breaks the code logic.
*/
ATOMISP_SUBDEV_INPUT_CSI2_PORT1,
ATOMISP_SUBDEV_INPUT_CSI2_PORT2,
ATOMISP_SUBDEV_INPUT_CSI2_PORT3,
};
#define ATOMISP_SUBDEV_PAD_SINK 0
/* capture output for still frames */
#define ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE 1
/* viewfinder output for downscaled capture output */
#define ATOMISP_SUBDEV_PAD_SOURCE_VF 2
/* preview output for display */
#define ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW 3
/* main output for video pipeline */
#define ATOMISP_SUBDEV_PAD_SOURCE_VIDEO 4
#define ATOMISP_SUBDEV_PADS_NUM 5
struct atomisp_in_fmt_conv {
u32 code;
uint8_t bpp; /* bits per pixel */
uint8_t depth; /* uncompressed */
enum atomisp_css_stream_format atomisp_in_fmt;
enum atomisp_css_bayer_order bayer_order;
enum ia_css_stream_format css_stream_fmt;
};
struct atomisp_sub_device;
struct atomisp_video_pipe {
struct video_device vdev;
enum v4l2_buf_type type;
struct media_pad pad;
struct videobuf_queue capq;
struct videobuf_queue outq;
struct list_head activeq;
struct list_head activeq_out;
/*
* the buffers waiting for per-frame parameters, this is only valid
* in per-frame setting mode.
*/
struct list_head buffers_waiting_for_param;
/* the link list to store per_frame parameters */
struct list_head per_frame_params;
unsigned int buffers_in_css;
/* irq_lock is used to protect video buffer state change operations and
* also to make activeq, activeq_out, capq and outq list
* operations atomic. */
spinlock_t irq_lock;
unsigned int users;
struct atomisp_device *isp;
struct v4l2_pix_format pix;
uint32_t sh_fmt;
struct atomisp_sub_device *asd;
/*
* This frame_config_id is got from CSS when dequueues buffers from CSS,
* it is used to indicate which parameter it has applied.
*/
unsigned int frame_config_id[VIDEO_MAX_FRAME];
/*
* This config id is set when camera HAL enqueues buffer, it has a
* non-zero value to indicate which parameter it needs to applu
*/
unsigned int frame_request_config_id[VIDEO_MAX_FRAME];
struct atomisp_css_params_with_list *frame_params[VIDEO_MAX_FRAME];
#ifdef ISP2401
/*
* move wdt from asd struct to create wdt for each pipe
*/
struct timer_list wdt;
unsigned int wdt_duration; /* in jiffies */
unsigned long wdt_expires;
atomic_t wdt_count;
#endif
};
struct atomisp_acc_pipe {
struct video_device vdev;
unsigned int users;
bool running;
struct atomisp_sub_device *asd;
struct atomisp_device *isp;
};
struct atomisp_pad_format {
struct v4l2_mbus_framefmt fmt;
struct v4l2_rect crop;
struct v4l2_rect compose;
};
/* Internal states for flash process */
enum atomisp_flash_state {
ATOMISP_FLASH_IDLE,
ATOMISP_FLASH_REQUESTED,
ATOMISP_FLASH_ONGOING,
ATOMISP_FLASH_DONE
};
/*
* This structure is used to cache the CSS parameters, it aligns to
* struct ia_css_isp_config but without un-supported and deprecated parts.
*/
struct atomisp_css_params {
struct ia_css_wb_config wb_config;
struct ia_css_cc_config cc_config;
struct ia_css_tnr_config tnr_config;
struct ia_css_ecd_config ecd_config;
struct ia_css_ynr_config ynr_config;
struct ia_css_fc_config fc_config;
struct ia_css_formats_config formats_config;
struct ia_css_cnr_config cnr_config;
struct ia_css_macc_config macc_config;
struct ia_css_ctc_config ctc_config;
struct ia_css_aa_config aa_config;
struct ia_css_aa_config baa_config;
struct ia_css_ce_config ce_config;
struct ia_css_ob_config ob_config;
struct ia_css_dp_config dp_config;
struct ia_css_de_config de_config;
struct ia_css_gc_config gc_config;
struct ia_css_nr_config nr_config;
struct ia_css_ee_config ee_config;
struct ia_css_anr_config anr_config;
struct ia_css_3a_config s3a_config;
struct ia_css_xnr_config xnr_config;
struct ia_css_dz_config dz_config;
struct ia_css_cc_config yuv2rgb_cc_config;
struct ia_css_cc_config rgb2yuv_cc_config;
struct ia_css_macc_table macc_table;
struct ia_css_gamma_table gamma_table;
struct ia_css_ctc_table ctc_table;
struct ia_css_xnr_table xnr_table;
struct ia_css_rgb_gamma_table r_gamma_table;
struct ia_css_rgb_gamma_table g_gamma_table;
struct ia_css_rgb_gamma_table b_gamma_table;
struct ia_css_vector motion_vector;
struct ia_css_anr_thres anr_thres;
struct ia_css_dvs_6axis_config *dvs_6axis;
struct ia_css_dvs2_coefficients *dvs2_coeff;
struct ia_css_shading_table *shading_table;
struct ia_css_morph_table *morph_table;
/*
* Used to store the user pointer address of the frame. driver needs to
* translate to ia_css_frame * and then set to CSS.
*/
void *output_frame;
uint32_t isp_config_id;
/* Indicates which parameters need to be updated. */
struct atomisp_parameters update_flag;
};
struct atomisp_subdev_params {
/* FIXME: Determines whether raw capture buffer are being passed to
* user space. Unimplemented for now. */
int online_process;
int yuv_ds_en;
unsigned int color_effect;
bool gdc_cac_en;
bool macc_en;
bool bad_pixel_en;
bool video_dis_en;
bool sc_en;
bool fpn_en;
bool xnr_en;
bool low_light;
int false_color;
unsigned int histogram_elenum;
/* Current grid info */
struct atomisp_css_grid_info curr_grid_info;
enum atomisp_css_pipe_id s3a_enabled_pipe;
int s3a_output_bytes;
bool dis_proj_data_valid;
struct ia_css_dz_config dz_config; /**< Digital Zoom */
struct ia_css_capture_config capture_config;
struct atomisp_css_isp_config config;
/* current configurations */
struct atomisp_css_params css_param;
/*
* Intermediate buffers used to communicate data between
* CSS and user space.
*/
struct ia_css_3a_statistics *s3a_user_stat;
void *metadata_user[ATOMISP_METADATA_TYPE_NUM];
uint32_t metadata_width_size;
struct ia_css_dvs2_statistics *dvs_stat;
struct atomisp_css_dvs_6axis *dvs_6axis;
uint32_t exp_id;
int dvs_hor_coef_bytes;
int dvs_ver_coef_bytes;
int dvs_ver_proj_bytes;
int dvs_hor_proj_bytes;
/* Flash */
int num_flash_frames;
enum atomisp_flash_state flash_state;
enum atomisp_frame_status last_frame_status;
/* continuous capture */
struct atomisp_cont_capture_conf offline_parm;
/* Flag to check if driver needs to update params to css */
bool css_update_params_needed;
};
struct atomisp_css_params_with_list {
/* parameters for CSS */
struct atomisp_css_params params;
struct list_head list;
};
struct atomisp_acc_fw {
struct atomisp_css_fw_info *fw;
unsigned int handle;
unsigned int flags;
unsigned int type;
struct {
size_t length;
unsigned long css_ptr;
} args[ATOMISP_ACC_NR_MEMORY];
struct list_head list;
};
struct atomisp_map {
ia_css_ptr ptr;
size_t length;
struct list_head list;
/* FIXME: should keep book which maps are currently used
* by binaries and not allow releasing those
* which are in use. Implement by reference counting.
*/
};
struct atomisp_sub_device {
struct v4l2_subdev subdev;
struct media_pad pads[ATOMISP_SUBDEV_PADS_NUM];
struct atomisp_pad_format fmt[ATOMISP_SUBDEV_PADS_NUM];
uint16_t capture_pad; /* main capture pad; defines much of isp config */
enum atomisp_subdev_input_entity input;
unsigned int output;
struct atomisp_video_pipe video_in;
struct atomisp_video_pipe video_out_capture; /* capture output */
struct atomisp_video_pipe video_out_vf; /* viewfinder output */
struct atomisp_video_pipe video_out_preview; /* preview output */
struct atomisp_acc_pipe video_acc;
/* video pipe main output */
struct atomisp_video_pipe video_out_video_capture;
/* struct isp_subdev_params params; */
spinlock_t lock;
struct atomisp_device *isp;
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_ctrl *fmt_auto;
struct v4l2_ctrl *run_mode;
struct v4l2_ctrl *depth_mode;
struct v4l2_ctrl *vfpp;
struct v4l2_ctrl *continuous_mode;
struct v4l2_ctrl *continuous_raw_buffer_size;
struct v4l2_ctrl *continuous_viewfinder;
struct v4l2_ctrl *enable_raw_buffer_lock;
#ifdef ISP2401
struct v4l2_ctrl *ion_dev_fd;
#endif
struct v4l2_ctrl *disable_dz;
#ifdef ISP2401
struct v4l2_ctrl *select_isp_version;
#endif
struct {
struct list_head fw;
struct list_head memory_maps;
struct atomisp_css_pipeline *pipeline;
bool extension_mode;
struct ida ida;
struct completion acc_done;
void *acc_stages;
} acc;
struct atomisp_subdev_params params;
struct atomisp_stream_env stream_env[ATOMISP_INPUT_STREAM_NUM];
struct v4l2_pix_format dvs_envelop;
unsigned int s3a_bufs_in_css[CSS_PIPE_ID_NUM];
unsigned int dis_bufs_in_css;
unsigned int metadata_bufs_in_css
[ATOMISP_INPUT_STREAM_NUM][CSS_PIPE_ID_NUM];
/* The list of free and available metadata buffers for CSS */
struct list_head metadata[ATOMISP_METADATA_TYPE_NUM];
/* The list of metadata buffers which have been en-queued to CSS */
struct list_head metadata_in_css[ATOMISP_METADATA_TYPE_NUM];
/* The list of metadata buffers which are ready for userspace to get */
struct list_head metadata_ready[ATOMISP_METADATA_TYPE_NUM];
/* The list of free and available s3a stat buffers for CSS */
struct list_head s3a_stats;
/* The list of s3a stat buffers which have been en-queued to CSS */
struct list_head s3a_stats_in_css;
/* The list of s3a stat buffers which are ready for userspace to get */
struct list_head s3a_stats_ready;
struct list_head dis_stats;
struct list_head dis_stats_in_css;
spinlock_t dis_stats_lock;
struct atomisp_css_frame *vf_frame; /* TODO: needed? */
struct atomisp_css_frame *raw_output_frame;
enum atomisp_frame_status frame_status[VIDEO_MAX_FRAME];
/* This field specifies which camera (v4l2 input) is selected. */
int input_curr;
/* This field specifies which sensor is being selected when there
are multiple sensors connected to the same MIPI port. */
int sensor_curr;
atomic_t sof_count;
atomic_t sequence; /* Sequence value that is assigned to buffer. */
atomic_t sequence_temp;
unsigned int streaming; /* Hold both mutex and lock to change this */
bool stream_prepared; /* whether css stream is created */
/* subdev index: will be used to show which subdev is holding the
* resource, like which camera is used by which subdev
*/
unsigned int index;
/* delayed memory allocation for css */
struct completion init_done;
struct workqueue_struct *delayed_init_workq;
unsigned int delayed_init;
struct work_struct delayed_init_work;
unsigned int latest_preview_exp_id; /* CSS ZSL/SDV raw buffer id */
unsigned int mipi_frame_size;
bool copy_mode; /* CSI2+ use copy mode */
bool yuvpp_mode; /* CSI2+ yuvpp pipe */
int raw_buffer_bitmap[ATOMISP_MAX_EXP_ID/32 + 1]; /* Record each Raw Buffer lock status */
int raw_buffer_locked_count;
spinlock_t raw_buffer_bitmap_lock;
#ifndef ISP2401
struct timer_list wdt;
unsigned int wdt_duration; /* in jiffies */
unsigned long wdt_expires;
#endif
struct atomisp_resolution sensor_array_res;
bool high_speed_mode; /* Indicate whether now is a high speed mode */
int pending_capture_request; /* Indicates the number of pending capture requests. */
#ifndef ISP2401
#else
bool re_trigger_capture;
#endif
unsigned int preview_exp_id;
unsigned int postview_exp_id;
};
extern const struct atomisp_in_fmt_conv atomisp_in_fmt_conv[];
u32 atomisp_subdev_uncompressed_code(u32 code);
bool atomisp_subdev_is_compressed(u32 code);
const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv(u32 code);
#ifndef ISP2401
const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_by_atomisp_in_fmt(
enum atomisp_css_stream_format atomisp_in_fmt);
#else
const struct atomisp_in_fmt_conv
*atomisp_find_in_fmt_conv_by_atomisp_in_fmt(enum atomisp_css_stream_format
atomisp_in_fmt);
#endif
const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_compressed(u32 code);
bool atomisp_subdev_format_conversion(struct atomisp_sub_device *asd,
unsigned int source_pad);
uint16_t atomisp_subdev_source_pad(struct video_device *vdev);
/* Get pointer to appropriate format */
struct v4l2_mbus_framefmt
*atomisp_subdev_get_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg, uint32_t which,
uint32_t pad);
struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad,
uint32_t target);
int atomisp_subdev_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad, uint32_t target,
uint32_t flags, struct v4l2_rect *r);
/* Actually set the format */
void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg, uint32_t which,
uint32_t pad, struct v4l2_mbus_framefmt *ffmt);
int atomisp_update_run_mode(struct atomisp_sub_device *asd);
void atomisp_subdev_cleanup_pending_events(struct atomisp_sub_device *asd);
void atomisp_subdev_unregister_entities(struct atomisp_sub_device *asd);
int atomisp_subdev_register_entities(struct atomisp_sub_device *asd,
struct v4l2_device *vdev);
int atomisp_subdev_init(struct atomisp_device *isp);
void atomisp_subdev_cleanup(struct atomisp_device *isp);
int atomisp_create_pads_links(struct atomisp_device *isp);
#endif /* __ATOMISP_SUBDEV_H__ */

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_TABLES_H__
#define __ATOMISP_TABLES_H__
#include "sh_css_params.h"
/*Sepia image effect table*/
static struct atomisp_css_cc_config sepia_cc_config = {
.fraction_bits = 8,
.matrix = {141, 18, 68, -40, -5, -19, 35, 4, 16},
};
/*Negative image effect table*/
static struct atomisp_css_cc_config nega_cc_config = {
.fraction_bits = 8,
.matrix = {255, 29, 120, 0, 374, 342, 0, 672, -301},
};
/*Mono image effect table*/
static struct atomisp_css_cc_config mono_cc_config = {
.fraction_bits = 8,
.matrix = {255, 29, 120, 0, 0, 0, 0, 0, 0},
};
/*Skin whiten image effect table*/
static struct atomisp_css_macc_table skin_low_macc_table = {
.data = {
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
7168, 0, 2048, 8192,
5120, -1024, 2048, 8192,
8192, 2048, -1024, 5120,
8192, 2048, 0, 7168,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192
}
};
static struct atomisp_css_macc_table skin_medium_macc_table = {
.data = {
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
5120, 0, 6144, 8192,
3072, -1024, 2048, 6144,
6144, 2048, -1024, 3072,
8192, 6144, 0, 5120,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192
}
};
static struct atomisp_css_macc_table skin_high_macc_table = {
.data = {
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
4096, 0, 8192, 8192,
0, -2048, 4096, 6144,
6144, 4096, -2048, 0,
8192, 8192, 0, 4096,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192
}
};
/*Blue enhencement image effect table*/
static struct atomisp_css_macc_table blue_macc_table = {
.data = {
9728, -3072, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
9728, 0, -3072, 8192,
12800, 1536, -3072, 8192,
11264, 0, 0, 11264,
9728, -3072, 0, 11264
}
};
/*Green enhencement image effect table*/
static struct atomisp_css_macc_table green_macc_table = {
.data = {
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
10240, 4096, 0, 8192,
10240, 4096, 0, 12288,
12288, 0, 0, 12288,
14336, -2048, 4096, 8192,
10240, 0, 4096, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192
}
};
static struct atomisp_css_ctc_table vivid_ctc_table = {
.data.vamem_2 = {
0, 384, 837, 957, 1011, 1062, 1083, 1080,
1078, 1077, 1053, 1039, 1012, 992, 969, 951,
929, 906, 886, 866, 845, 823, 809, 790,
772, 758, 741, 726, 711, 701, 688, 675,
666, 656, 648, 639, 633, 626, 618, 612,
603, 594, 582, 572, 557, 545, 529, 516,
504, 491, 480, 467, 459, 447, 438, 429,
419, 412, 404, 397, 389, 382, 376, 368,
363, 357, 351, 345, 340, 336, 330, 326,
321, 318, 312, 308, 304, 300, 297, 294,
291, 286, 284, 281, 278, 275, 271, 268,
261, 257, 251, 245, 240, 235, 232, 225,
223, 218, 213, 209, 206, 204, 199, 197,
193, 189, 186, 185, 183, 179, 177, 175,
172, 170, 169, 167, 164, 164, 162, 160,
158, 157, 156, 154, 154, 152, 151, 150,
149, 148, 146, 147, 146, 144, 143, 143,
142, 141, 140, 141, 139, 138, 138, 138,
137, 136, 136, 135, 134, 134, 134, 133,
132, 132, 131, 130, 131, 130, 129, 128,
129, 127, 127, 127, 127, 125, 125, 125,
123, 123, 122, 120, 118, 115, 114, 111,
110, 108, 106, 105, 103, 102, 100, 99,
97, 97, 96, 95, 94, 93, 93, 91,
91, 91, 90, 90, 89, 89, 88, 88,
89, 88, 88, 87, 87, 87, 87, 86,
87, 87, 86, 87, 86, 86, 84, 84,
82, 80, 78, 76, 74, 72, 70, 68,
67, 65, 62, 60, 58, 56, 55, 54,
53, 51, 49, 49, 47, 45, 45, 45,
41, 40, 39, 39, 34, 33, 34, 32,
25, 23, 24, 20, 13, 9, 12, 0,
0
}
};
#endif

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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <media/v4l2-event.h>
#include <media/v4l2-mediabus.h>
#include "atomisp_internal.h"
#include "atomisp_tpg.h"
static int tpg_s_stream(struct v4l2_subdev *sd, int enable)
{
return 0;
}
static int tpg_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
{
/*to fake*/
return 0;
}
static int tpg_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param)
{
/*to fake*/
return 0;
}
static int tpg_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
/*to fake*/
return 0;
}
static int tpg_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
if (format->pad)
return -EINVAL;
/* only raw8 grbg is supported by TPG */
fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
cfg->try_fmt = *fmt;
return 0;
}
return 0;
}
static int tpg_log_status(struct v4l2_subdev *sd)
{
/*to fake*/
return 0;
}
static int tpg_s_power(struct v4l2_subdev *sd, int on)
{
return 0;
}
static int tpg_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
/*to fake*/
return 0;
}
static int tpg_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
/*to fake*/
return 0;
}
static int tpg_enum_frame_ival(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_interval_enum *fie)
{
/*to fake*/
return 0;
}
static const struct v4l2_subdev_video_ops tpg_video_ops = {
.s_stream = tpg_s_stream,
.g_parm = tpg_g_parm,
.s_parm = tpg_s_parm,
};
static const struct v4l2_subdev_core_ops tpg_core_ops = {
.log_status = tpg_log_status,
.s_power = tpg_s_power,
};
static const struct v4l2_subdev_pad_ops tpg_pad_ops = {
.enum_mbus_code = tpg_enum_mbus_code,
.enum_frame_size = tpg_enum_frame_size,
.enum_frame_interval = tpg_enum_frame_ival,
.get_fmt = tpg_get_fmt,
.set_fmt = tpg_set_fmt,
};
static const struct v4l2_subdev_ops tpg_ops = {
.core = &tpg_core_ops,
.video = &tpg_video_ops,
.pad = &tpg_pad_ops,
};
void atomisp_tpg_unregister_entities(struct atomisp_tpg_device *tpg)
{
media_entity_cleanup(&tpg->sd.entity);
v4l2_device_unregister_subdev(&tpg->sd);
}
int atomisp_tpg_register_entities(struct atomisp_tpg_device *tpg,
struct v4l2_device *vdev)
{
int ret;
/* Register the subdev and video nodes. */
ret = v4l2_device_register_subdev(vdev, &tpg->sd);
if (ret < 0)
goto error;
return 0;
error:
atomisp_tpg_unregister_entities(tpg);
return ret;
}
void atomisp_tpg_cleanup(struct atomisp_device *isp)
{
}
int atomisp_tpg_init(struct atomisp_device *isp)
{
struct atomisp_tpg_device *tpg = &isp->tpg;
struct v4l2_subdev *sd = &tpg->sd;
struct media_pad *pads = tpg->pads;
struct media_entity *me = &sd->entity;
int ret;
tpg->isp = isp;
v4l2_subdev_init(sd, &tpg_ops);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
strcpy(sd->name, "tpg_subdev");
v4l2_set_subdevdata(sd, tpg);
pads[0].flags = MEDIA_PAD_FL_SINK;
me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
ret = media_entity_pads_init(me, 1, pads);
if (ret < 0)
goto fail;
return 0;
fail:
atomisp_tpg_cleanup(isp);
return ret;
}

42
drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.h Normal file
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_TPG_H__
#define __ATOMISP_TPG_H__
#include <media/media-entity.h>
#include <media/v4l2-subdev.h>
struct atomisp_tpg_device {
struct v4l2_subdev sd;
struct atomisp_device *isp;
struct media_pad pads[1];
};
void atomisp_tpg_cleanup(struct atomisp_device *isp);
int atomisp_tpg_init(struct atomisp_device *isp);
void atomisp_tpg_unregister_entities(struct atomisp_tpg_device *tpg);
int atomisp_tpg_register_entities(struct atomisp_tpg_device *tpg,
struct v4l2_device *vdev);
#endif /* __ATOMISP_TPG_H__ */

133
drivers/staging/media/atomisp/pci/atomisp2/atomisp_trace_event.h Normal file
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/*
* Support Camera Imaging tracer core.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#undef TRACE_SYSTEM
#define TRACE_SYSTEM atomisp
#if !defined(ATOMISP_TRACE_EVENT_H) || defined(TRACE_HEADER_MULTI_READ)
#define ATOMISP_TRACE_EVENT_H
#include <linux/tracepoint.h>
#include <linux/string.h>
TRACE_EVENT(camera_meminfo,
TP_PROTO(const char *name, int uptr_size, int counter, int sys_size,
int sys_res_size, int cam_sys_use, int cam_dyc_use,
int cam_res_use),
TP_ARGS(name, uptr_size, counter, sys_size, sys_res_size, cam_sys_use,
cam_dyc_use, cam_res_use),
TP_STRUCT__entry(
__array(char, name, 24)
__field(int, uptr_size)
__field(int, counter)
__field(int, sys_size)
__field(int, sys_res_size)
__field(int, cam_res_use)
__field(int, cam_dyc_use)
__field(int, cam_sys_use)
),
TP_fast_assign(
strlcpy(__entry->name, name, 24);
__entry->uptr_size = uptr_size;
__entry->counter = counter;
__entry->sys_size = sys_size;
__entry->sys_res_size = sys_res_size;
__entry->cam_res_use = cam_res_use;
__entry->cam_dyc_use = cam_dyc_use;
__entry->cam_sys_use = cam_sys_use;
),
TP_printk(
"<%s> User ptr memory:%d pages,\tISP private memory used:%d"
" pages:\tsysFP system size:%d,\treserved size:%d"
"\tcamFP sysUse:%d,\tdycUse:%d,\tresUse:%d.\n",
__entry->name, __entry->uptr_size, __entry->counter,
__entry->sys_size, __entry->sys_res_size, __entry->cam_sys_use,
__entry->cam_dyc_use, __entry->cam_res_use)
);
TRACE_EVENT(camera_debug,
TP_PROTO(const char *name, char *info, const int line),
TP_ARGS(name, info, line),
TP_STRUCT__entry(
__array(char, name, 24)
__array(char, info, 24)
__field(int, line)
),
TP_fast_assign(
strlcpy(__entry->name, name, 24);
strlcpy(__entry->info, info, 24);
__entry->line = line;
),
TP_printk("<%s>-<%d> %s\n", __entry->name, __entry->line,
__entry->info)
);
TRACE_EVENT(ipu_cstate,
TP_PROTO(int cstate),
TP_ARGS(cstate),
TP_STRUCT__entry(
__field(int, cstate)
),
TP_fast_assign(
__entry->cstate = cstate;
),
TP_printk("cstate=%d", __entry->cstate)
);
TRACE_EVENT(ipu_pstate,
TP_PROTO(int freq, int util),
TP_ARGS(freq, util),
TP_STRUCT__entry(
__field(int, freq)
__field(int, util)
),
TP_fast_assign(
__entry->freq = freq;
__entry->util = util;
),
TP_printk("freq=%d util=%d", __entry->freq, __entry->util)
);
#endif
#undef TRACE_INCLUDE_PATH
#undef TRACE_INCLUDE_FILE
#define TRACE_INCLUDE_PATH .
#define TRACE_INCLUDE_FILE atomisp_trace_event
/* This part must be outside protection */
#include <trace/define_trace.h>

1649
drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.c Normal file
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File diff suppressed because it is too large Load Diff

44
drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.h Normal file
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@ -0,0 +1,44 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#ifndef __ATOMISP_V4L2_H__
#define __ATOMISP_V4L2_H__
struct atomisp_video_pipe;
struct atomisp_acc_pipe;
struct v4l2_device;
struct atomisp_device;
struct firmware;
int atomisp_video_init(struct atomisp_video_pipe *video, const char *name);
void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name);
void atomisp_video_unregister(struct atomisp_video_pipe *video);
int atomisp_video_register(struct atomisp_video_pipe *video,
struct v4l2_device *vdev);
void atomisp_acc_unregister(struct atomisp_acc_pipe *video);
int atomisp_acc_register(struct atomisp_acc_pipe *video,
struct v4l2_device *vdev);
const struct firmware *atomisp_load_firmware(struct atomisp_device *isp);
int atomisp_csi_lane_config(struct atomisp_device *isp);
#endif /* __ATOMISP_V4L2_H__ */

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