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arm64: dts: n5x: Add support for Intel's eASIC N5X platform
The Intel eASIC N5X platform shares the same register map as the Agilex platform, thus, we can re-use the socfpga_agilex.dtsi as the base DTSI. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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@ -13,6 +13,11 @@ config ARCH_AGILEX
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help
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This enables support for Intel's Agilex SoCFPGA Family.
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config ARCH_N5X
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bool "Intel's eASIC N5X SoCFPGA Family"
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help
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This enables support for Intel's eASIC N5X SoCFPGA Family.
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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@ -2,3 +2,4 @@
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dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
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socfpga_agilex_socdk_nand.dtb
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dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
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dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb
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53
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
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53
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
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@ -0,0 +1,53 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021, Intel Corporation
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*/
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#include "socfpga_agilex.dtsi"
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/ {
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model = "eASIC N5X SoCDK";
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aliases {
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serial0 = &uart0;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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soc {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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};
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&clkmgr {
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compatible = "intel,easic-n5x-clkmgr";
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};
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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broken-cd;
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bus-width = <4>;
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};
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&uart0 {
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status = "okay";
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};
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&watchdog0 {
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status = "okay";
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};
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