arm64: dts: n5x: Add support for Intel's eASIC N5X platform

The Intel eASIC N5X platform shares the same register map as the Agilex
platform, thus, we can re-use the socfpga_agilex.dtsi as the base
DTSI.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Dinh Nguyen 2020-12-07 14:43:01 -06:00
parent 62b3c680cf
commit a427485a00
3 changed files with 59 additions and 0 deletions

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@ -13,6 +13,11 @@ config ARCH_AGILEX
help
This enables support for Intel's Agilex SoCFPGA Family.
config ARCH_N5X
bool "Intel's eASIC N5X SoCFPGA Family"
help
This enables support for Intel's eASIC N5X SoCFPGA Family.
config ARCH_SUNXI
bool "Allwinner sunxi 64-bit SoC Family"
select ARCH_HAS_RESET_CONTROLLER

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@ -2,3 +2,4 @@
dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb

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@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
/ {
model = "eASIC N5X SoCDK";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
soc {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
};
};
&clkmgr {
compatible = "intel,easic-n5x-clkmgr";
};
&mmc {
status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
};
&uart0 {
status = "okay";
};
&watchdog0 {
status = "okay";
};