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dt-bindings: Changes for v5.20-rc1
These changes add clock, reset, memory client and power domain definitions for various devices found on Tegra234 along with a few device tree bindings for new hardware. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmLIeLYTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zodtBEACW4bu7bO2/aAQNOX4R0qUOM64nj9cE sqxo1A7JxxGQWBsjiVCD62nCnRP1ehqF2anVEdCJvh2eXlWHdhTgs/lV2HK712Ny otkgok/1pVKfvwTuziyqyOHyKD0j2ZoDJlRgYDTF+WUrVrXXnQyc32lt+zmibtH1 w3TIx6vx4FUnYJELNQPeqbbBP450eIGJ8fZBhIM68kqF/4HKVb4e2jofV3Gd1SBx wSBDW63nvqmvErmHfS9LVEX5GcRm0m4RvHWCMK61yc92BwlRKOlweTYczfZmw3oB feVtW59+yHYUWa9Dx7PATz7ns+YgpVI9ZU35NKT31/B0gLWh52kZuXFwA9g+02fE vq7qV3FhFZtyMBp8CaYopp1INCxU0xXTxvIRw+R00Y5Fab6XUGz+qKTDyHVfhkcD LtSHyWQ5h/PAUrcBaAALuvkU8ZCYvdOfTQMQBm5sUoTBMFQ7GsuvOmGy48HbWxLV n1SRZNNoXAKWK20Ko+ydLe5rAWpAKOb5onufPhm0JiGziVto/Q/qz9tsh+5lE0Gw v9W9poXoLlfwpAdLteAchKCgCGIuWims0XwRxVz8lvudEb6OUyMlr2eUNNYFMGsd SnPwHUO67fm6/hxA5NoHDuy0mdynJEcDXaJ+OORfezT/JILgIughAp51+/Whk88p ByXU/MOC+61yoA== =3/dX -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLMQ3IACgkQmmx57+YA GNldFQ//SrIZR5mCeRnLSZEdw5xah7TXwvIOvDw+4JQ3Fbrzq63L/ggm307q6WcC 4ymOP0ImzAxbHp7Vc5qb6wELSSIiGBy/4y3g/rVinK1ZFRqHiiOkVwHABQp5GMhM h/Xm3QVym9UDA4a0hy6EUREb5QHo0l/yYgsXoRJLfh1HuARswevAu2GK+Q4rEH1b 8aG8xm7fbhafhAJzzJkufOH6WHyhelP0zCVs9Ipa0oOcz1t0/cqYhLDQH/43r76z oN+NbEOuCxEShTAhEZ2K5F6lXtR1CB20BE4y5lfMebevSRIXjfN2XfQnJfcAcCY/ CfT0RCi0w4uz5ZgnkWhI+SbXNT7oHSDvdEogOI1yKm1tm0F8PqUKsPv3tL/P7H0D BcOmPslYP10iRuwXDZzbE5FgCZwjIacwJF24BLqI8nEr1U6aC13rwlnsB7mWk1E5 OXuo/1T0X8R34OrZQzkNpV2WAhT/jNMC5Pj01h0A2XAX0UGB2vP+P5wWurumMkwn V8VX82qN0FN6LOOnm+YgreLHv8uR6V95EzIDnvND3dyz0qvsajlIo1Q+PACsVUOA fBuxDd2/ABAMglqNNTZTg75PIosrbRqtaaZDq2ehlyWUjn4BGWaEv4W0zZBpyrZB CMUQ7ZBhJapvXoRxjOkkPU7WmfYo/CQtjxRkkBS03O+xNIZJxRo= =iDCl -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.20-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.20-rc1 These changes add clock, reset, memory client and power domain definitions for various devices found on Tegra234 along with a few device tree bindings for new hardware. * tag 'tegra-for-5.20-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: tegra-ccplex-cluster: Remove status from required properties dt-bindings: Add headers for Host1x and VIC on Tegra234 dt-bindings: timer: Add Tegra186 & Tegra234 Timer dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB 2.0 binding dt-bindings: arm: tegra: Add NVIDIA Tegra194 AXI2APB binding dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB 1.0 binding dt-bindings: memory: Add Tegra234 MGBE memory clients dt-bindings: Add Tegra234 MGBE clocks and resets dt-bindings: power: Add Tegra234 MGBE power domains dt-bindings: Add headers for Tegra234 GPCDMA Link: https://lore.kernel.org/r/20220708185608.676474-4-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
a41bf1aabd
@ -40,7 +40,6 @@ required:
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- compatible
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- reg
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- nvidia,bpmp
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- status
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examples:
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- |
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@ -0,0 +1,40 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra194 AXI2APB bridge
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maintainers:
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- Sumit Gupta <sumitg@nvidia.com>
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properties:
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$nodename:
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pattern: "^axi2apb@([0-9a-f]+)$"
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compatible:
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enum:
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- nvidia,tegra194-axi2apb
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reg:
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maxItems: 6
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description: Physical base address and length of registers for all bridges
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additionalProperties: false
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required:
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- compatible
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- reg
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examples:
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- |
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axi2apb: axi2apb@2390000 {
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compatible = "nvidia,tegra194-axi2apb";
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reg = <0x02390000 0x1000>,
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<0x023a0000 0x1000>,
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<0x023b0000 0x1000>,
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<0x023c0000 0x1000>,
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<0x023d0000 0x1000>,
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<0x023e0000 0x1000>;
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};
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@ -0,0 +1,97 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra194 CBB 1.0 bindings
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maintainers:
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- Sumit Gupta <sumitg@nvidia.com>
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description: |+
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The Control Backbone (CBB) is comprised of the physical path from an
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initiator to a target's register configuration space. CBB 1.0 has
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multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
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initiators and targets using different bridges like AXIP2P, AXI2APB.
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This driver handles errors due to illegal register accesses reported
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by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
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"AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
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which is the main NOC.
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By default, the access issuing initiator is informed about the error
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using SError or Data Abort exception unless the ERD (Error Response
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Disable) is enabled/set for that initiator. If the ERD is enabled, then
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SError or Data Abort is masked and the error is reported with interrupt.
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- For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
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errors due to illegal accesses from CCPLEX are reported by interrupts.
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If ERD is not set, then error is reported by SError.
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- For other initiators, the ERD is disabled. So, the access issuing
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initiator is informed about the illegal access by Data Abort exception.
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In addition, an interrupt is also generated to CCPLEX. These initiators
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include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
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engine) etc which can initiate transactions.
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The driver prints relevant debug information like Error Code, Error
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Description, Master, Address, AXI ID, Cache, Protection, Security Group
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etc on receiving error notification.
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properties:
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$nodename:
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pattern: "^[a-z]+-noc@[0-9a-f]+$"
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compatible:
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enum:
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- nvidia,tegra194-cbb-noc
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- nvidia,tegra194-aon-noc
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- nvidia,tegra194-bpmp-noc
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- nvidia,tegra194-rce-noc
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- nvidia,tegra194-sce-noc
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reg:
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maxItems: 1
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interrupts:
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description:
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CCPLEX receives secure or nonsecure interrupt depending on error type.
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A secure interrupt is received for SEC(firewall) & SLV errors and a
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non-secure interrupt is received for TMO & DEC errors.
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items:
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- description: non-secure interrupt
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- description: secure interrupt
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nvidia,axi2apb:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description:
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Specifies the node having all axi2apb bridges which need to be checked
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for any error logged in their status register.
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nvidia,apbmisc:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description:
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Specifies the apbmisc node which need to be used for reading the ERD
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register.
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- nvidia,apbmisc
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cbb-noc@2300000 {
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compatible = "nvidia,tegra194-cbb-noc";
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reg = <0x02300000 0x1000>;
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interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,axi2apb = <&axi2apb>;
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nvidia,apbmisc = <&apbmisc>;
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};
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@ -0,0 +1,74 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra CBB 2.0 bindings
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maintainers:
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- Sumit Gupta <sumitg@nvidia.com>
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description: |+
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The Control Backbone (CBB) is comprised of the physical path from an
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initiator to a target's register configuration space. CBB 2.0 consists
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of multiple sub-blocks connected to each other to create a topology.
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The Tegra234 SoC has different fabrics based on CBB 2.0 architecture
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which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
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"CBB central fabric".
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In CBB 2.0, each initiator which can issue transactions connects to a
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Root Master Node (MN) before it connects to any other element of the
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fabric. Each Root MN contains a Error Monitor (EM) which detects and
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logs error. Interrupts from various EM blocks are collated by Error
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Notifier (EN) which is per fabric and presents a single interrupt from
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fabric to the SoC interrupt controller.
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The driver handles errors from CBB due to illegal register accesses
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and prints debug information about failed transaction on receiving
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the interrupt from EN. Debug information includes Error Code, Error
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Description, MasterID, Fabric, SlaveID, Address, Cache, Protection,
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Security Group etc on receiving error notification.
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If the Error Response Disable (ERD) is set/enabled for an initiator,
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then SError or Data abort exception error response is masked and an
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interrupt is used for reporting errors due to illegal accesses from
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that initiator. The value returned on read failures is '0xFFFFFFFF'
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for compatibility with PCIE.
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properties:
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$nodename:
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pattern: "^[a-z]+-fabric@[0-9a-f]+$"
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compatible:
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enum:
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- nvidia,tegra234-aon-fabric
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- nvidia,tegra234-bpmp-fabric
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- nvidia,tegra234-cbb-fabric
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- nvidia,tegra234-dce-fabric
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- nvidia,tegra234-rce-fabric
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- nvidia,tegra234-sce-fabric
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: secure interrupt from error notifier
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cbb-fabric@1300000 {
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compatible = "nvidia,tegra234-cbb-fabric";
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reg = <0x13a00000 0x400000>;
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interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -0,0 +1,109 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra186 timer
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maintainers:
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- Thierry Reding <treding@nvidia.com>
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description: >
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The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
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counter. Each NV timer selects its timing reference signal from the 1 MHz
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reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
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programmed to generate one-shot, periodic, or watchdog interrupts.
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properties:
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compatible:
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oneOf:
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- const: nvidia,tegra186-timer
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description: >
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The Tegra186 timer provides ten 29-bit timer counters.
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- const: nvidia,tegra234-timer
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description: >
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The Tegra234 timer provides sixteen 29-bit timer counters.
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reg:
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maxItems: 1
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interrupts: true
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra186-timer
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then:
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properties:
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interrupts:
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maxItems: 10
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description: >
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One per each timer channels 0 through 9.
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- if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra234-timer
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then:
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properties:
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interrupts:
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maxItems: 16
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description: >
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One per each timer channels 0 through 15.
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@3010000 {
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compatible = "nvidia,tegra186-timer";
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reg = <0x03010000 0x000e0000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@2080000 {
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compatible = "nvidia,tegra234-timer";
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reg = <0x02080000 0x00121000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -38,6 +38,8 @@
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* throughput and memory controller power.
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*/
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#define TEGRA234_CLK_EMC 31U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
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#define TEGRA234_CLK_HOST1X 46U
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/** @brief output of gate CLK_ENB_FUSE */
|
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#define TEGRA234_CLK_FUSE 40U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
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@ -132,6 +134,8 @@
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#define TEGRA234_CLK_UARTA 155U
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/** @brief output of gate CLK_ENB_PEX1_CORE_6 */
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#define TEGRA234_CLK_PEX1_C6_CORE 161U
|
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
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#define TEGRA234_CLK_VIC 167U
|
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/** @brief output of gate CLK_ENB_PEX2_CORE_7 */
|
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#define TEGRA234_CLK_PEX2_C7_CORE 171U
|
||||
/** @brief output of gate CLK_ENB_PEX2_CORE_8 */
|
||||
@ -164,10 +168,111 @@
|
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#define TEGRA234_CLK_PEX1_C5_CORE 225U
|
||||
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
|
||||
#define TEGRA234_CLK_PLLC4 237U
|
||||
/** @brief RX clock recovered from MGBE0 lane input */
|
||||
#define TEGRA234_CLK_MGBE0_RX_INPUT 248U
|
||||
/** @brief RX clock recovered from MGBE1 lane input */
|
||||
#define TEGRA234_CLK_MGBE1_RX_INPUT 249U
|
||||
/** @brief RX clock recovered from MGBE2 lane input */
|
||||
#define TEGRA234_CLK_MGBE2_RX_INPUT 250U
|
||||
/** @brief RX clock recovered from MGBE3 lane input */
|
||||
#define TEGRA234_CLK_MGBE3_RX_INPUT 251U
|
||||
/** @brief 32K input clock provided by PMIC */
|
||||
#define TEGRA234_CLK_CLK_32K 289U
|
||||
/** @brief Monitored branch of MBGE0 RX input clock */
|
||||
#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U
|
||||
/** @brief Monitored branch of MBGE1 RX input clock */
|
||||
#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U
|
||||
/** @brief Monitored branch of MBGE2 RX input clock */
|
||||
#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U
|
||||
/** @brief Monitored branch of MBGE3 RX input clock */
|
||||
#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U
|
||||
/** @brief Monitored branch of MGBE0 RX PCS mux output */
|
||||
#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U
|
||||
/** @brief Monitored branch of MGBE1 RX PCS mux output */
|
||||
#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U
|
||||
/** @brief Monitored branch of MGBE2 RX PCS mux output */
|
||||
#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U
|
||||
/** @brief Monitored branch of MGBE3 RX PCS mux output */
|
||||
#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U
|
||||
/** @brief RX PCS clock recovered from MGBE0 lane input */
|
||||
#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U
|
||||
/** @brief RX PCS clock recovered from MGBE1 lane input */
|
||||
#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U
|
||||
/** @brief RX PCS clock recovered from MGBE2 lane input */
|
||||
#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U
|
||||
/** @brief RX PCS clock recovered from MGBE3 lane input */
|
||||
#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U
|
||||
/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
|
||||
#define TEGRA234_CLK_MGBE0_RX_PCS 373U
|
||||
/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE0_TX 374U
|
||||
/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE0_TX_PCS 375U
|
||||
/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
|
||||
#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U
|
||||
/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE0_MAC 377U
|
||||
/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE0_MACSEC 378U
|
||||
/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE0_EEE_PCS 379U
|
||||
/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE0_APP 380U
|
||||
/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE0_PTP_REF 381U
|
||||
/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
|
||||
#define TEGRA234_CLK_MGBE1_RX_PCS 382U
|
||||
/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE1_TX 383U
|
||||
/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE1_TX_PCS 384U
|
||||
/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
|
||||
#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U
|
||||
/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE1_MAC 386U
|
||||
/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE1_EEE_PCS 388U
|
||||
/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE1_APP 389U
|
||||
/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE1_PTP_REF 390U
|
||||
/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
|
||||
#define TEGRA234_CLK_MGBE2_RX_PCS 391U
|
||||
/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE2_TX 392U
|
||||
/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE2_TX_PCS 393U
|
||||
/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
|
||||
#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U
|
||||
/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE2_MAC 395U
|
||||
/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE2_EEE_PCS 397U
|
||||
/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE2_APP 398U
|
||||
/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE2_PTP_REF 399U
|
||||
/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
|
||||
#define TEGRA234_CLK_MGBE3_RX_PCS 400U
|
||||
/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE3_TX 401U
|
||||
/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE3_TX_PCS 402U
|
||||
/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
|
||||
#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U
|
||||
/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE3_MAC 404U
|
||||
/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE3_MACSEC 405U
|
||||
/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE3_EEE_PCS 406U
|
||||
/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE3_APP 407U
|
||||
/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE3_PTP_REF 408U
|
||||
/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
|
||||
#define TEGRA234_CLK_AZA_2XBIT 457U
|
||||
/** @brief aza_2xbitclk / 2 (aza_bitclk) */
|
||||
#define TEGRA234_CLK_AZA_BIT 458U
|
||||
|
||||
#endif
|
||||
|
||||
@ -11,11 +11,16 @@
|
||||
/* NISO0 stream IDs */
|
||||
#define TEGRA234_SID_APE 0x02
|
||||
#define TEGRA234_SID_HDA 0x03
|
||||
#define TEGRA234_SID_GPCDMA 0x04
|
||||
#define TEGRA234_SID_MGBE 0x06
|
||||
#define TEGRA234_SID_PCIE0 0x12
|
||||
#define TEGRA234_SID_PCIE4 0x13
|
||||
#define TEGRA234_SID_PCIE5 0x14
|
||||
#define TEGRA234_SID_PCIE6 0x15
|
||||
#define TEGRA234_SID_PCIE9 0x1f
|
||||
#define TEGRA234_SID_MGBE_VF1 0x49
|
||||
#define TEGRA234_SID_MGBE_VF2 0x4a
|
||||
#define TEGRA234_SID_MGBE_VF3 0x4b
|
||||
|
||||
/* NISO1 stream IDs */
|
||||
#define TEGRA234_SID_SDMMC4 0x02
|
||||
@ -26,6 +31,8 @@
|
||||
#define TEGRA234_SID_PCIE8 0x09
|
||||
#define TEGRA234_SID_PCIE10 0x0b
|
||||
#define TEGRA234_SID_BPMP 0x10
|
||||
#define TEGRA234_SID_HOST1X 0x27
|
||||
#define TEGRA234_SID_VIC 0x34
|
||||
|
||||
/*
|
||||
* memory client IDs
|
||||
@ -33,6 +40,7 @@
|
||||
|
||||
/* High-definition audio (HDA) read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
|
||||
#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16
|
||||
/* PCIE6 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
|
||||
/* PCIE6 write clients */
|
||||
@ -61,10 +69,28 @@
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
|
||||
/* PCIE7r1 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
|
||||
/* MGBE0 read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
|
||||
/* MGBEB read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
|
||||
/* MGBEC read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
|
||||
/* MGBED read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
|
||||
/* MGBE0 write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
|
||||
/* MGBEB write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
|
||||
/* MGBEC write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
|
||||
/* sdmmcd memory read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
|
||||
/* MGBED write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
|
||||
/* sdmmcd memory write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
|
||||
#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c
|
||||
#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d
|
||||
/* BPMP read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
|
||||
/* BPMP write client */
|
||||
|
||||
@ -18,5 +18,7 @@
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEA 17U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEB 18U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEC 19U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBED 20U
|
||||
#define TEGRA234_POWER_DOMAIN_VIC 29U
|
||||
|
||||
#endif
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#define TEGRA234_RESET_PEX1_COMMON_APB 13U
|
||||
#define TEGRA234_RESET_PEX2_CORE_7 14U
|
||||
#define TEGRA234_RESET_PEX2_CORE_7_APB 15U
|
||||
#define TEGRA234_RESET_GPCDMA 18U
|
||||
#define TEGRA234_RESET_HDA 20U
|
||||
#define TEGRA234_RESET_HDACODEC 21U
|
||||
#define TEGRA234_RESET_I2C1 24U
|
||||
@ -29,6 +30,12 @@
|
||||
#define TEGRA234_RESET_I2C7 33U
|
||||
#define TEGRA234_RESET_I2C8 34U
|
||||
#define TEGRA234_RESET_I2C9 35U
|
||||
#define TEGRA234_RESET_MGBE0_PCS 45U
|
||||
#define TEGRA234_RESET_MGBE0_MAC 46U
|
||||
#define TEGRA234_RESET_MGBE1_PCS 49U
|
||||
#define TEGRA234_RESET_MGBE1_MAC 50U
|
||||
#define TEGRA234_RESET_MGBE2_PCS 53U
|
||||
#define TEGRA234_RESET_MGBE2_MAC 54U
|
||||
#define TEGRA234_RESET_PEX2_CORE_10 56U
|
||||
#define TEGRA234_RESET_PEX2_CORE_10_APB 57U
|
||||
#define TEGRA234_RESET_PEX2_COMMON_APB 58U
|
||||
@ -43,7 +50,10 @@
|
||||
#define TEGRA234_RESET_QSPI0 76U
|
||||
#define TEGRA234_RESET_QSPI1 77U
|
||||
#define TEGRA234_RESET_SDMMC4 85U
|
||||
#define TEGRA234_RESET_MGBE3_PCS 87U
|
||||
#define TEGRA234_RESET_MGBE3_MAC 88U
|
||||
#define TEGRA234_RESET_UARTA 100U
|
||||
#define TEGRA234_RESET_VIC 113U
|
||||
#define TEGRA234_RESET_PEX0_CORE_0 116U
|
||||
#define TEGRA234_RESET_PEX0_CORE_1 117U
|
||||
#define TEGRA234_RESET_PEX0_CORE_2 118U
|
||||
|
||||
Loading…
Reference in New Issue
Block a user