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drm/amd/display: Fix CW4 programming for dmub30 cached inbox

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[Why]
The conditions for whether we used cached vs non-cached inbox1 depend
on a version check that mismatches what the shared helpers in dmub20
implement.

[How]
Use the dmub_dcn20_use_cached_inbox check for dmub_dcn30 as well.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2021-01-19 14:46:21 -05:00 committed by Alex Deucher
parent 163e3bcbca
commit a38b873f49
3 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
View File

@ -81,7 +81,7 @@ static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
}
static inline bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
{
/* Cached inbox is not supported in this fw version range */
return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&

2
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
View File

@ -198,4 +198,6 @@ void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);
bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);
#endif /* _DMUB_DCN20_H_ */

2
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
View File

@ -155,7 +155,7 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
offset = cw4->offset;
/* New firmware can support CW4. */
if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10)) {
if (dmub_dcn20_use_cached_inbox(dmub)) {
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);