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ARM: dts: meson: add the hardware random number generator

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All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2017-06-15 23:33:49 +02:00 committed by Kevin Hilman
parent 8a7f0c52e8
commit a35910d399
3 changed files with 17 additions and 0 deletions
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5
arch/arm/boot/dts/meson.dtsi
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@ -80,6 +80,11 @@
#size-cells = <1>;
ranges = <0x0 0xc1100000 0x200000>;
hwrng: rng@8100 {
compatible = "amlogic,meson-rng";
reg = <0x8100 0x8>;
};
uart_A: serial@84c0 {
compatible = "amlogic,meson-uart";
reg = <0x84c0 0x18>;

6
arch/arm/boot/dts/meson8.dtsi
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@ -241,6 +241,12 @@
clock-names = "stmmaceth";
};
&hwrng {
compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
&i2c_AO {
clocks = <&clkc CLKID_CLK81>;
};

6
arch/arm/boot/dts/meson8b.dtsi
View File

@ -171,6 +171,12 @@
};
};
&hwrng {
compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
&L2 {
arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>;