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ASoC: tegra: fix maxburst settings in dmaengine code

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The I2S controllers are programmed with an "attention" level of 4 DWORDs.
This must match the configuration passed to the DMA driver, so that when
they burst in data, they don't overflow the available FIFO space. Also,
the burst size is relevant to the destination for playback, and source
for capture, not vice-versa as originally written.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Stephen Warren 2012-09-06 17:47:33 -06:00 committed by Mark Brown
parent 57b2d68863
commit a32826e4ae
1 changed files with 2 additions and 2 deletions
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4
sound/soc/tegra/tegra_pcm.c
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@ -334,11 +334,11 @@ static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
slave_config.dst_addr = dmap->addr;
slave_config.src_maxburst = 0;
slave_config.dst_maxburst = 4;
} else {
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
slave_config.src_addr = dmap->addr;
slave_config.dst_maxburst = 0;
slave_config.src_maxburst = 4;
}
slave_config.slave_id = dmap->req_sel;