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- Device Tree implementation for the ARM RealView boards
- DTS file for the ARM RealView PB1176 - Updates on top of the same DTS file -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUR5sZAAoJEEEQszewGV1zEFoP/iqRbD//O4ul8jMNMwrRXw5W y6vO8jPPImZm9PSz/KGpx/W/HUXZOZpyja8HgD9v8345jQYhtzFQTagXerNDEMRR YXU2CnAPCLoowu/pI+ImNh9rVehGBszzZxEHuBZJq0GAhum6JvaTu3tUWKxfAaqO hRfPLchHhHhduzdivHuq2ghmrzYcWM9T8T7MN/8fwI4cnkPaOhPgfIFSD49IydP3 tx2OaUKVbThw+4t01hD9Ojjj418Cgxl1JNWp55qmQS5l7WMqR885kax1b3OYaStZ 3vTpbgvQVY/Ht+NFZVE9nNbqGudwCAa8AfhRprHHQ2eaCL/EF35xKtzV7Qr+PwaJ jLogO3LlHBsTkkM+UGGz75aclwbyoCcwskqfRefxLRH5ZShIK4noe12Q/DTkR9wB lCVEnEtEcMQlVkso/yTZj6u2emQn0mmPDm+HHlK916E4/UlwN7nC47IpNHwtl6fT ELAi/7/YoWc+VpdkAjRMKkbK5Aw3m3WhwbG1hGEwscfDmkfJ+gjbmieJJxoEUqEI fIZ3uw7Vvn3hxEAJgT/Nf8z9j0r8qq8/EfzsJucH3sVI9dqAcaNPoPRvixtDM+p3 WgpE+pe9BfE/iD5wYkxoe3vKovqe2vLIcsh+UgPEaFOKpmwV4sdCAaEoEbPI15VH S7aSrXpVBZpnypMgS/vA =ubCW -----END PGP SIGNATURE----- Merge tag 'arm-realview-dt-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt Merge "RealView DeviceTree support for v3.19" from Linus Walleij: - Device Tree implementation for the ARM RealView boards - DTS file for the ARM RealView PB1176 - Updates on top of the same DTS file * tag 'arm-realview-dt-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: realview: add MMCI to the PB1176 DTS ARM: realview: add KMIs to the PB1176 DTS ARM: realview: add FPGA UART4 to PB1176 DTS ARM: realview: add PL022 SSP/SPI block to PB1176 DTS ARM: realview: add RTC clocks to device tree ARM: realview: add charlcd to PB1176 device tree ARM: realview: add PL061 GPIO to the PB1176 DTS ARM: realview: move DT GIC to FPGA node ARM: realview: add device tree and bindings for PB1176 ARM: realview: basic device tree implementation Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
a3206509f6
@ -92,3 +92,68 @@ Required nodes:
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- core-module: the root node to the Versatile platforms must have
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a core-module with regs and the compatible strings
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"arm,core-module-versatile", "syscon"
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ARM RealView Boards
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-------------------
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The RealView boards cover tailored evaluation boards that are used to explore
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the ARM11 and Cortex A-8 and Cortex A-9 processors.
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Required properties (in root node):
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/* RealView Emulation Baseboard */
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compatible = "arm,realview-eb";
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/* RealView Platform Baseboard for ARM1176JZF-S */
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compatible = "arm,realview-pb1176";
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/* RealView Platform Baseboard for ARM11 MPCore */
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compatible = "arm,realview-pb11mp";
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/* RealView Platform Baseboard for Cortex A-8 */
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compatible = "arm,realview-pba8";
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/* RealView Platform Baseboard Explore for Cortex A-9 */
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compatible = "arm,realview-pbx";
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Required nodes:
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- soc: some node of the RealView platforms must be the SoC
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node that contain the SoC-specific devices, withe the compatible
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string set to one of these tuples:
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"arm,realview-eb-soc", "simple-bus"
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"arm,realview-pb1176-soc", "simple-bus"
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"arm,realview-pb11mp-soc", "simple-bus"
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"arm,realview-pba8-soc", "simple-bus"
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"arm,realview-pbx-soc", "simple-bus"
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- syscon: some subnode of the RealView SoC node must be a
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system controller node pointing to the control registers,
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with the compatible string set to one of these tuples:
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"arm,realview-eb-syscon", "syscon"
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"arm,realview-pb1176-syscon", "syscon"
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"arm,realview-pb11mp-syscon", "syscon"
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"arm,realview-pba8-syscon", "syscon"
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"arm,realview-pbx-syscon", "syscon"
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Required properties for the system controller:
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- regs: the location and size of the system controller registers,
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one range of 0x1000 bytes.
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Example:
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "skeleton.dtsi"
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/ {
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model = "ARM RealView PB1176 with device tree";
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compatible = "arm,realview-pb1176";
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,realview-pb1176-soc", "simple-bus";
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ranges;
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syscon: syscon@10000000 {
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compatible = "arm,realview-syscon", "syscon";
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reg = <0x10000000 0x1000>;
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};
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};
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};
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@ -17,6 +17,7 @@ Main node required properties:
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"arm,cortex-a7-gic"
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"arm,arm11mp-gic"
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"brcm,brahma-b15-gic"
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"arm,arm1176jzf-devchip-gic"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 3.
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@ -364,6 +364,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-msm8974-sony-xperia-honami.dtb
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dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk3066a-bqcurie2.dtb \
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rk3188-radxarock.dtb \
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412
arch/arm/boot/dts/arm-realview-pb1176.dts
Normal file
412
arch/arm/boot/dts/arm-realview-pb1176.dts
Normal file
@ -0,0 +1,412 @@
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/*
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* Copyright 2014 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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/ {
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model = "ARM RealView PB1176";
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compatible = "arm,realview-pb1176";
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chosen { };
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aliases {
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serial0 = &pb1176_serial0;
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serial1 = &pb1176_serial1;
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serial2 = &pb1176_serial2;
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serial3 = &pb1176_serial3;
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serial4 = &fpga_serial;
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};
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memory {
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/* 128 MiB memory @ 0x0 */
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reg = <0x00000000 0x08000000>;
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};
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/* The voltage to the MMC card is hardwired at 3.3V */
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vmmc: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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timclk: timclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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mclk: mclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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kmiclk: kmiclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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sspclk: sspclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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uartclk: uartclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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/* FIXME: this actually hangs off the PLL clocks */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,realview-pb1176-soc", "simple-bus";
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regmap = <&syscon>;
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ranges;
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syscon: syscon@10000000 {
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compatible = "arm,realview-pb1176-syscon", "syscon";
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reg = <0x10000000 0x1000>;
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led@08.0 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x01>;
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label = "versatile:0";
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linux,default-trigger = "heartbeat";
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default-state = "on";
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};
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led@08.1 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x02>;
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label = "versatile:1";
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linux,default-trigger = "mmc0";
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default-state = "off";
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};
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led@08.2 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x04>;
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label = "versatile:2";
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linux,default-trigger = "cpu0";
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default-state = "off";
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};
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led@08.3 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x08>;
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label = "versatile:3";
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default-state = "off";
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};
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led@08.4 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x10>;
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label = "versatile:4";
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default-state = "off";
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};
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led@08.5 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x20>;
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label = "versatile:5";
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default-state = "off";
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};
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led@08.6 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x40>;
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label = "versatile:6";
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default-state = "off";
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};
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led@08.7 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x80>;
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label = "versatile:7";
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default-state = "off";
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};
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};
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/* Primary DevChip GIC synthesized with the CPU */
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intc_dc1176: interrupt-controller@10120000 {
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compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x10121000 0x1000>,
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<0x10120000 0x100>;
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};
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L2: l2-cache {
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compatible = "arm,l220-cache";
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reg = <0x10110000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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/*
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* Override default cache size, sets and
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* associativity as these may be erroneously set
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* up by boot loader(s).
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*/
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arm,override-auxreg;
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cache-size = <131072>; // 128kB
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cache-sets = <512>;
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cache-line-size = <32>;
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};
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pmu {
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compatible = "arm,arm1176-pmu";
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer01: timer@10104000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x10104000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&timclk>, <&timclk>, <&pclk>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer23: timer@10105000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x10105000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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arm,sp804-has-irq = <1>;
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clocks = <&timclk>, <&timclk>, <&pclk>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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pb1176_rtc: rtc@10108000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x10108000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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pb1176_gpio0: gpio@1010a000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x1010a000 0x1000>;
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gpio-controller;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
|
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};
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pb1176_ssp: ssp@1010b000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x1010b000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
|
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&sspclk>, <&pclk>;
|
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clock-names = "SSPCLK", "apb_pclk";
|
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};
|
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|
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pb1176_serial0: serial@1010c000 {
|
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compatible = "arm,pl011", "arm,primecell";
|
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reg = <0x1010c000 0x1000>;
|
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interrupt-parent = <&intc_dc1176>;
|
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interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&uartclk>, <&pclk>;
|
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clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
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pb1176_serial1: serial@1010d000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1010d000 0x1000>;
|
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interrupt-parent = <&intc_dc1176>;
|
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interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
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clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_serial2: serial@1010e000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1010e000 0x1000>;
|
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interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_serial3: serial@1010f000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1010f000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
/* These peripherals are inside the FPGA rather than the DevChip */
|
||||
fpga {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
fpga_mci: mmcsd@10005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x10005000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
/* Due to frequent FIFO overruns, use just 500 kHz */
|
||||
max-frequency = <500000>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
clocks = <&mclk>, <&pclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
vmmc-supply = <&vmmc>;
|
||||
cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
fpga_kmi0: kmi@10006000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10006000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_kmi1: kmi@10007000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10007000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_charlcd: charlcd@10008000 {
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_serial: serial@10009000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x10009000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
/* This GIC on the board is cascaded off the DevChip GIC */
|
||||
intc_fpga1176: interrupt-controller@10040000 {
|
||||
compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x10041000 0x1000>,
|
||||
<0x10040000 0x100>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
fpga_gpio0: gpio@10014000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10014000 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_gpio1: gpio@10015000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10015000 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_rtc: rtc@10017000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x10017000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
|
||||
};
|
||||
};
|
||||
@ -1,6 +1,19 @@
|
||||
menu "RealView platform type"
|
||||
depends on ARCH_REALVIEW
|
||||
|
||||
config REALVIEW_DT
|
||||
bool "Support RealView(R) Device Tree based boot"
|
||||
select ARM_GIC
|
||||
select MFD_SYSCON
|
||||
select POWER_RESET
|
||||
select POWER_RESET_VERSATILE
|
||||
select POWER_SUPPLY
|
||||
select SOC_REALVIEW
|
||||
select USE_OF
|
||||
help
|
||||
Include support for booting the ARM(R) RealView(R) evaluation
|
||||
boards using a device tree machine description.
|
||||
|
||||
config MACH_REALVIEW_EB
|
||||
bool "Support RealView(R) Emulation Baseboard"
|
||||
select ARM_GIC
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
#
|
||||
|
||||
obj-y := core.o
|
||||
obj-$(CONFIG_REALVIEW_DT) += realview-dt.o
|
||||
obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
|
||||
obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o
|
||||
obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o
|
||||
|
||||
32
arch/arm/mach-realview/realview-dt.c
Normal file
32
arch/arm/mach-realview/realview-dt.c
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Linaro Ltd.
|
||||
*
|
||||
* Author: Linus Walleij <linus.walleij@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include "core.h"
|
||||
|
||||
static const char *realview_dt_platform_compat[] __initconst = {
|
||||
"arm,realview-eb",
|
||||
"arm,realview-pb1176",
|
||||
"arm,realview-pb11mp",
|
||||
"arm,realview-pba8",
|
||||
"arm,realview-pbx",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(REALVIEW_DT, "ARM RealView Machine (Device Tree Support)")
|
||||
#ifdef CONFIG_ZONE_DMA
|
||||
.dma_zone_size = SZ_256M,
|
||||
#endif
|
||||
.dt_compat = realview_dt_platform_compat,
|
||||
.l2c_aux_val = 0x0,
|
||||
.l2c_aux_mask = ~0x0,
|
||||
MACHINE_END
|
||||
@ -1041,6 +1041,8 @@ gic_of_init(struct device_node *node, struct device_node *parent)
|
||||
return 0;
|
||||
}
|
||||
IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
|
||||
IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
|
||||
IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
|
||||
IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
|
||||
IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
|
||||
IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user