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ARM: mach-shmobile: sh7372 INTCS MFIS2 interrupt update
Enable the MFIS2 interrupt source in the INTCS interrupt controller included in the sh7372 processor. The priority field is constantly enabled to let the interrupt through to both the ARM side and the SH side. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -365,6 +365,7 @@ static struct intc_desc intca_desc __initdata = {
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enum {
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UNUSED_INTCS = 0,
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ENABLED_INTCS,
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INTCS,
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@ -413,7 +414,7 @@ enum {
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CMT4,
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DSITX1_DSITX1_0,
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DSITX1_DSITX1_1,
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/* MFIS2 */
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MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
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CPORTS2R,
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/* CEC */
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JPU6E,
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@ -477,7 +478,7 @@ static struct intc_vect intcs_vectors[] = {
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INTCS_VECT(CMT4, 0x1980),
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INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
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INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
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/* MFIS2 */
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INTCS_VECT(MFIS2_INTCS, 0x1a00),
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INTCS_VECT(CPORTS2R, 0x1a20),
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/* CEC */
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INTCS_VECT(JPU6E, 0x1a80),
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@ -543,7 +544,7 @@ static struct intc_mask_reg intcs_mask_registers[] = {
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{ 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
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CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
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{ 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
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{ 0, CPORTS2R, 0, 0,
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{ MFIS2_INTCS, CPORTS2R, 0, 0,
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JPU6E, 0, 0, 0 } },
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{ 0xffd20104, 0, 16, /* INTAMASK */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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@ -571,7 +572,8 @@ static struct intc_prio_reg intcs_prio_registers[] = {
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{ 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
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{ 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
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DSITX1_DSITX1_1, 0 } },
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{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
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{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
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0, 0 } },
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{ 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
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};
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@ -590,6 +592,7 @@ static struct resource intcs_resources[] __initdata = {
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static struct intc_desc intcs_desc __initdata = {
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.name = "sh7372-intcs",
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.force_enable = ENABLED_INTCS,
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.resource = intcs_resources,
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.num_resources = ARRAY_SIZE(intcs_resources),
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.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
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