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powerpc/powernv: Fix SMT4 forcing idle code
The PSSCR value is not stored to PACA_REQ_PSSCR if the CPU does not
have the XER[SO] bug.
Fix this by storing up-front, outside the workaround code. The initial
test is not required because it is a slow path.
The workaround is made to depend on CONFIG_KVM_BOOK3S_HV_POSSIBLE, to
match pnv_power9_force_smt4_catch() where it is used. Drop the comment
on pnv_power9_force_smt4_catch() as it's no longer true.
Fixes: 7672691a08
("powerpc/powernv: Provide a way to force a core into SMT4 mode")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
parent
b6f534d1a6
commit
a2b5e056b7
@ -442,20 +442,20 @@ _GLOBAL(power9_offline_stop)
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* r3 contains desired PSSCR register value.
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*/
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_GLOBAL(power9_idle_stop)
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BEGIN_FTR_SECTION
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lwz r5, PACA_DONT_STOP(r13)
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cmpwi r5, 0
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bne 1f
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std r3, PACA_REQ_PSSCR(r13)
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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BEGIN_FTR_SECTION
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sync
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lwz r5, PACA_DONT_STOP(r13)
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cmpwi r5, 0
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bne 1f
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END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
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#endif
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mtspr SPRN_PSSCR,r3
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LOAD_REG_ADDR(r4,power_enter_stop)
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b pnv_powersave_common
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/* No return */
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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1:
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/*
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* We get here when TM / thread reconfiguration bug workaround
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@ -465,6 +465,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
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li r3, 0
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std r3, PACA_REQ_PSSCR(r13)
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blr /* return 0 for wakeup cause / SRR1 value */
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#endif
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/*
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* On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
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@ -397,10 +397,6 @@ void power9_idle(void)
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* all other threads not to stop, and sending a message to any
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* that are in a stop state.
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* Must be called with preemption disabled.
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*
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* DO NOT call this unless cpu_has_feature(CPU_FTR_P9_TM_XER_SO_BUG) is
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* true; otherwise this function will hang the system, due to the
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* optimization in power9_idle_stop.
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*/
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void pnv_power9_force_smt4_catch(void)
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{
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