powerpc/powernv: Fix SMT4 forcing idle code

The PSSCR value is not stored to PACA_REQ_PSSCR if the CPU does not
have the XER[SO] bug.

Fix this by storing up-front, outside the workaround code. The initial
test is not required because it is a slow path.

The workaround is made to depend on CONFIG_KVM_BOOK3S_HV_POSSIBLE, to
match pnv_power9_force_smt4_catch() where it is used. Drop the comment
on pnv_power9_force_smt4_catch() as it's no longer true.

Fixes: 7672691a08 ("powerpc/powernv: Provide a way to force a core into SMT4 mode")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Nicholas Piggin 2018-04-01 15:38:13 +10:00 committed by Michael Ellerman
parent b6f534d1a6
commit a2b5e056b7
2 changed files with 5 additions and 8 deletions

View File

@ -442,20 +442,20 @@ _GLOBAL(power9_offline_stop)
* r3 contains desired PSSCR register value.
*/
_GLOBAL(power9_idle_stop)
BEGIN_FTR_SECTION
lwz r5, PACA_DONT_STOP(r13)
cmpwi r5, 0
bne 1f
std r3, PACA_REQ_PSSCR(r13)
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
BEGIN_FTR_SECTION
sync
lwz r5, PACA_DONT_STOP(r13)
cmpwi r5, 0
bne 1f
END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
#endif
mtspr SPRN_PSSCR,r3
LOAD_REG_ADDR(r4,power_enter_stop)
b pnv_powersave_common
/* No return */
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
1:
/*
* We get here when TM / thread reconfiguration bug workaround
@ -465,6 +465,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
li r3, 0
std r3, PACA_REQ_PSSCR(r13)
blr /* return 0 for wakeup cause / SRR1 value */
#endif
/*
* On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,

View File

@ -397,10 +397,6 @@ void power9_idle(void)
* all other threads not to stop, and sending a message to any
* that are in a stop state.
* Must be called with preemption disabled.
*
* DO NOT call this unless cpu_has_feature(CPU_FTR_P9_TM_XER_SO_BUG) is
* true; otherwise this function will hang the system, due to the
* optimization in power9_idle_stop.
*/
void pnv_power9_force_smt4_catch(void)
{