korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-11 13:04:03 +08:00
Code Issues Packages Projects Releases Wiki Activity

ASoC: Intel: Skylake: Add support for programming D0i3C

Browse Source 
To set the controller in D0i3 mode, the driver needs to set D0i3C
register after DSP is quiesced. Since the D0iX entry/exit is done by IPC,
add this as callback so that it can be invoked from IPC module.

Signed-off-by: Pardha Saradhi K <pardha.saradhi.kesapragada@intel.com>
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Pardha Saradhi K 2016-11-03 17:07:16 +05:30 committed by Mark Brown
parent 41b7523f19
commit a26a3f53e3
4 changed files with 56 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
sound/soc/intel/skylake/skl-pcm.c
View File

@ -1211,6 +1211,7 @@ static int skl_platform_soc_probe(struct snd_soc_platform *platform)
return ret;
}
skl_populate_modules(skl);
skl->skl_sst->update_d0i3c = skl_update_d0i3c;
}
pm_runtime_mark_last_busy(platform->dev);
pm_runtime_put_autosuspend(platform->dev);

3
sound/soc/intel/skylake/skl-sst-ipc.h
View File

@ -83,6 +83,9 @@ struct skl_sst {
/* tplg manifest */
struct skl_dfw_manifest manifest;
/* Callback to update D0i3C register */
void (*update_d0i3c)(struct device *dev, bool enable);
};
struct skl_ipc_init_instance_msg {

47
sound/soc/intel/skylake/skl.c
View File

@ -26,6 +26,7 @@
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <linux/delay.h>
#include <sound/pcm.h>
#include "../common/sst-acpi.h"
#include <sound/hda_register.h>
@ -109,6 +110,52 @@ static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
return ret;
}
void skl_update_d0i3c(struct device *dev, bool enable)
{
struct pci_dev *pci = to_pci_dev(dev);
struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
struct hdac_bus *bus = ebus_to_hbus(ebus);
u8 reg;
int timeout = 50;
reg = snd_hdac_chip_readb(bus, VS_D0I3C);
/* Do not write to D0I3C until command in progress bit is cleared */
while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
udelay(10);
reg = snd_hdac_chip_readb(bus, VS_D0I3C);
}
/* Highly unlikely. But if it happens, flag error explicitly */
if (!timeout) {
dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
return;
}
if (enable)
reg = reg | AZX_REG_VS_D0I3C_I3;
else
reg = reg & (~AZX_REG_VS_D0I3C_I3);
snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
timeout = 50;
/* Wait for cmd in progress to be cleared before exiting the function */
reg = snd_hdac_chip_readb(bus, VS_D0I3C);
while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
udelay(10);
reg = snd_hdac_chip_readb(bus, VS_D0I3C);
}
/* Highly unlikely. But if it happens, flag error explicitly */
if (!timeout) {
dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
return;
}
dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
snd_hdac_chip_readb(bus, VS_D0I3C));
}
/* called from IRQ */
static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
{

5
sound/soc/intel/skylake/skl.h
View File

@ -52,6 +52,9 @@
#define AZX_PGCTL_LSRMD_MASK (1 << 4)
#define AZX_PCIREG_CGCTL 0x48
#define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
/* D0I3C Register fields */
#define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */
#define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */
struct skl_dsp_resource {
u32 max_mcps;
@ -125,4 +128,6 @@ int skl_suspend_dsp(struct skl *skl);
int skl_resume_dsp(struct skl *skl);
void skl_cleanup_resources(struct skl *skl);
const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
void skl_update_d0i3c(struct device *dev, bool enable);
#endif /* __SOUND_SOC_SKL_H */