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RDMA/hns: Remove support for HIP08_A
HIP08_A is an temporary version and all features of it are supported by HIP08_B. So remove the relevant code. Link: https://lore.kernel.org/r/1595932941-40613-4-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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@ -37,9 +37,8 @@
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#define DRV_NAME "hns_roce"
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/* hip08 is a pci device, it includes two version according pci version id */
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#define PCI_REVISION_ID_HIP08_A 0x20
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#define PCI_REVISION_ID_HIP08_B 0x21
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/* hip08 is a pci device */
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#define PCI_REVISION_ID_HIP08 0x21
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#define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
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@ -1744,27 +1744,25 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
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caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
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caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
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if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
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caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
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HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
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HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
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caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
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HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
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HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
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caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
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caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
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caps->qpc_timer_ba_pg_sz = 0;
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caps->qpc_timer_buf_pg_sz = 0;
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caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
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caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
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caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
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caps->cqc_timer_ba_pg_sz = 0;
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caps->cqc_timer_buf_pg_sz = 0;
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caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
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caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
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caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
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caps->qpc_timer_ba_pg_sz = 0;
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caps->qpc_timer_buf_pg_sz = 0;
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caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
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caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
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caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
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caps->cqc_timer_ba_pg_sz = 0;
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caps->cqc_timer_buf_pg_sz = 0;
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caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
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caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ;
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caps->sccc_ba_pg_sz = 0;
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caps->sccc_buf_pg_sz = 0;
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caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
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}
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caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ;
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caps->sccc_ba_pg_sz = 0;
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caps->sccc_buf_pg_sz = 0;
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caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
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}
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static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
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@ -1995,20 +1993,18 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
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caps->srqc_bt_num, &caps->srqc_buf_pg_sz,
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&caps->srqc_ba_pg_sz, HEM_TYPE_SRQC);
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if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
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caps->sccc_hop_num = ctx_hop_num;
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caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
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caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
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caps->sccc_hop_num = ctx_hop_num;
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caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
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caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
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calc_pg_sz(caps->num_qps, caps->sccc_entry_sz,
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caps->sccc_hop_num, caps->sccc_bt_num,
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&caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz,
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HEM_TYPE_SCCC);
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calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz,
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caps->cqc_timer_hop_num, caps->cqc_timer_bt_num,
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&caps->cqc_timer_buf_pg_sz,
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&caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
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}
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calc_pg_sz(caps->num_qps, caps->sccc_entry_sz,
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caps->sccc_hop_num, caps->sccc_bt_num,
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&caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz,
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HEM_TYPE_SCCC);
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calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz,
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caps->cqc_timer_hop_num, caps->cqc_timer_bt_num,
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&caps->cqc_timer_buf_pg_sz,
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&caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
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calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num,
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1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
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@ -2055,22 +2051,19 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
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return ret;
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}
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if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
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ret = hns_roce_query_pf_timer_resource(hr_dev);
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if (ret) {
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dev_err(hr_dev->dev,
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"Query pf timer resource fail, ret = %d.\n",
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ret);
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return ret;
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}
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ret = hns_roce_query_pf_timer_resource(hr_dev);
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if (ret) {
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dev_err(hr_dev->dev,
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"failed to query pf timer resource, ret = %d.\n", ret);
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return ret;
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}
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ret = hns_roce_set_vf_switch_param(hr_dev, 0);
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if (ret) {
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dev_err(hr_dev->dev,
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"Set function switch param fail, ret = %d.\n",
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ret);
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return ret;
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}
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ret = hns_roce_set_vf_switch_param(hr_dev, 0);
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if (ret) {
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dev_err(hr_dev->dev,
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"failed to set function switch param, ret = %d.\n",
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ret);
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return ret;
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}
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hr_dev->vendor_part_id = hr_dev->pci_dev->device;
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@ -2336,8 +2329,7 @@ static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B)
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hns_roce_function_clear(hr_dev);
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hns_roce_function_clear(hr_dev);
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hns_roce_free_link_table(hr_dev, &priv->tpq);
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hns_roce_free_link_table(hr_dev, &priv->tsq);
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@ -4231,12 +4223,13 @@ static int hns_roce_v2_set_path(struct ib_qp *ibqp,
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roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
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V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
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if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B && is_udp)
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if (is_udp)
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roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
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V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2);
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else
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roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
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V2_QPC_BYTE_24_TC_S, grh->traffic_class);
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roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
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V2_QPC_BYTE_24_TC_S, 0);
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roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
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@ -411,7 +411,6 @@ static int set_extend_sge_param(struct hns_roce_dev *hr_dev, u32 sq_wqe_cnt,
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struct hns_roce_qp *hr_qp,
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struct ib_qp_cap *cap)
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{
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struct ib_device *ibdev = &hr_dev->ib_dev;
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u32 cnt;
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cnt = max(1U, cap->max_send_sge);
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@ -431,15 +430,6 @@ static int set_extend_sge_param(struct hns_roce_dev *hr_dev, u32 sq_wqe_cnt,
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} else if (hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE) {
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cnt = roundup_pow_of_two(sq_wqe_cnt *
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(hr_qp->sq.max_gs - HNS_ROCE_SGE_IN_WQE));
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if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_A) {
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if (cnt > hr_dev->caps.max_extend_sg) {
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ibdev_err(ibdev,
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"failed to check exSGE num, exSGE num = %d.\n",
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cnt);
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return -EINVAL;
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}
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}
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} else {
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cnt = 0;
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}
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