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iommu/vt-d: Implement page request handling
Largely based on the driver-mode implementation by Jesse Barnes. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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1208225cf4
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@ -1698,8 +1698,11 @@ static void free_dmar_iommu(struct intel_iommu *iommu)
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free_context_table(iommu);
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#ifdef CONFIG_INTEL_IOMMU_SVM
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if (pasid_enabled(iommu))
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if (pasid_enabled(iommu)) {
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if (ecap_prs(iommu->ecap))
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intel_svm_finish_prq(iommu);
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intel_svm_free_pasid_tables(iommu);
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}
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#endif
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}
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@ -3243,6 +3246,13 @@ domains_done:
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iommu_flush_write_buffer(iommu);
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#ifdef CONFIG_INTEL_IOMMU_SVM
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if (pasid_enabled(iommu) && ecap_prs(iommu->ecap)) {
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ret = intel_svm_enable_prq(iommu);
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if (ret)
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goto free_iommu;
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}
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#endif
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ret = dmar_set_interrupt(iommu);
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if (ret)
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goto free_iommu;
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@ -4187,6 +4197,14 @@ static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
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intel_iommu_init_qi(iommu);
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iommu_flush_write_buffer(iommu);
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#ifdef CONFIG_INTEL_IOMMU_SVM
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if (pasid_enabled(iommu) && ecap_prs(iommu->ecap)) {
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ret = intel_svm_enable_prq(iommu);
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if (ret)
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goto disable_iommu;
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}
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#endif
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ret = dmar_set_interrupt(iommu);
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if (ret)
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goto disable_iommu;
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@ -4983,6 +5001,8 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sd
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ctx_lo |= CONTEXT_PASIDE;
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if (iommu->pasid_state_table)
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ctx_lo |= CONTEXT_DINVE;
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if (info->pri_supported)
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ctx_lo |= CONTEXT_PRS;
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context[0].lo = ctx_lo;
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wmb();
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iommu->flush.flush_context(iommu, sdev->did, sdev->sid,
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@ -21,6 +21,10 @@
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#include <linux/rculist.h>
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#include <linux/pci.h>
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#include <linux/pci-ats.h>
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#include <linux/dmar.h>
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#include <linux/interrupt.h>
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static irqreturn_t prq_event_thread(int irq, void *d);
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struct pasid_entry {
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u64 val;
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@ -82,6 +86,66 @@ int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
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return 0;
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}
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#define PRQ_ORDER 0
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int intel_svm_enable_prq(struct intel_iommu *iommu)
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{
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struct page *pages;
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int irq, ret;
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pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
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if (!pages) {
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pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
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iommu->name);
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return -ENOMEM;
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}
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iommu->prq = page_address(pages);
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irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
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if (irq <= 0) {
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pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
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iommu->name);
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ret = -EINVAL;
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err:
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free_pages((unsigned long)iommu->prq, PRQ_ORDER);
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iommu->prq = NULL;
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return ret;
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}
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iommu->pr_irq = irq;
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snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
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ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
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iommu->prq_name, iommu);
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if (ret) {
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pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
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iommu->name);
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dmar_free_hwirq(irq);
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goto err;
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}
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dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
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return 0;
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}
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int intel_svm_finish_prq(struct intel_iommu *iommu)
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{
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dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
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dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
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free_irq(iommu->pr_irq, iommu);
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dmar_free_hwirq(iommu->pr_irq);
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iommu->pr_irq = 0;
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free_pages((unsigned long)iommu->prq, PRQ_ORDER);
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iommu->prq = NULL;
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return 0;
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}
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static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
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unsigned long address, int pages, int ih)
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{
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@ -363,3 +427,112 @@ int intel_svm_unbind_mm(struct device *dev, int pasid)
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return ret;
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}
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EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
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/* Page request queue descriptor */
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struct page_req_dsc {
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u64 srr:1;
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u64 bof:1;
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u64 pasid_present:1;
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u64 lpig:1;
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u64 pasid:20;
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u64 bus:8;
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u64 private:23;
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u64 prg_index:9;
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u64 rd_req:1;
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u64 wr_req:1;
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u64 exe_req:1;
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u64 priv_req:1;
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u64 devfn:8;
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u64 addr:52;
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};
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#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
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static irqreturn_t prq_event_thread(int irq, void *d)
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{
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struct intel_iommu *iommu = d;
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struct intel_svm *svm = NULL;
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int head, tail, handled = 0;
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tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
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head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
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while (head != tail) {
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struct vm_area_struct *vma;
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struct page_req_dsc *req;
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struct qi_desc resp;
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int ret, result;
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u64 address;
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handled = 1;
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req = &iommu->prq[head / sizeof(*req)];
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result = QI_RESP_FAILURE;
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address = req->addr << PAGE_SHIFT;
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if (!req->pasid_present) {
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pr_err("%s: Page request without PASID: %08llx %08llx\n",
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iommu->name, ((unsigned long long *)req)[0],
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((unsigned long long *)req)[1]);
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goto bad_req;
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}
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if (!svm || svm->pasid != req->pasid) {
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rcu_read_lock();
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svm = idr_find(&iommu->pasid_idr, req->pasid);
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/* It *can't* go away, because the driver is not permitted
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* to unbind the mm while any page faults are outstanding.
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* So we only need RCU to protect the internal idr code. */
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rcu_read_unlock();
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if (!svm) {
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pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
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iommu->name, req->pasid, ((unsigned long long *)req)[0],
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((unsigned long long *)req)[1]);
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goto bad_req;
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}
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}
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result = QI_RESP_INVALID;
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down_read(&svm->mm->mmap_sem);
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vma = find_extend_vma(svm->mm, address);
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if (!vma || address < vma->vm_start)
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goto invalid;
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ret = handle_mm_fault(svm->mm, vma, address,
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req->wr_req ? FAULT_FLAG_WRITE : 0);
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if (ret & VM_FAULT_ERROR)
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goto invalid;
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result = QI_RESP_SUCCESS;
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invalid:
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up_read(&svm->mm->mmap_sem);
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bad_req:
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/* Accounting for major/minor faults? */
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if (req->lpig) {
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/* Page Group Response */
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resp.low = QI_PGRP_PASID(req->pasid) |
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QI_PGRP_DID((req->bus << 8) | req->devfn) |
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QI_PGRP_PASID_P(req->pasid_present) |
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QI_PGRP_RESP_TYPE;
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resp.high = QI_PGRP_IDX(req->prg_index) |
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QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
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qi_submit_sync(&resp, svm->iommu);
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} else if (req->srr) {
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/* Page Stream Response */
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resp.low = QI_PSTRM_IDX(req->prg_index) |
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QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
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QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
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resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
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QI_PSTRM_RESP_CODE(result);
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qi_submit_sync(&resp, svm->iommu);
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}
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head = (head + sizeof(*req)) & PRQ_RING_MASK;
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}
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dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
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return IRQ_RETVAL(handled);
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}
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@ -265,6 +265,8 @@ enum {
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#define QI_EIOTLB_TYPE 0x6
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#define QI_PC_TYPE 0x7
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#define QI_DEIOTLB_TYPE 0x8
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#define QI_PGRP_RESP_TYPE 0x9
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#define QI_PSTRM_RESP_TYPE 0xa
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#define QI_IEC_SELECTIVE (((u64)1) << 4)
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#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
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@ -315,6 +317,25 @@ enum {
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#define QI_DEV_EIOTLB_QDEP(qd) (((qd) & 0x1f) << 16)
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#define QI_DEV_EIOTLB_MAX_INVS 32
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#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
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#define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
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#define QI_PGRP_RESP_CODE(res) ((u64)(res))
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#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
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#define QI_PGRP_DID(did) (((u64)(did)) << 16)
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#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
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#define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
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#define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
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#define QI_PSTRM_RESP_CODE(res) ((u64)(res))
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#define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
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#define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
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#define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
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#define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
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#define QI_RESP_SUCCESS 0x0
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#define QI_RESP_INVALID 0x1
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#define QI_RESP_FAILURE 0xf
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#define QI_GRAN_ALL_ALL 0
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#define QI_GRAN_NONG_ALL 1
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#define QI_GRAN_NONG_PASID 2
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@ -369,6 +390,7 @@ enum {
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struct pasid_entry;
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struct pasid_state_entry;
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struct page_req_dsc;
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struct intel_iommu {
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void __iomem *reg; /* Pointer to hardware regs, virtual addr */
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@ -401,6 +423,8 @@ struct intel_iommu {
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* told to. But while it's all driver-arbitrated, we're fine. */
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struct pasid_entry *pasid_table;
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struct pasid_state_entry *pasid_state_table;
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struct page_req_dsc *prq;
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unsigned char prq_name[16]; /* Name for PRQ interrupt */
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struct idr pasid_idr;
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#endif
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struct q_inval *qi; /* Queued invalidation info */
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@ -445,6 +469,8 @@ extern int dmar_ir_support(void);
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#ifdef CONFIG_INTEL_IOMMU_SVM
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extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
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extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
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extern int intel_svm_enable_prq(struct intel_iommu *iommu);
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extern int intel_svm_finish_prq(struct intel_iommu *iommu);
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struct intel_svm_dev {
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struct list_head list;
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