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thunderbolt: Add bandwidth management for Display Port tunnels
Titan Ridge supports Display Port 1.4 which adds HBR3 (High Bit Rate) rates that may be up to 8.1 Gb/s over 4 lanes. This translates to effective data bandwidth of 25.92 Gb/s (as 8/10 encoding is removed by the DP adapters when going over Thunderbolt fabric). If another high rate monitor is connected we may need to reduce the bandwidth it consumes so that it fits into the total 40 Gb/s available on the Thunderbolt fabric. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Mika Westerberg
parent
8afe909b78
commit
a11b88add4
@ -557,3 +557,25 @@ bool tb_path_is_invalid(struct tb_path *path)
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}
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return false;
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}
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/**
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* tb_path_switch_on_path() - Does the path go through certain switch
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* @path: Path to check
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* @sw: Switch to check
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*
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* Goes over all hops on path and checks if @sw is any of them.
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* Direction does not matter.
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*/
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bool tb_path_switch_on_path(const struct tb_path *path,
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const struct tb_switch *sw)
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{
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int i;
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for (i = 0; i < path->path_length; i++) {
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if (path->hops[i].in_port->sw == sw ||
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path->hops[i].out_port->sw == sw)
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return true;
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}
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return false;
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}
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@ -422,11 +422,51 @@ out:
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return tb_find_unused_port(sw, TB_TYPE_PCIE_DOWN);
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}
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static int tb_available_bw(struct tb_cm *tcm, struct tb_port *in,
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struct tb_port *out)
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{
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struct tb_switch *sw = out->sw;
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struct tb_tunnel *tunnel;
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int bw, available_bw = 40000;
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while (sw && sw != in->sw) {
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bw = sw->link_speed * sw->link_width * 1000; /* Mb/s */
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/* Leave 10% guard band */
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bw -= bw / 10;
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/*
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* Check for any active DP tunnels that go through this
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* switch and reduce their consumed bandwidth from
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* available.
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*/
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list_for_each_entry(tunnel, &tcm->tunnel_list, list) {
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int consumed_bw;
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if (!tb_tunnel_switch_on_path(tunnel, sw))
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continue;
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consumed_bw = tb_tunnel_consumed_bandwidth(tunnel);
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if (consumed_bw < 0)
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return consumed_bw;
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bw -= consumed_bw;
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}
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if (bw < available_bw)
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available_bw = bw;
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sw = tb_switch_parent(sw);
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}
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return available_bw;
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}
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static void tb_tunnel_dp(struct tb *tb)
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{
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struct tb_cm *tcm = tb_priv(tb);
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struct tb_port *port, *in, *out;
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struct tb_tunnel *tunnel;
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int available_bw;
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/*
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* Find pair of inactive DP IN and DP OUT adapters and then
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@ -464,7 +504,17 @@ static void tb_tunnel_dp(struct tb *tb)
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return;
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}
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tunnel = tb_tunnel_alloc_dp(tb, in, out);
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/* Calculate available bandwidth between in and out */
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available_bw = tb_available_bw(tcm, in, out);
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if (available_bw < 0) {
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tb_warn(tb, "failed to determine available bandwidth\n");
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return;
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}
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tb_dbg(tb, "available bandwidth for new DP tunnel %u Mb/s\n",
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available_bw);
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tunnel = tb_tunnel_alloc_dp(tb, in, out, available_bw);
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if (!tunnel) {
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tb_port_dbg(out, "could not allocate DP tunnel\n");
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goto dealloc_dp;
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@ -691,6 +691,8 @@ void tb_path_free(struct tb_path *path);
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int tb_path_activate(struct tb_path *path);
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void tb_path_deactivate(struct tb_path *path);
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bool tb_path_is_invalid(struct tb_path *path);
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bool tb_path_switch_on_path(const struct tb_path *path,
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const struct tb_switch *sw);
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int tb_drom_read(struct tb_switch *sw);
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int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid);
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@ -255,6 +255,23 @@ struct tb_regs_port_header {
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#define DP_STATUS_CTRL 0x06
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#define DP_STATUS_CTRL_CMHS BIT(25)
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#define DP_STATUS_CTRL_UF BIT(26)
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#define DP_COMMON_CAP 0x07
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/*
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* DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
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* with exception of DPRX done.
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*/
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#define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)
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#define DP_COMMON_CAP_RATE_SHIFT 8
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#define DP_COMMON_CAP_RATE_RBR 0x0
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#define DP_COMMON_CAP_RATE_HBR 0x1
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#define DP_COMMON_CAP_RATE_HBR2 0x2
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#define DP_COMMON_CAP_RATE_HBR3 0x3
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#define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12)
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#define DP_COMMON_CAP_LANES_SHIFT 12
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#define DP_COMMON_CAP_1_LANE 0x0
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#define DP_COMMON_CAP_2_LANES 0x1
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#define DP_COMMON_CAP_4_LANES 0x2
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#define DP_COMMON_CAP_DPRX_DONE BIT(31)
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/* PCIe adapter registers */
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#define ADP_PCIE_CS_0 0x00
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@ -279,11 +279,138 @@ static int tb_dp_cm_handshake(struct tb_port *in, struct tb_port *out)
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return -ETIMEDOUT;
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}
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static inline u32 tb_dp_cap_get_rate(u32 val)
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{
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u32 rate = (val & DP_COMMON_CAP_RATE_MASK) >> DP_COMMON_CAP_RATE_SHIFT;
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switch (rate) {
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case DP_COMMON_CAP_RATE_RBR:
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return 1620;
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case DP_COMMON_CAP_RATE_HBR:
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return 2700;
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case DP_COMMON_CAP_RATE_HBR2:
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return 5400;
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case DP_COMMON_CAP_RATE_HBR3:
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return 8100;
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default:
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return 0;
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}
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}
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static inline u32 tb_dp_cap_set_rate(u32 val, u32 rate)
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{
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val &= ~DP_COMMON_CAP_RATE_MASK;
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switch (rate) {
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default:
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WARN(1, "invalid rate %u passed, defaulting to 1620 MB/s\n", rate);
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/* Fallthrough */
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case 1620:
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val |= DP_COMMON_CAP_RATE_RBR << DP_COMMON_CAP_RATE_SHIFT;
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break;
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case 2700:
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val |= DP_COMMON_CAP_RATE_HBR << DP_COMMON_CAP_RATE_SHIFT;
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break;
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case 5400:
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val |= DP_COMMON_CAP_RATE_HBR2 << DP_COMMON_CAP_RATE_SHIFT;
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break;
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case 8100:
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val |= DP_COMMON_CAP_RATE_HBR3 << DP_COMMON_CAP_RATE_SHIFT;
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break;
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}
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return val;
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}
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static inline u32 tb_dp_cap_get_lanes(u32 val)
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{
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u32 lanes = (val & DP_COMMON_CAP_LANES_MASK) >> DP_COMMON_CAP_LANES_SHIFT;
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switch (lanes) {
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case DP_COMMON_CAP_1_LANE:
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return 1;
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case DP_COMMON_CAP_2_LANES:
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return 2;
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case DP_COMMON_CAP_4_LANES:
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return 4;
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default:
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return 0;
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}
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}
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static inline u32 tb_dp_cap_set_lanes(u32 val, u32 lanes)
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{
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val &= ~DP_COMMON_CAP_LANES_MASK;
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switch (lanes) {
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default:
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WARN(1, "invalid number of lanes %u passed, defaulting to 1\n",
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lanes);
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/* Fallthrough */
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case 1:
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val |= DP_COMMON_CAP_1_LANE << DP_COMMON_CAP_LANES_SHIFT;
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break;
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case 2:
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val |= DP_COMMON_CAP_2_LANES << DP_COMMON_CAP_LANES_SHIFT;
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break;
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case 4:
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val |= DP_COMMON_CAP_4_LANES << DP_COMMON_CAP_LANES_SHIFT;
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break;
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}
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return val;
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}
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static unsigned int tb_dp_bandwidth(unsigned int rate, unsigned int lanes)
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{
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/* Tunneling removes the DP 8b/10b encoding */
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return rate * lanes * 8 / 10;
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}
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static int tb_dp_reduce_bandwidth(int max_bw, u32 in_rate, u32 in_lanes,
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u32 out_rate, u32 out_lanes, u32 *new_rate,
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u32 *new_lanes)
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{
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static const u32 dp_bw[][2] = {
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/* Mb/s, lanes */
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{ 8100, 4 }, /* 25920 Mb/s */
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{ 5400, 4 }, /* 17280 Mb/s */
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{ 8100, 2 }, /* 12960 Mb/s */
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{ 2700, 4 }, /* 8640 Mb/s */
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{ 5400, 2 }, /* 8640 Mb/s */
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{ 8100, 1 }, /* 6480 Mb/s */
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{ 1620, 4 }, /* 5184 Mb/s */
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{ 5400, 1 }, /* 4320 Mb/s */
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{ 2700, 2 }, /* 4320 Mb/s */
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{ 1620, 2 }, /* 2592 Mb/s */
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{ 2700, 1 }, /* 2160 Mb/s */
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{ 1620, 1 }, /* 1296 Mb/s */
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};
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unsigned int i;
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/*
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* Find a combination that can fit into max_bw and does not
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* exceed the maximum rate and lanes supported by the DP OUT and
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* DP IN adapters.
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*/
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for (i = 0; i < ARRAY_SIZE(dp_bw); i++) {
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if (dp_bw[i][0] > out_rate || dp_bw[i][1] > out_lanes)
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continue;
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if (dp_bw[i][0] > in_rate || dp_bw[i][1] > in_lanes)
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continue;
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if (tb_dp_bandwidth(dp_bw[i][0], dp_bw[i][1]) <= max_bw) {
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*new_rate = dp_bw[i][0];
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*new_lanes = dp_bw[i][1];
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return 0;
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}
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}
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return -ENOSR;
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}
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static int tb_dp_xchg_caps(struct tb_tunnel *tunnel)
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{
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u32 out_dp_cap, out_rate, out_lanes, in_dp_cap, in_rate, in_lanes, bw;
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struct tb_port *out = tunnel->dst_port;
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struct tb_port *in = tunnel->src_port;
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u32 in_dp_cap, out_dp_cap;
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int ret;
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/*
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@ -318,6 +445,44 @@ static int tb_dp_xchg_caps(struct tb_tunnel *tunnel)
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if (ret)
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return ret;
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in_rate = tb_dp_cap_get_rate(in_dp_cap);
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in_lanes = tb_dp_cap_get_lanes(in_dp_cap);
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tb_port_dbg(in, "maximum supported bandwidth %u Mb/s x%u = %u Mb/s\n",
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in_rate, in_lanes, tb_dp_bandwidth(in_rate, in_lanes));
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/*
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* If the tunnel bandwidth is limited (max_bw is set) then see
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* if we need to reduce bandwidth to fit there.
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*/
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out_rate = tb_dp_cap_get_rate(out_dp_cap);
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out_lanes = tb_dp_cap_get_lanes(out_dp_cap);
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bw = tb_dp_bandwidth(out_rate, out_lanes);
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tb_port_dbg(out, "maximum supported bandwidth %u Mb/s x%u = %u Mb/s\n",
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out_rate, out_lanes, bw);
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if (tunnel->max_bw && bw > tunnel->max_bw) {
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u32 new_rate, new_lanes, new_bw;
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ret = tb_dp_reduce_bandwidth(tunnel->max_bw, in_rate, in_lanes,
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out_rate, out_lanes, &new_rate,
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&new_lanes);
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if (ret) {
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tb_port_info(out, "not enough bandwidth for DP tunnel\n");
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return ret;
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}
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new_bw = tb_dp_bandwidth(new_rate, new_lanes);
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tb_port_dbg(out, "bandwidth reduced to %u Mb/s x%u = %u Mb/s\n",
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new_rate, new_lanes, new_bw);
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/*
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* Set new rate and number of lanes before writing it to
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* the IN port remote caps.
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*/
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out_dp_cap = tb_dp_cap_set_rate(out_dp_cap, new_rate);
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out_dp_cap = tb_dp_cap_set_lanes(out_dp_cap, new_lanes);
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}
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return tb_port_write(in, &out_dp_cap, TB_CFG_PORT,
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in->cap_adap + DP_REMOTE_CAP, 1);
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}
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@ -359,6 +524,56 @@ static int tb_dp_activate(struct tb_tunnel *tunnel, bool active)
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return 0;
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}
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static int tb_dp_consumed_bandwidth(struct tb_tunnel *tunnel)
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{
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struct tb_port *in = tunnel->src_port;
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const struct tb_switch *sw = in->sw;
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u32 val, rate = 0, lanes = 0;
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int ret;
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if (tb_switch_is_titan_ridge(sw)) {
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int timeout = 10;
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/*
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* Wait for DPRX done. Normally it should be already set
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* for active tunnel.
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*/
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do {
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ret = tb_port_read(in, &val, TB_CFG_PORT,
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in->cap_adap + DP_COMMON_CAP, 1);
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if (ret)
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return ret;
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if (val & DP_COMMON_CAP_DPRX_DONE) {
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rate = tb_dp_cap_get_rate(val);
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lanes = tb_dp_cap_get_lanes(val);
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break;
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}
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msleep(250);
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} while (timeout--);
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if (!timeout)
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return -ETIMEDOUT;
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} else if (sw->generation >= 2) {
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/*
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* Read from the copied remote cap so that we take into
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* account if capabilities were reduced during exchange.
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*/
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ret = tb_port_read(in, &val, TB_CFG_PORT,
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in->cap_adap + DP_REMOTE_CAP, 1);
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if (ret)
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return ret;
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rate = tb_dp_cap_get_rate(val);
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lanes = tb_dp_cap_get_lanes(val);
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} else {
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/* No bandwidth management for legacy devices */
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return 0;
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}
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return tb_dp_bandwidth(rate, lanes);
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}
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static void tb_dp_init_aux_path(struct tb_path *path)
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{
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int i;
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@ -423,6 +638,7 @@ struct tb_tunnel *tb_tunnel_discover_dp(struct tb *tb, struct tb_port *in)
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tunnel->init = tb_dp_xchg_caps;
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tunnel->activate = tb_dp_activate;
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tunnel->consumed_bandwidth = tb_dp_consumed_bandwidth;
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tunnel->src_port = in;
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path = tb_path_discover(in, TB_DP_VIDEO_HOPID, NULL, -1,
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@ -481,6 +697,7 @@ err_free:
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* @tb: Pointer to the domain structure
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* @in: DP in adapter port
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* @out: DP out adapter port
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* @max_bw: Maximum available bandwidth for the DP tunnel (%0 if not limited)
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*
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* Allocates a tunnel between @in and @out that is capable of tunneling
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* Display Port traffic.
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@ -488,7 +705,7 @@ err_free:
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* Return: Returns a tb_tunnel on success or NULL on failure.
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*/
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struct tb_tunnel *tb_tunnel_alloc_dp(struct tb *tb, struct tb_port *in,
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struct tb_port *out)
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struct tb_port *out, int max_bw)
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{
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struct tb_tunnel *tunnel;
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struct tb_path **paths;
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@ -503,8 +720,10 @@ struct tb_tunnel *tb_tunnel_alloc_dp(struct tb *tb, struct tb_port *in,
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tunnel->init = tb_dp_xchg_caps;
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tunnel->activate = tb_dp_activate;
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tunnel->consumed_bandwidth = tb_dp_consumed_bandwidth;
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tunnel->src_port = in;
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tunnel->dst_port = out;
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tunnel->max_bw = max_bw;
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paths = tunnel->paths;
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@ -751,3 +970,62 @@ void tb_tunnel_deactivate(struct tb_tunnel *tunnel)
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tb_path_deactivate(tunnel->paths[i]);
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}
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}
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/**
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* tb_tunnel_switch_on_path() - Does the tunnel go through switch
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* @tunnel: Tunnel to check
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* @sw: Switch to check
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*
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* Returns true if @tunnel goes through @sw (direction does not matter),
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* false otherwise.
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*/
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bool tb_tunnel_switch_on_path(const struct tb_tunnel *tunnel,
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const struct tb_switch *sw)
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{
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int i;
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for (i = 0; i < tunnel->npaths; i++) {
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if (!tunnel->paths[i])
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continue;
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if (tb_path_switch_on_path(tunnel->paths[i], sw))
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return true;
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}
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return false;
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}
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static bool tb_tunnel_is_active(const struct tb_tunnel *tunnel)
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{
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int i;
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for (i = 0; i < tunnel->npaths; i++) {
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if (!tunnel->paths[i])
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return false;
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if (!tunnel->paths[i]->activated)
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return false;
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||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* tb_tunnel_consumed_bandwidth() - Return bandwidth consumed by the tunnel
|
||||
* @tunnel: Tunnel to check
|
||||
*
|
||||
* Returns bandwidth currently consumed by @tunnel and %0 if the @tunnel
|
||||
* is not active or does consume bandwidth.
|
||||
*/
|
||||
int tb_tunnel_consumed_bandwidth(struct tb_tunnel *tunnel)
|
||||
{
|
||||
if (!tb_tunnel_is_active(tunnel))
|
||||
return 0;
|
||||
|
||||
if (tunnel->consumed_bandwidth) {
|
||||
int ret = tunnel->consumed_bandwidth(tunnel);
|
||||
|
||||
tb_tunnel_dbg(tunnel, "consumed bandwidth %d Mb/s\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -27,8 +27,11 @@ enum tb_tunnel_type {
|
||||
* @npaths: Number of paths in @paths
|
||||
* @init: Optional tunnel specific initialization
|
||||
* @activate: Optional tunnel specific activation/deactivation
|
||||
* @consumed_bandwidth: Return how much bandwidth the tunnel consumes
|
||||
* @list: Tunnels are linked using this field
|
||||
* @type: Type of the tunnel
|
||||
* @max_bw: Maximum bandwidth (Mb/s) available for the tunnel (only for DP).
|
||||
* Only set if the bandwidth needs to be limited.
|
||||
*/
|
||||
struct tb_tunnel {
|
||||
struct tb *tb;
|
||||
@ -38,8 +41,10 @@ struct tb_tunnel {
|
||||
size_t npaths;
|
||||
int (*init)(struct tb_tunnel *tunnel);
|
||||
int (*activate)(struct tb_tunnel *tunnel, bool activate);
|
||||
int (*consumed_bandwidth)(struct tb_tunnel *tunnel);
|
||||
struct list_head list;
|
||||
enum tb_tunnel_type type;
|
||||
unsigned int max_bw;
|
||||
};
|
||||
|
||||
struct tb_tunnel *tb_tunnel_discover_pci(struct tb *tb, struct tb_port *down);
|
||||
@ -47,7 +52,7 @@ struct tb_tunnel *tb_tunnel_alloc_pci(struct tb *tb, struct tb_port *up,
|
||||
struct tb_port *down);
|
||||
struct tb_tunnel *tb_tunnel_discover_dp(struct tb *tb, struct tb_port *in);
|
||||
struct tb_tunnel *tb_tunnel_alloc_dp(struct tb *tb, struct tb_port *in,
|
||||
struct tb_port *out);
|
||||
struct tb_port *out, int max_bw);
|
||||
struct tb_tunnel *tb_tunnel_alloc_dma(struct tb *tb, struct tb_port *nhi,
|
||||
struct tb_port *dst, int transmit_ring,
|
||||
int transmit_path, int receive_ring,
|
||||
@ -58,6 +63,9 @@ int tb_tunnel_activate(struct tb_tunnel *tunnel);
|
||||
int tb_tunnel_restart(struct tb_tunnel *tunnel);
|
||||
void tb_tunnel_deactivate(struct tb_tunnel *tunnel);
|
||||
bool tb_tunnel_is_invalid(struct tb_tunnel *tunnel);
|
||||
bool tb_tunnel_switch_on_path(const struct tb_tunnel *tunnel,
|
||||
const struct tb_switch *sw);
|
||||
int tb_tunnel_consumed_bandwidth(struct tb_tunnel *tunnel);
|
||||
|
||||
static inline bool tb_tunnel_is_pci(const struct tb_tunnel *tunnel)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user