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dmaengine: remove coh901318 driver
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210120131859.2056308-4-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Arnd Bergmann
Vinod Koul
parent
1c8963f830
commit
a033a74e8b
@ -1,32 +0,0 @@
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ST-Ericsson COH 901 318 DMA Controller
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This is a DMA controller which has begun as a fork of the
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ARM PL08x PrimeCell VHDL code.
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Required properties:
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- compatible: should be "stericsson,coh901318"
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- reg: register locations and length
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- interrupts: the single DMA IRQ
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- #dma-cells: must be set to <1>, as the channels on the
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COH 901 318 are simple and identified by a single number
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- dma-channels: the number of DMA channels handled
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Example:
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dmac: dma-controller@c00020000 {
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compatible = "stericsson,coh901318";
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reg = <0xc0020000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <2>;
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#dma-cells = <1>;
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dma-channels = <40>;
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};
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Consumers example:
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uart0: serial@c0013000 {
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compatible = "...";
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(...)
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dmas = <&dmac 17 &dmac 18>;
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dma-names = "tx", "rx";
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};
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@ -124,13 +124,6 @@ config BCM_SBA_RAID
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has the capability to offload memcpy, xor and pq computation
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for raid5/6.
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config COH901318
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bool "ST-Ericsson COH901318 DMA support"
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select DMA_ENGINE
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depends on ARCH_U300 || COMPILE_TEST
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help
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Enable support for ST-Ericsson COH 901 318 DMA.
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config DMA_BCM2835
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tristate "BCM2835 DMA engine support"
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depends on ARCH_BCM2835
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@ -20,7 +20,6 @@ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
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obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
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obj-$(CONFIG_AXI_DMAC) += dma-axi-dmac.o
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obj-$(CONFIG_BCM_SBA_RAID) += bcm-sba-raid.o
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obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
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obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
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obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o
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obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
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File diff suppressed because it is too large
Load Diff
@ -1,141 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2007-2013 ST-Ericsson
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* DMA driver for COH 901 318
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#ifndef COH901318_H
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#define COH901318_H
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#define MAX_DMA_PACKET_SIZE_SHIFT 11
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#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
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struct device;
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struct coh901318_pool {
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spinlock_t lock;
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struct dma_pool *dmapool;
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struct device *dev;
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#ifdef CONFIG_DEBUG_FS
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int debugfs_pool_counter;
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#endif
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};
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/**
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* struct coh901318_lli - linked list item for DMAC
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* @control: control settings for DMAC
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* @src_addr: transfer source address
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* @dst_addr: transfer destination address
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* @link_addr: physical address to next lli
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* @virt_link_addr: virtual address of next lli (only used by pool_free)
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* @phy_this: physical address of current lli (only used by pool_free)
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*/
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struct coh901318_lli {
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u32 control;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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dma_addr_t link_addr;
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void *virt_link_addr;
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dma_addr_t phy_this;
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};
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/**
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* coh901318_pool_create() - Creates an dma pool for lli:s
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* @pool: pool handle
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* @dev: dma device
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* @lli_nbr: number of lli:s in the pool
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* @algin: address alignemtn of lli:s
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* returns 0 on success otherwise none zero
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*/
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int coh901318_pool_create(struct coh901318_pool *pool,
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struct device *dev,
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size_t lli_nbr, size_t align);
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/**
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* coh901318_pool_destroy() - Destroys the dma pool
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* @pool: pool handle
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* returns 0 on success otherwise none zero
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*/
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int coh901318_pool_destroy(struct coh901318_pool *pool);
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/**
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* coh901318_lli_alloc() - Allocates a linked list
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*
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* @pool: pool handle
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* @len: length to list
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* return: none NULL if success otherwise NULL
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*/
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struct coh901318_lli *
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coh901318_lli_alloc(struct coh901318_pool *pool,
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unsigned int len);
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/**
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* coh901318_lli_free() - Returns the linked list items to the pool
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* @pool: pool handle
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* @lli: reference to lli pointer to be freed
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*/
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void coh901318_lli_free(struct coh901318_pool *pool,
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struct coh901318_lli **lli);
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/**
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* coh901318_lli_fill_memcpy() - Prepares the lli:s for dma memcpy
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* @pool: pool handle
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* @lli: allocated lli
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* @src: src address
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* @size: transfer size
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* @dst: destination address
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* @ctrl_chained: ctrl for chained lli
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* @ctrl_last: ctrl for the last lli
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* returns number of CPU interrupts for the lli, negative on error.
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*/
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int
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coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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dma_addr_t src, unsigned int size,
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dma_addr_t dst, u32 ctrl_chained, u32 ctrl_last);
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/**
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* coh901318_lli_fill_single() - Prepares the lli:s for dma single transfer
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* @pool: pool handle
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* @lli: allocated lli
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* @buf: transfer buffer
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* @size: transfer size
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* @dev_addr: address of periphal
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* @ctrl_chained: ctrl for chained lli
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* @ctrl_last: ctrl for the last lli
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* @dir: direction of transfer (to or from device)
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* returns number of CPU interrupts for the lli, negative on error.
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*/
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int
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coh901318_lli_fill_single(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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dma_addr_t buf, unsigned int size,
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dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last,
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enum dma_transfer_direction dir);
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/**
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* coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
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* @pool: pool handle
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* @lli: allocated lli
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* @sg: scatter gather list
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* @nents: number of entries in sg
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* @dev_addr: address of periphal
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* @ctrl_chained: ctrl for chained lli
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* @ctrl: ctrl of middle lli
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* @ctrl_last: ctrl for the last lli
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* @dir: direction of transfer (to or from device)
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* @ctrl_irq_mask: ctrl mask for CPU interrupt
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* returns number of CPU interrupts for the lli, negative on error.
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*/
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int
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coh901318_lli_fill_sg(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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struct scatterlist *sg, unsigned int nents,
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dma_addr_t dev_addr, u32 ctrl_chained,
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u32 ctrl, u32 ctrl_last,
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enum dma_transfer_direction dir, u32 ctrl_irq_mask);
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#endif /* COH901318_H */
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@ -1,313 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* driver/dma/coh901318_lli.c
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*
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* Copyright (C) 2007-2009 ST-Ericsson
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* Support functions for handling lli for dma
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#include <linux/spinlock.h>
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#include <linux/memory.h>
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#include <linux/gfp.h>
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#include <linux/dmapool.h>
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#include <linux/dmaengine.h>
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#include "coh901318.h"
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#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
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#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
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#define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)
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#else
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#define DEBUGFS_POOL_COUNTER_RESET(pool)
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#define DEBUGFS_POOL_COUNTER_ADD(pool, add)
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#endif
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static struct coh901318_lli *
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coh901318_lli_next(struct coh901318_lli *data)
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{
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if (data == NULL || data->link_addr == 0)
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return NULL;
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return (struct coh901318_lli *) data->virt_link_addr;
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}
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int coh901318_pool_create(struct coh901318_pool *pool,
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struct device *dev,
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size_t size, size_t align)
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{
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spin_lock_init(&pool->lock);
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pool->dev = dev;
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pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);
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DEBUGFS_POOL_COUNTER_RESET(pool);
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return 0;
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}
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int coh901318_pool_destroy(struct coh901318_pool *pool)
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{
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dma_pool_destroy(pool->dmapool);
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return 0;
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}
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struct coh901318_lli *
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coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)
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{
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int i;
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struct coh901318_lli *head;
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struct coh901318_lli *lli;
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struct coh901318_lli *lli_prev;
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dma_addr_t phy;
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if (len == 0)
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return NULL;
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spin_lock(&pool->lock);
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head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
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if (head == NULL)
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goto err;
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DEBUGFS_POOL_COUNTER_ADD(pool, 1);
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lli = head;
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lli->phy_this = phy;
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lli->link_addr = 0x00000000;
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lli->virt_link_addr = NULL;
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for (i = 1; i < len; i++) {
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lli_prev = lli;
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lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
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if (lli == NULL)
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goto err_clean_up;
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DEBUGFS_POOL_COUNTER_ADD(pool, 1);
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lli->phy_this = phy;
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lli->link_addr = 0x00000000;
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lli->virt_link_addr = NULL;
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lli_prev->link_addr = phy;
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lli_prev->virt_link_addr = lli;
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}
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spin_unlock(&pool->lock);
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return head;
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err:
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spin_unlock(&pool->lock);
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return NULL;
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err_clean_up:
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lli_prev->link_addr = 0x00000000U;
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spin_unlock(&pool->lock);
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coh901318_lli_free(pool, &head);
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return NULL;
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}
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void coh901318_lli_free(struct coh901318_pool *pool,
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struct coh901318_lli **lli)
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{
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struct coh901318_lli *l;
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struct coh901318_lli *next;
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if (lli == NULL)
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return;
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l = *lli;
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if (l == NULL)
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return;
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spin_lock(&pool->lock);
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while (l->link_addr) {
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next = l->virt_link_addr;
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dma_pool_free(pool->dmapool, l, l->phy_this);
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DEBUGFS_POOL_COUNTER_ADD(pool, -1);
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l = next;
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}
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dma_pool_free(pool->dmapool, l, l->phy_this);
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DEBUGFS_POOL_COUNTER_ADD(pool, -1);
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spin_unlock(&pool->lock);
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*lli = NULL;
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}
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int
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coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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dma_addr_t source, unsigned int size,
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dma_addr_t destination, u32 ctrl_chained,
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u32 ctrl_eom)
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{
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int s = size;
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dma_addr_t src = source;
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dma_addr_t dst = destination;
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lli->src_addr = src;
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lli->dst_addr = dst;
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while (lli->link_addr) {
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lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
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lli->src_addr = src;
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lli->dst_addr = dst;
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s -= MAX_DMA_PACKET_SIZE;
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lli = coh901318_lli_next(lli);
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src += MAX_DMA_PACKET_SIZE;
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dst += MAX_DMA_PACKET_SIZE;
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}
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lli->control = ctrl_eom | s;
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lli->src_addr = src;
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lli->dst_addr = dst;
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return 0;
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}
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int
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coh901318_lli_fill_single(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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dma_addr_t buf, unsigned int size,
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dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
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enum dma_transfer_direction dir)
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{
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int s = size;
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dma_addr_t src;
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dma_addr_t dst;
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if (dir == DMA_MEM_TO_DEV) {
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src = buf;
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dst = dev_addr;
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} else if (dir == DMA_DEV_TO_MEM) {
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src = dev_addr;
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dst = buf;
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} else {
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return -EINVAL;
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}
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while (lli->link_addr) {
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size_t block_size = MAX_DMA_PACKET_SIZE;
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lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
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/* If we are on the next-to-final block and there will
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* be less than half a DMA packet left for the last
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* block, then we want to make this block a little
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* smaller to balance the sizes. This is meant to
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* avoid too small transfers if the buffer size is
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* (MAX_DMA_PACKET_SIZE*N + 1) */
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if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))
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block_size = MAX_DMA_PACKET_SIZE/2;
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s -= block_size;
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lli->src_addr = src;
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lli->dst_addr = dst;
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lli = coh901318_lli_next(lli);
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if (dir == DMA_MEM_TO_DEV)
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src += block_size;
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else if (dir == DMA_DEV_TO_MEM)
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dst += block_size;
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}
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lli->control = ctrl_eom | s;
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lli->src_addr = src;
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lli->dst_addr = dst;
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return 0;
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}
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int
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coh901318_lli_fill_sg(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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struct scatterlist *sgl, unsigned int nents,
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dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
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u32 ctrl_last,
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enum dma_transfer_direction dir, u32 ctrl_irq_mask)
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{
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int i;
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struct scatterlist *sg;
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u32 ctrl_sg;
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dma_addr_t src = 0;
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dma_addr_t dst = 0;
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u32 bytes_to_transfer;
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u32 elem_size;
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if (lli == NULL)
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goto err;
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spin_lock(&pool->lock);
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if (dir == DMA_MEM_TO_DEV)
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dst = dev_addr;
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else if (dir == DMA_DEV_TO_MEM)
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src = dev_addr;
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else
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goto err;
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for_each_sg(sgl, sg, nents, i) {
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if (sg_is_chain(sg)) {
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/* sg continues to the next sg-element don't
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* send ctrl_finish until the last
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* sg-element in the chain
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*/
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ctrl_sg = ctrl_chained;
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} else if (i == nents - 1)
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ctrl_sg = ctrl_last;
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else
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ctrl_sg = ctrl ? ctrl : ctrl_last;
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if (dir == DMA_MEM_TO_DEV)
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/* increment source address */
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src = sg_dma_address(sg);
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else
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/* increment destination address */
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dst = sg_dma_address(sg);
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bytes_to_transfer = sg_dma_len(sg);
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while (bytes_to_transfer) {
|
||||
u32 val;
|
||||
|
||||
if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {
|
||||
elem_size = MAX_DMA_PACKET_SIZE;
|
||||
val = ctrl_chained;
|
||||
} else {
|
||||
elem_size = bytes_to_transfer;
|
||||
val = ctrl_sg;
|
||||
}
|
||||
|
||||
lli->control = val | elem_size;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
if (dir == DMA_DEV_TO_MEM)
|
||||
dst += elem_size;
|
||||
else
|
||||
src += elem_size;
|
||||
|
||||
BUG_ON(lli->link_addr & 3);
|
||||
|
||||
bytes_to_transfer -= elem_size;
|
||||
lli = coh901318_lli_next(lli);
|
||||
}
|
||||
|
||||
}
|
||||
spin_unlock(&pool->lock);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
spin_unlock(&pool->lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -1,72 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Platform data for the COH901318 DMA controller
|
||||
* Copyright (C) 2007-2013 ST-Ericsson
|
||||
*/
|
||||
|
||||
#ifndef PLAT_COH901318_H
|
||||
#define PLAT_COH901318_H
|
||||
|
||||
#ifdef CONFIG_COH901318
|
||||
|
||||
/* We only support the U300 DMA channels */
|
||||
#define U300_DMA_MSL_TX_0 0
|
||||
#define U300_DMA_MSL_TX_1 1
|
||||
#define U300_DMA_MSL_TX_2 2
|
||||
#define U300_DMA_MSL_TX_3 3
|
||||
#define U300_DMA_MSL_TX_4 4
|
||||
#define U300_DMA_MSL_TX_5 5
|
||||
#define U300_DMA_MSL_TX_6 6
|
||||
#define U300_DMA_MSL_RX_0 7
|
||||
#define U300_DMA_MSL_RX_1 8
|
||||
#define U300_DMA_MSL_RX_2 9
|
||||
#define U300_DMA_MSL_RX_3 10
|
||||
#define U300_DMA_MSL_RX_4 11
|
||||
#define U300_DMA_MSL_RX_5 12
|
||||
#define U300_DMA_MSL_RX_6 13
|
||||
#define U300_DMA_MMCSD_RX_TX 14
|
||||
#define U300_DMA_MSPRO_TX 15
|
||||
#define U300_DMA_MSPRO_RX 16
|
||||
#define U300_DMA_UART0_TX 17
|
||||
#define U300_DMA_UART0_RX 18
|
||||
#define U300_DMA_APEX_TX 19
|
||||
#define U300_DMA_APEX_RX 20
|
||||
#define U300_DMA_PCM_I2S0_TX 21
|
||||
#define U300_DMA_PCM_I2S0_RX 22
|
||||
#define U300_DMA_PCM_I2S1_TX 23
|
||||
#define U300_DMA_PCM_I2S1_RX 24
|
||||
#define U300_DMA_XGAM_CDI 25
|
||||
#define U300_DMA_XGAM_PDI 26
|
||||
#define U300_DMA_SPI_TX 27
|
||||
#define U300_DMA_SPI_RX 28
|
||||
#define U300_DMA_GENERAL_PURPOSE_0 29
|
||||
#define U300_DMA_GENERAL_PURPOSE_1 30
|
||||
#define U300_DMA_GENERAL_PURPOSE_2 31
|
||||
#define U300_DMA_GENERAL_PURPOSE_3 32
|
||||
#define U300_DMA_GENERAL_PURPOSE_4 33
|
||||
#define U300_DMA_GENERAL_PURPOSE_5 34
|
||||
#define U300_DMA_GENERAL_PURPOSE_6 35
|
||||
#define U300_DMA_GENERAL_PURPOSE_7 36
|
||||
#define U300_DMA_GENERAL_PURPOSE_8 37
|
||||
#define U300_DMA_UART1_TX 38
|
||||
#define U300_DMA_UART1_RX 39
|
||||
|
||||
#define U300_DMA_DEVICE_CHANNELS 32
|
||||
#define U300_DMA_CHANNELS 40
|
||||
|
||||
/**
|
||||
* coh901318_filter_id() - DMA channel filter function
|
||||
* @chan: dma channel handle
|
||||
* @chan_id: id of dma channel to be filter out
|
||||
*
|
||||
* In dma_request_channel() it specifies what channel id to be requested
|
||||
*/
|
||||
bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
|
||||
#else
|
||||
static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PLAT_COH901318_H */
|
||||
Loading…
Reference in New Issue
Block a user