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perf vendor events intel: Update westmereep-dp event topics

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Apply topic updates from:

https://github.com/intel/event-converter-for-linux-perf/

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220413210503.3256922-9-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2022-04-13 14:04:58 -07:00 committed by Arnaldo Carvalho de Melo
parent 55ae1b759e
commit a01174fc9e
2 changed files with 66 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
View File

@ -1,28 +1,4 @@
[
{
"BriefDescription": "Early Branch Prediciton Unit clears",
"Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
"Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "Branch prediction unit missed call or return",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
@ -127,46 +103,6 @@
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "All RAT stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
"UMask": "0xf"
},
{
"BriefDescription": "Flag stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Partial register stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "ROB read port stalls cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "Scoreboard stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
"UMask": "0x8"
},
{
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
@ -284,4 +220,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
]
]

66
tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
View File

@ -50,6 +50,30 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Early Branch Prediciton Unit clears",
"Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
"Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "Branch prediction unit missed call or return",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1,2,3",
@ -494,6 +518,46 @@
"SampleAfterValue": "20000",
"UMask": "0x4"
},
{
"BriefDescription": "All RAT stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
"UMask": "0xf"
},
{
"BriefDescription": "Flag stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Partial register stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "ROB read port stalls cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "Scoreboard stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
"UMask": "0x8"
},
{
"BriefDescription": "Resource related stall cycles",
"Counter": "0,1,2,3",
@ -896,4 +960,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
]
]