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ARM: 8711/1: V7M: Add support for MPU to M-class
This patch makes it possible to use MPU with v7M cores. Tested-by: Szemző András <sza@esh.hu> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Vladimir Murzin
Russell King
parent
89a6dafe13
commit
9fcb01a9f5
@ -52,8 +52,8 @@ config REMAP_VECTORS_TO_RAM
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config ARM_MPU
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bool 'Use the ARM v7 PMSA Compliant MPU'
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depends on !XIP_KERNEL && CPU_V7
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default y
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depends on !XIP_KERNEL && (CPU_V7 || CPU_V7M)
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default y if CPU_V7
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help
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Some ARM systems without an MMU have instead a Memory Protection
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Unit (MPU) that defines the type and permissions for regions of
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@ -173,6 +173,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
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return read_cpuid(CPUID_CACHETYPE);
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}
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static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
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{
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return read_cpuid(CPUID_MPUIR);
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}
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#elif defined(CONFIG_CPU_V7M)
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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@ -185,6 +190,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
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return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
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}
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static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
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{
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return readl(BASEADDR_V7M_SCB + MPU_TYPE);
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}
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#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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@ -57,6 +57,16 @@
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#define V7M_SCB_CCSIDR 0x80 /* Cache size ID register */
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#define V7M_SCB_CSSELR 0x84 /* Cache size selection register */
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/* Memory-mapped MPU registers for M-class */
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#define MPU_TYPE 0x90
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#define MPU_CTRL 0x94
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#define MPU_CTRL_ENABLE 1
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#define MPU_CTRL_PRIVDEFENA (1 << 2)
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#define MPU_RNR 0x98
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#define MPU_RBAR 0x9c
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#define MPU_RASR 0xa0
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/* Cache opeartions */
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#define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
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#define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
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@ -176,19 +176,33 @@ ENDPROC(__after_proc_init)
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#ifdef CONFIG_ARM_MPU
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#ifndef CONFIG_CPU_V7M
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/* Set which MPU region should be programmed */
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.macro set_region_nr tmp, rgnr
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.macro set_region_nr tmp, rgnr, unused
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mov \tmp, \rgnr @ Use static region numbers
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mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
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.endm
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/* Setup a single MPU region, either D or I side (D-side for unified) */
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.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
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.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE, unused
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mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
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mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
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mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
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.endm
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#else
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.macro set_region_nr tmp, rgnr, base
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mov \tmp, \rgnr
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str \tmp, [\base, #MPU_RNR]
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.endm
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.macro setup_region bar, acr, sr, unused, base
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lsl \acr, \acr, #16
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orr \acr, \acr, \sr
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str \bar, [\base, #MPU_RBAR]
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str \acr, [\base, #MPU_RASR]
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.endm
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#endif
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/*
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* Setup the MPU and initial MPU Regions. We create the following regions:
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* Region 0: Use this for probing the MPU details, so leave disabled.
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@ -202,48 +216,58 @@ ENDPROC(__after_proc_init)
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ENTRY(__setup_mpu)
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/* Probe for v7 PMSA compliance */
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mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
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M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
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M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
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AR_CLASS(mrc p15, 0, r0, c0, c1, 4) @ Read ID_MMFR0
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M_CLASS(ldr r0, [r12, 0x50])
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and r0, r0, #(MMFR0_PMSA) @ PMSA field
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teq r0, #(MMFR0_PMSAv7) @ PMSA v7
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bxne lr
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/* Determine whether the D/I-side memory map is unified. We set the
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* flags here and continue to use them for the rest of this function */
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mrc p15, 0, r0, c0, c0, 4 @ MPUIR
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AR_CLASS(mrc p15, 0, r0, c0, c0, 4) @ MPUIR
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M_CLASS(ldr r0, [r12, #MPU_TYPE])
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ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
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bxeq lr
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tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
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/* Setup second region first to free up r6 */
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set_region_nr r0, #MPU_RAM_REGION
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set_region_nr r0, #MPU_RAM_REGION, r12
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isb
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/* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
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ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
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ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
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setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled
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beq 1f @ Memory-map not unified
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setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
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setup_region r0, r5, r6, MPU_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
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beq 1f @ Memory-map not unified
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setup_region r0, r5, r6, MPU_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
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1: isb
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/* First/background region */
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set_region_nr r0, #MPU_BG_REGION
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set_region_nr r0, #MPU_BG_REGION, r12
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isb
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/* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
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mov r0, #0 @ BG region starts at 0x0
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ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
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mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled
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setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled
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beq 2f @ Memory-map not unified
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setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
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setup_region r0, r5, r6, MPU_DATA_SIDE, r12 @ 0x0, BG region, enabled
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beq 2f @ Memory-map not unified
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setup_region r0, r5, r6, MPU_INSTR_SIDE r12 @ 0x0, BG region, enabled
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2: isb
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/* Enable the MPU */
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
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bic r0, r0, #CR_BR @ Disable the 'default mem-map'
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orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
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mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
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AR_CLASS(mrc p15, 0, r0, c1, c0, 0) @ Read SCTLR
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AR_CLASS(bic r0, r0, #CR_BR) @ Disable the 'default mem-map'
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AR_CLASS(orr r0, r0, #CR_M) @ Set SCTRL.M (MPU on)
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AR_CLASS(mcr p15, 0, r0, c1, c0, 0) @ Enable MPU
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M_CLASS(ldr r0, [r12, #MPU_CTRL])
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M_CLASS(bic r0, #MPU_CTRL_PRIVDEFENA)
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M_CLASS(orr r0, #MPU_CTRL_ENABLE)
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M_CLASS(str r0, [r12, #MPU_CTRL])
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isb
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ret lr
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@ -15,6 +15,8 @@
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static unsigned int __initdata mpu_min_region_order;
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static unsigned int __initdata mpu_max_regions;
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#ifndef CONFIG_CPU_V7M
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#define DRBAR __ACCESS_CP15(c6, 0, c1, 0)
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#define IRBAR __ACCESS_CP15(c6, 0, c1, 1)
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#define DRSR __ACCESS_CP15(c6, 0, c1, 2)
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@ -78,6 +80,51 @@ static inline u32 irbar_read(void)
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return read_sysreg(IRBAR);
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}
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#else
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static inline void rgnr_write(u32 v)
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{
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writel_relaxed(v, BASEADDR_V7M_SCB + MPU_RNR);
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}
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/* Data-side / unified region attributes */
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/* Region access control register */
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static inline void dracr_write(u32 v)
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{
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u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(15, 0);
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writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + MPU_RASR);
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}
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/* Region size register */
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static inline void drsr_write(u32 v)
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{
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u32 racr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(31, 16);
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writel_relaxed(v | racr, BASEADDR_V7M_SCB + MPU_RASR);
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}
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/* Region base address register */
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static inline void drbar_write(u32 v)
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{
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writel_relaxed(v, BASEADDR_V7M_SCB + MPU_RBAR);
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}
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static inline u32 drbar_read(void)
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{
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return readl_relaxed(BASEADDR_V7M_SCB + MPU_RBAR);
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}
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/* ARMv7-M only supports a unified MPU, so I-side operations are nop */
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static inline void iracr_write(u32 v) {}
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static inline void irsr_write(u32 v) {}
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static inline void irbar_write(u32 v) {}
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static inline unsigned long irbar_read(void) {return 0;}
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#endif
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static int __init mpu_present(void)
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{
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return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
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@ -166,7 +213,7 @@ static int __init __mpu_max_regions(void)
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*/
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u32 dregions, iregions, mpuir;
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mpuir = read_cpuid(CPUID_MPUIR);
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mpuir = read_cpuid_mputype();
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dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
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@ -181,7 +228,7 @@ static int __init __mpu_max_regions(void)
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static int __init mpu_iside_independent(void)
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{
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/* MPUIR.nU specifies whether there is *not* a unified memory map */
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return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
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return read_cpuid_mputype() & MPUIR_nU;
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}
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static int __init __mpu_min_region_order(void)
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@ -284,9 +331,11 @@ void __init mpu_setup(void)
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MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
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/* Vectors */
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#ifndef CONFIG_CPU_V7M
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err |= mpu_setup_region(region++, vectors_base,
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ilog2(2 * PAGE_SIZE),
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MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL);
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#endif
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if (err) {
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panic("MPU region initialization failure! %d", err);
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} else {
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