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RISC-V: Prefer sstc extension if available
RISC-V ISA has sstc extension which allows updating the next clock event via a CSR (stimecmp) instead of an SBI call. This should happen dynamically if sstc extension is available. Otherwise, it will fallback to SBI call to maintain backward compatibility. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/r/20220722165047.519994-4-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -7,6 +7,9 @@
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* either be read from the "time" and "timeh" CSRs, and can use the SBI to
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* setup events, or directly accessed using MMIO registers.
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*/
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#define pr_fmt(fmt) "riscv-timer: " fmt
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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@ -20,14 +23,28 @@
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#include <linux/of_irq.h>
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#include <clocksource/timer-riscv.h>
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#include <asm/smp.h>
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#include <asm/hwcap.h>
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#include <asm/sbi.h>
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#include <asm/timex.h>
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static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
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static int riscv_clock_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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u64 next_tval = get_cycles64() + delta;
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csr_set(CSR_IE, IE_TIE);
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sbi_set_timer(get_cycles64() + delta);
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if (static_branch_likely(&riscv_sstc_available)) {
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#if defined(CONFIG_32BIT)
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csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
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csr_write(CSR_STIMECMPH, next_tval >> 32);
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#else
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csr_write(CSR_STIMECMP, next_tval);
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#endif
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} else
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sbi_set_timer(next_tval);
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return 0;
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}
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@ -165,6 +182,12 @@ static int __init riscv_timer_init_dt(struct device_node *n)
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if (error)
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pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
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error);
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if (riscv_isa_extension_available(NULL, SSTC)) {
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pr_info("Timer interrupt in S-mode is available via sstc extension\n");
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static_branch_enable(&riscv_sstc_available);
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}
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return error;
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}
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