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KVM: SVM: move MSR_IA32_SPEC_CTRL save/restore to assembly
Restoration of the host IA32_SPEC_CTRL value is probably too late
with respect to the return thunk training sequence.
With respect to the user/kernel boundary, AMD says, "If software chooses
to toggle STIBP (e.g., set STIBP on kernel entry, and clear it on kernel
exit), software should set STIBP to 1 before executing the return thunk
training sequence." I assume the same requirements apply to the guest/host
boundary. The return thunk training sequence is in vmenter.S, quite close
to the VM-exit. On hosts without V_SPEC_CTRL, however, the host's
IA32_SPEC_CTRL value is not restored until much later.
To avoid this, move the restoration of host SPEC_CTRL to assembly and,
for consistency, move the restoration of the guest SPEC_CTRL as well.
This is not particularly difficult, apart from some care to cover both
32- and 64-bit, and to share code between SEV-ES and normal vmentry.
Cc: stable@vger.kernel.org
Fixes: a149180fbc ("x86: Add magic AMD return-thunk")
Suggested-by: Jim Mattson <jmattson@google.com>
Reviewed-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
e287bd005a
commit
9f2febf3f0
@ -196,22 +196,15 @@ void __init check_bugs(void)
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}
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/*
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* NOTE: This function is *only* called for SVM. VMX spec_ctrl handling is
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* done in vmenter.S.
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* NOTE: This function is *only* called for SVM, since Intel uses
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* MSR_IA32_SPEC_CTRL for SSBD.
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*/
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void
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x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
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{
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u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
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u64 guestval, hostval;
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struct thread_info *ti = current_thread_info();
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if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
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if (hostval != guestval) {
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msrval = setguest ? guestval : hostval;
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wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
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}
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}
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/*
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* If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
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* MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
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@ -16,6 +16,7 @@ static void __used common(void)
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BLANK();
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OFFSET(SVM_vcpu_arch_regs, vcpu_svm, vcpu.arch.regs);
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OFFSET(SVM_current_vmcb, vcpu_svm, current_vmcb);
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OFFSET(SVM_spec_ctrl, vcpu_svm, spec_ctrl);
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OFFSET(SVM_vmcb01, vcpu_svm, vmcb01);
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OFFSET(KVM_VMCB_pa, kvm_vmcb_info, pa);
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OFFSET(SD_save_area_pa, svm_cpu_data, save_area_pa);
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@ -720,6 +720,15 @@ static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
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u32 offset;
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u32 *msrpm;
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/*
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* For non-nested case:
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* If the L01 MSR bitmap does not intercept the MSR, then we need to
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* save it.
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*
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* For nested case:
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* If the L02 MSR bitmap does not intercept the MSR, then we need to
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* save it.
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*/
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msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
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to_svm(vcpu)->msrpm;
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@ -3901,16 +3910,16 @@ static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
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return EXIT_FASTPATH_NONE;
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}
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static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
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static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted)
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{
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struct vcpu_svm *svm = to_svm(vcpu);
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guest_state_enter_irqoff();
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if (sev_es_guest(vcpu->kvm))
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__svm_sev_es_vcpu_run(svm);
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__svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted);
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else
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__svm_vcpu_run(svm);
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__svm_vcpu_run(svm, spec_ctrl_intercepted);
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guest_state_exit_irqoff();
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}
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@ -3918,6 +3927,7 @@ static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
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static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
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{
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struct vcpu_svm *svm = to_svm(vcpu);
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bool spec_ctrl_intercepted = msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL);
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trace_kvm_entry(vcpu);
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@ -3976,26 +3986,7 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
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if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
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x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
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svm_vcpu_enter_exit(vcpu);
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/*
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* We do not use IBRS in the kernel. If this vCPU has used the
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* SPEC_CTRL MSR it may have left it on; save the value and
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* turn it off. This is much more efficient than blindly adding
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* it to the atomic save/restore list. Especially as the former
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* (Saving guest MSRs on vmexit) doesn't even exist in KVM.
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*
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* For non-nested case:
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* If the L01 MSR bitmap does not intercept the MSR, then we need to
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* save it.
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*
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* For nested case:
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* If the L02 MSR bitmap does not intercept the MSR, then we need to
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* save it.
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*/
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if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
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unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
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svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
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svm_vcpu_enter_exit(vcpu, spec_ctrl_intercepted);
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if (!sev_es_guest(vcpu->kvm))
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reload_tss(vcpu);
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@ -682,7 +682,7 @@ void sev_es_unmap_ghcb(struct vcpu_svm *svm);
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/* vmenter.S */
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void __svm_sev_es_vcpu_run(struct vcpu_svm *svm);
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void __svm_vcpu_run(struct vcpu_svm *svm);
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void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted);
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void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted);
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#endif
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@ -32,9 +32,69 @@
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.section .noinstr.text, "ax"
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.macro RESTORE_GUEST_SPEC_CTRL
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/* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
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ALTERNATIVE_2 "", \
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"jmp 800f", X86_FEATURE_MSR_SPEC_CTRL, \
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"", X86_FEATURE_V_SPEC_CTRL
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801:
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.endm
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.macro RESTORE_GUEST_SPEC_CTRL_BODY
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800:
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/*
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* SPEC_CTRL handling: if the guest's SPEC_CTRL value differs from the
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* host's, write the MSR. This is kept out-of-line so that the common
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* case does not have to jump.
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*
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* IMPORTANT: To avoid RSB underflow attacks and any other nastiness,
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* there must not be any returns or indirect branches between this code
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* and vmentry.
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*/
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movl SVM_spec_ctrl(%_ASM_DI), %eax
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cmp PER_CPU_VAR(x86_spec_ctrl_current), %eax
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je 801b
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mov $MSR_IA32_SPEC_CTRL, %ecx
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xor %edx, %edx
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wrmsr
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jmp 801b
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.endm
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.macro RESTORE_HOST_SPEC_CTRL
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/* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
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ALTERNATIVE_2 "", \
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"jmp 900f", X86_FEATURE_MSR_SPEC_CTRL, \
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"", X86_FEATURE_V_SPEC_CTRL
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901:
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.endm
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.macro RESTORE_HOST_SPEC_CTRL_BODY
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900:
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/* Same for after vmexit. */
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mov $MSR_IA32_SPEC_CTRL, %ecx
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/*
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* Load the value that the guest had written into MSR_IA32_SPEC_CTRL,
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* if it was not intercepted during guest execution.
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*/
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cmpb $0, (%_ASM_SP)
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jnz 998f
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rdmsr
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movl %eax, SVM_spec_ctrl(%_ASM_DI)
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998:
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/* Now restore the host value of the MSR if different from the guest's. */
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movl PER_CPU_VAR(x86_spec_ctrl_current), %eax
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cmp SVM_spec_ctrl(%_ASM_DI), %eax
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je 901b
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xor %edx, %edx
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wrmsr
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jmp 901b
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.endm
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/**
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* __svm_vcpu_run - Run a vCPU via a transition to SVM guest mode
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* @svm: struct vcpu_svm *
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* @spec_ctrl_intercepted: bool
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*/
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SYM_FUNC_START(__svm_vcpu_run)
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push %_ASM_BP
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@ -54,17 +114,26 @@ SYM_FUNC_START(__svm_vcpu_run)
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* order compared to when they are needed.
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*/
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/* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
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push %_ASM_ARG2
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/* Needed to restore access to percpu variables. */
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__ASM_SIZE(push) PER_CPU_VAR(svm_data + SD_save_area_pa)
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/* Save @svm. */
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/* Finally save @svm. */
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push %_ASM_ARG1
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.ifnc _ASM_ARG1, _ASM_DI
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/* Move @svm to RDI. */
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/*
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* Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
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* and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
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*/
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mov %_ASM_ARG1, %_ASM_DI
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.endif
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/* Clobbers RAX, RCX, RDX. */
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RESTORE_GUEST_SPEC_CTRL
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/*
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* Use a single vmcb (vmcb01 because it's always valid) for
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* context switching guest state via VMLOAD/VMSAVE, that way
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@ -142,6 +211,9 @@ SYM_FUNC_START(__svm_vcpu_run)
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FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
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#endif
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/* Clobbers RAX, RCX, RDX. */
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RESTORE_HOST_SPEC_CTRL
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
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* untrained as soon as we exit the VM and are back to the
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@ -177,6 +249,9 @@ SYM_FUNC_START(__svm_vcpu_run)
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xor %r15d, %r15d
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#endif
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/* "Pop" @spec_ctrl_intercepted. */
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pop %_ASM_BX
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pop %_ASM_BX
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#ifdef CONFIG_X86_64
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@ -191,6 +266,9 @@ SYM_FUNC_START(__svm_vcpu_run)
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pop %_ASM_BP
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RET
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RESTORE_GUEST_SPEC_CTRL_BODY
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RESTORE_HOST_SPEC_CTRL_BODY
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10: cmpb $0, kvm_rebooting
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jne 2b
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ud2
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@ -214,6 +292,7 @@ SYM_FUNC_END(__svm_vcpu_run)
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/**
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* __svm_sev_es_vcpu_run - Run a SEV-ES vCPU via a transition to SVM guest mode
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* @svm: struct vcpu_svm *
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* @spec_ctrl_intercepted: bool
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*/
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SYM_FUNC_START(__svm_sev_es_vcpu_run)
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push %_ASM_BP
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@ -228,8 +307,30 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run)
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#endif
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push %_ASM_BX
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/*
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* Save variables needed after vmexit on the stack, in inverse
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* order compared to when they are needed.
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*/
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/* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
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push %_ASM_ARG2
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/* Save @svm. */
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push %_ASM_ARG1
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.ifnc _ASM_ARG1, _ASM_DI
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/*
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* Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
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* and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
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*/
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mov %_ASM_ARG1, %_ASM_DI
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.endif
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/* Clobbers RAX, RCX, RDX. */
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RESTORE_GUEST_SPEC_CTRL
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/* Get svm->current_vmcb->pa into RAX. */
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mov SVM_current_vmcb(%_ASM_ARG1), %_ASM_AX
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mov SVM_current_vmcb(%_ASM_DI), %_ASM_AX
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mov KVM_VMCB_pa(%_ASM_AX), %_ASM_AX
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/* Enter guest mode */
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@ -239,11 +340,17 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run)
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2: cli
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/* Pop @svm to RDI, guest registers have been saved already. */
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pop %_ASM_DI
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#ifdef CONFIG_RETPOLINE
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/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
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FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
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#endif
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/* Clobbers RAX, RCX, RDX. */
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RESTORE_HOST_SPEC_CTRL
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
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* untrained as soon as we exit the VM and are back to the
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@ -253,6 +360,9 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run)
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*/
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UNTRAIN_RET
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/* "Pop" @spec_ctrl_intercepted. */
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pop %_ASM_BX
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pop %_ASM_BX
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#ifdef CONFIG_X86_64
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@ -267,6 +377,9 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run)
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pop %_ASM_BP
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RET
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RESTORE_GUEST_SPEC_CTRL_BODY
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RESTORE_HOST_SPEC_CTRL_BODY
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3: cmpb $0, kvm_rebooting
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jne 2b
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ud2
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