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riscv: clear the instruction cache and all registers when booting

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When we get booted we want a clear slate without any leaks from previous
supervisors or the firmware.  Flush the instruction cache and then clear
all registers to known good values.  This is really important for the
upcoming nommu support that runs on M-mode, but can't really harm when
running in S-mode either.  Vaguely based on the concepts from opensbi.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
This commit is contained in:
Christoph Hellwig 2019-10-28 13:10:40 +01:00 committed by Paul Walmsley
parent accb9dbc4a
commit 9e80635619
2 changed files with 88 additions and 1 deletions
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1
arch/riscv/include/asm/csr.h
View File

@ -92,6 +92,7 @@
#define CSR_SATP 0x180 #define CSR_SATP 0x180
#define CSR_MSTATUS 0x300 #define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MIE 0x304 #define CSR_MIE 0x304
#define CSR_MTVEC 0x305 #define CSR_MTVEC 0x305
#define CSR_MSCRATCH 0x340 #define CSR_MSCRATCH 0x340

88
arch/riscv/kernel/head.S
View File

@ -11,6 +11,7 @@
#include <asm/thread_info.h> #include <asm/thread_info.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/csr.h> #include <asm/csr.h>
#include <asm/hwcap.h>
#include <asm/image.h> #include <asm/image.h>
__INIT __INIT
@ -51,12 +52,18 @@ _start_kernel:
csrw CSR_IP, zero csrw CSR_IP, zero
#ifdef CONFIG_RISCV_M_MODE #ifdef CONFIG_RISCV_M_MODE
/* flush the instruction cache */
fence.i
/* Reset all registers except ra, a0, a1 */
call reset_regs
/* /*
* The hartid in a0 is expected later on, and we have no firmware * The hartid in a0 is expected later on, and we have no firmware
* to hand it to us. * to hand it to us.
*/ */
csrr a0, CSR_MHARTID csrr a0, CSR_MHARTID
#endif #endif /* CONFIG_RISCV_M_MODE */
/* Load the global pointer */ /* Load the global pointer */
.option push .option push
@ -203,6 +210,85 @@ relocate:
j .Lsecondary_park j .Lsecondary_park
END(_start) END(_start)
#ifdef CONFIG_RISCV_M_MODE
ENTRY(reset_regs)
li sp, 0
li gp, 0
li tp, 0
li t0, 0
li t1, 0
li t2, 0
li s0, 0
li s1, 0
li a2, 0
li a3, 0
li a4, 0
li a5, 0
li a6, 0
li a7, 0
li s2, 0
li s3, 0
li s4, 0
li s5, 0
li s6, 0
li s7, 0
li s8, 0
li s9, 0
li s10, 0
li s11, 0
li t3, 0
li t4, 0
li t5, 0
li t6, 0
csrw sscratch, 0
#ifdef CONFIG_FPU
csrr t0, CSR_MISA
andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
bnez t0, .Lreset_regs_done
li t1, SR_FS
csrs CSR_STATUS, t1
fmv.s.x f0, zero
fmv.s.x f1, zero
fmv.s.x f2, zero
fmv.s.x f3, zero
fmv.s.x f4, zero
fmv.s.x f5, zero
fmv.s.x f6, zero
fmv.s.x f7, zero
fmv.s.x f8, zero
fmv.s.x f9, zero
fmv.s.x f10, zero
fmv.s.x f11, zero
fmv.s.x f12, zero
fmv.s.x f13, zero
fmv.s.x f14, zero
fmv.s.x f15, zero
fmv.s.x f16, zero
fmv.s.x f17, zero
fmv.s.x f18, zero
fmv.s.x f19, zero
fmv.s.x f20, zero
fmv.s.x f21, zero
fmv.s.x f22, zero
fmv.s.x f23, zero
fmv.s.x f24, zero
fmv.s.x f25, zero
fmv.s.x f26, zero
fmv.s.x f27, zero
fmv.s.x f28, zero
fmv.s.x f29, zero
fmv.s.x f30, zero
fmv.s.x f31, zero
csrw fcsr, 0
/* note that the caller must clear SR_FS */
#endif /* CONFIG_FPU */
.Lreset_regs_done:
ret
END(reset_regs)
#endif /* CONFIG_RISCV_M_MODE */
__PAGE_ALIGNED_BSS __PAGE_ALIGNED_BSS
/* Empty zero page */ /* Empty zero page */
.balign PAGE_SIZE .balign PAGE_SIZE