mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-10 12:34:07 +08:00
net: dsa: mv88e6xxx: add RMU disable op
The RMU mode bits moved a lot within the Global Control 2 register of the Marvell switch families. Add an .rmu_disable op to support at least 3 known alternatives. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
23c9891996
commit
9e5baf9b36
@ -1069,6 +1069,14 @@ static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
|
||||||
|
{
|
||||||
|
if (chip->info->ops->rmu_disable)
|
||||||
|
return chip->info->ops->rmu_disable(chip);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
|
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
|
||||||
{
|
{
|
||||||
if (chip->info->ops->pot_clear)
|
if (chip->info->ops->pot_clear)
|
||||||
@ -2263,6 +2271,10 @@ static int mv88e6xxx_setup(struct dsa_switch *ds)
|
|||||||
if (err)
|
if (err)
|
||||||
goto unlock;
|
goto unlock;
|
||||||
|
|
||||||
|
err = mv88e6xxx_rmu_setup(chip);
|
||||||
|
if (err)
|
||||||
|
goto unlock;
|
||||||
|
|
||||||
err = mv88e6xxx_rsvd2cpu_setup(chip);
|
err = mv88e6xxx_rsvd2cpu_setup(chip);
|
||||||
if (err)
|
if (err)
|
||||||
goto unlock;
|
goto unlock;
|
||||||
@ -2530,6 +2542,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
|
|||||||
.ppu_enable = mv88e6185_g1_ppu_enable,
|
.ppu_enable = mv88e6185_g1_ppu_enable,
|
||||||
.ppu_disable = mv88e6185_g1_ppu_disable,
|
.ppu_disable = mv88e6185_g1_ppu_disable,
|
||||||
.reset = mv88e6185_g1_reset,
|
.reset = mv88e6185_g1_reset,
|
||||||
|
.rmu_disable = mv88e6085_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6341_serdes_power,
|
.serdes_power = mv88e6341_serdes_power,
|
||||||
@ -2588,6 +2601,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6085_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
||||||
};
|
};
|
||||||
@ -2815,6 +2829,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6352_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6352_serdes_power,
|
.serdes_power = mv88e6352_serdes_power,
|
||||||
@ -2888,6 +2903,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6352_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6352_serdes_power,
|
.serdes_power = mv88e6352_serdes_power,
|
||||||
@ -2953,6 +2969,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6390_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6390_serdes_power,
|
.serdes_power = mv88e6390_serdes_power,
|
||||||
@ -2989,6 +3006,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6390_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6390_serdes_power,
|
.serdes_power = mv88e6390_serdes_power,
|
||||||
@ -3025,6 +3043,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6390_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6390_serdes_power,
|
.serdes_power = mv88e6390_serdes_power,
|
||||||
@ -3062,6 +3081,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6352_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6352_serdes_power,
|
.serdes_power = mv88e6352_serdes_power,
|
||||||
@ -3100,6 +3120,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6390_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6390_serdes_power,
|
.serdes_power = mv88e6390_serdes_power,
|
||||||
@ -3316,6 +3337,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6352_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
.vtu_getnext = mv88e6352_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6352_serdes_power,
|
.serdes_power = mv88e6352_serdes_power,
|
||||||
@ -3359,6 +3381,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6390_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6390_serdes_power,
|
.serdes_power = mv88e6390_serdes_power,
|
||||||
@ -3399,6 +3422,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
|
|||||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||||
.pot_clear = mv88e6xxx_g2_pot_clear,
|
.pot_clear = mv88e6xxx_g2_pot_clear,
|
||||||
.reset = mv88e6352_g1_reset,
|
.reset = mv88e6352_g1_reset,
|
||||||
|
.rmu_disable = mv88e6390_g1_rmu_disable,
|
||||||
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
.vtu_getnext = mv88e6390_g1_vtu_getnext,
|
||||||
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
|
||||||
.serdes_power = mv88e6390_serdes_power,
|
.serdes_power = mv88e6390_serdes_power,
|
||||||
|
@ -432,6 +432,9 @@ struct mv88e6xxx_ops {
|
|||||||
|
|
||||||
/* Interface to the AVB/PTP registers */
|
/* Interface to the AVB/PTP registers */
|
||||||
const struct mv88e6xxx_avb_ops *avb_ops;
|
const struct mv88e6xxx_avb_ops *avb_ops;
|
||||||
|
|
||||||
|
/* Remote Management Unit operations */
|
||||||
|
int (*rmu_disable)(struct mv88e6xxx_chip *chip);
|
||||||
};
|
};
|
||||||
|
|
||||||
struct mv88e6xxx_irq_ops {
|
struct mv88e6xxx_irq_ops {
|
||||||
|
@ -373,6 +373,24 @@ int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
|
|||||||
return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
|
return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
|
||||||
|
{
|
||||||
|
return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
|
||||||
|
MV88E6085_G1_CTL2_RM_ENABLE, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
|
||||||
|
{
|
||||||
|
return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
|
||||||
|
MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
|
||||||
|
}
|
||||||
|
|
||||||
|
int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
|
||||||
|
{
|
||||||
|
return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
|
||||||
|
MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
|
||||||
|
}
|
||||||
|
|
||||||
int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
|
int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
|
||||||
{
|
{
|
||||||
u16 val;
|
u16 val;
|
||||||
|
@ -207,6 +207,22 @@
|
|||||||
#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
|
#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
|
||||||
#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
|
#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
|
||||||
#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
|
#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
|
||||||
|
#define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000
|
||||||
|
#define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000
|
||||||
|
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000
|
||||||
|
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000
|
||||||
|
#define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000
|
||||||
|
#define MV88E6085_G1_CTL2_DA_CHECK 0x4000
|
||||||
|
#define MV88E6085_G1_CTL2_P10RM 0x2000
|
||||||
|
#define MV88E6085_G1_CTL2_RM_ENABLE 0x1000
|
||||||
|
#define MV88E6352_G1_CTL2_DA_CHECK 0x0800
|
||||||
|
#define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700
|
||||||
|
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000
|
||||||
|
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100
|
||||||
|
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200
|
||||||
|
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300
|
||||||
|
#define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600
|
||||||
|
#define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700
|
||||||
#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
|
#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
|
||||||
|
|
||||||
/* Offset 0x1D: Stats Operation Register */
|
/* Offset 0x1D: Stats Operation Register */
|
||||||
@ -257,6 +273,10 @@ int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
|
|||||||
|
|
||||||
int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
|
int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
|
||||||
|
|
||||||
|
int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
|
||||||
|
int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
|
||||||
|
int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
|
||||||
|
|
||||||
int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
|
int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
|
||||||
|
|
||||||
int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
|
int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
|
||||||
|
Loading…
Reference in New Issue
Block a user