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PCI: Move private DT related functions into private header
The functions in linux/of_pci.h are primarily used by host bridge drivers, so they can be private to drivers/pci/. The remaining functions are still used mostly in host bridge drivers that still live in arch specific code. Hopefully someday, those will get moved into drivers/pci as well. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
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@ -27,6 +27,7 @@
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "../pci.h"
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#include "pcie-designware.h"
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/* PCIe controller wrapper DRA7XX configuration registers */
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@ -15,6 +15,7 @@
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#include <linux/pci_regs.h>
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#include <linux/platform_device.h>
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#include "../pci.h"
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#include "pcie-designware.h"
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static struct pci_ops dw_pcie_ops;
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@ -19,6 +19,8 @@
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include "../pci.h"
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/* PCIe core registers */
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#define PCIE_CORE_CMD_STATUS_REG 0x4
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#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
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@ -28,6 +28,8 @@
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include "../pci.h"
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/*
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* Special configuration registers directly in the first few words
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* in I/O space.
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@ -21,6 +21,8 @@
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include "../pci.h"
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/*
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* PCIe unit register offsets.
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*/
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@ -21,6 +21,8 @@
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include "../pci.h"
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/* AHB-PCI Bridge PCI communication registers */
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#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
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@ -40,6 +40,8 @@
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#include <soc/tegra/cpuidle.h>
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#include <soc/tegra/pmc.h>
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#include "../pci.h"
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#define INT_PCI_MSI_NR (8 * 32)
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/* register definitions */
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@ -33,6 +33,8 @@
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include "../pci.h"
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#define V3_PCI_VENDOR 0x00000000
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#define V3_PCI_DEVICE 0x00000002
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#define V3_PCI_CMD 0x00000004
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@ -22,6 +22,8 @@
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "../pci.h"
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#define PCIECORE_CTLANDSTATUS 0x50
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#define PIM1_1L 0x80
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#define IBAR2 0x98
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@ -17,6 +17,8 @@
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "../pci.h"
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#define RP_TX_REG0 0x2000
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#define RP_TX_REG1 0x2004
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#define RP_TX_CNTRL 0x2008
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@ -16,6 +16,7 @@
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include "../pci.h"
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#include "pcie-iproc.h"
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static const struct of_device_id iproc_pcie_of_match_table[] = {
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@ -22,6 +22,8 @@
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include "../pci.h"
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/* PCIe shared registers */
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#define PCIE_SYS_CFG 0x00
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#define PCIE_INT_ENABLE 0x0c
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@ -28,6 +28,8 @@
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include "../pci.h"
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#define PCIECAR 0x000010
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#define PCIECCTLR 0x000018
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#define CONFIG_SEND_ENABLE (1 << 31)
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@ -36,6 +36,8 @@
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#include <linux/reset.h>
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#include <linux/regmap.h>
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#include "../pci.h"
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/*
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* The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
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* bits. This allows atomic updates of the register without locking.
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@ -21,6 +21,8 @@
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#include <linux/platform_device.h>
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#include <linux/irqchip/chained_irq.h>
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#include "../pci.h"
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/* Bridge core config registers */
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#define BRCFG_PCIE_RX0 0x00000000
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#define BRCFG_INTERRUPT 0x00000010
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@ -23,6 +23,8 @@
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include "../pci.h"
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/* Register definitions */
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#define XILINX_PCIE_REG_BIR 0x00000130
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#define XILINX_PCIE_REG_IDR 0x00000138
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@ -407,4 +407,44 @@ static inline u64 pci_rebar_size_to_bytes(int size)
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return 1ULL << (size + 20);
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}
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struct device_node;
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#ifdef CONFIG_OF
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int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
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int of_get_pci_domain_nr(struct device_node *node);
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int of_pci_get_max_link_speed(struct device_node *node);
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#else
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static inline int
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of_pci_parse_bus_range(struct device_node *node, struct resource *res)
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{
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return -EINVAL;
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}
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static inline int
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of_get_pci_domain_nr(struct device_node *node)
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{
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return -1;
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}
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static inline int
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of_pci_get_max_link_speed(struct device_node *node)
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{
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return -EINVAL;
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}
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#endif /* CONFIG_OF */
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#if defined(CONFIG_OF_ADDRESS)
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int of_pci_get_host_bridge_resources(struct device_node *dev,
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unsigned char busno, unsigned char bus_max,
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struct list_head *resources, resource_size_t *io_base);
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#else
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static inline int of_pci_get_host_bridge_resources(struct device_node *dev,
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unsigned char busno, unsigned char bus_max,
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struct list_head *resources, resource_size_t *io_base)
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{
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return -EINVAL;
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}
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#endif
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#endif /* DRIVERS_PCI_H */
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@ -13,9 +13,6 @@ struct device_node;
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struct device_node *of_pci_find_child_device(struct device_node *parent,
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unsigned int devfn);
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int of_pci_get_devfn(struct device_node *np);
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int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
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int of_get_pci_domain_nr(struct device_node *node);
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int of_pci_get_max_link_speed(struct device_node *node);
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void of_pci_check_probe_only(void);
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int of_pci_map_rid(struct device_node *np, u32 rid,
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const char *map_name, const char *map_mask_name,
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@ -32,18 +29,6 @@ static inline int of_pci_get_devfn(struct device_node *np)
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return -EINVAL;
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}
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static inline int
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of_pci_parse_bus_range(struct device_node *node, struct resource *res)
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{
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return -EINVAL;
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}
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static inline int
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of_get_pci_domain_nr(struct device_node *node)
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{
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return -1;
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}
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static inline int of_pci_map_rid(struct device_node *np, u32 rid,
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const char *map_name, const char *map_mask_name,
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struct device_node **target, u32 *id_out)
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@ -51,12 +36,6 @@ static inline int of_pci_map_rid(struct device_node *np, u32 rid,
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return -EINVAL;
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}
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static inline int
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of_pci_get_max_link_speed(struct device_node *node)
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{
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return -EINVAL;
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}
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static inline void of_pci_check_probe_only(void) { }
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#endif
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@ -70,17 +49,4 @@ of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
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}
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#endif
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#if defined(CONFIG_OF_ADDRESS)
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int of_pci_get_host_bridge_resources(struct device_node *dev,
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unsigned char busno, unsigned char bus_max,
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struct list_head *resources, resource_size_t *io_base);
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#else
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static inline int of_pci_get_host_bridge_resources(struct device_node *dev,
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unsigned char busno, unsigned char bus_max,
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struct list_head *resources, resource_size_t *io_base)
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{
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return -EINVAL;
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}
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#endif
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#endif
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