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spi: pxa2xx: replace ugly table by approximation
The Quark SoC data sheet describes the baud rate setting using fractional divider. The subset of possible values represented by a table suggests that the divisor has one block that could divide by 5. This explains the number of the beast in some cases in the table. Thus, in this particular case the divisor can be evaluated as 5^i * 2^j * 2 * k, where i = [0, 1] j = [0, 23] k = [1, 256] There are few cases as mentioned in the data sheet, i.e. better form of the clock signal will be in case if DDS_CLK_RATE either 2^n or 2/5. It's also possible to use any value that is less or equal to 0x33333 (1/5/16 = 1/80). All three cases are compared to each other and the one that suits better is chosen by the approximation algorithm. Anyone can play with the script [1] that represents the algorithm. [1] https://gist.github.com/06b084488b3629898121 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Andy Shevchenko
Mark Brown
parent
025ffe88ee
commit
9df461eca1
@ -20,6 +20,7 @@
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/spi/spi.h>
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@ -63,54 +64,6 @@ MODULE_ALIAS("platform:pxa2xx-spi");
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#define LPSS_TX_LOTHRESH_DFLT 160
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#define LPSS_TX_HITHRESH_DFLT 224
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struct quark_spi_rate {
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u32 bitrate;
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u32 dds_clk_rate;
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u32 clk_div;
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};
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/*
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* 'rate', 'dds', 'clk_div' lookup table, which is defined in
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* the Quark SPI datasheet.
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*/
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static const struct quark_spi_rate quark_spi_rate_table[] = {
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/* bitrate, dds_clk_rate, clk_div */
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{50000000, 0x800000, 0},
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{40000000, 0x666666, 0},
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{25000000, 0x400000, 0},
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{20000000, 0x666666, 1},
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{16667000, 0x800000, 2},
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{13333000, 0x666666, 2},
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{12500000, 0x200000, 0},
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{10000000, 0x800000, 4},
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{8000000, 0x666666, 4},
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{6250000, 0x400000, 3},
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{5000000, 0x400000, 4},
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{4000000, 0x666666, 9},
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{3125000, 0x80000, 0},
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{2500000, 0x400000, 9},
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{2000000, 0x666666, 19},
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{1563000, 0x40000, 0},
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{1250000, 0x200000, 9},
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{1000000, 0x400000, 24},
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{800000, 0x666666, 49},
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{781250, 0x20000, 0},
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{625000, 0x200000, 19},
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{500000, 0x400000, 49},
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{400000, 0x666666, 99},
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{390625, 0x10000, 0},
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{250000, 0x400000, 99},
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{200000, 0x666666, 199},
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{195313, 0x8000, 0},
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{125000, 0x100000, 49},
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{100000, 0x200000, 124},
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{50000, 0x100000, 124},
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{25000, 0x80000, 124},
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{10016, 0x20000, 77},
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{5040, 0x20000, 154},
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{1002, 0x8000, 194},
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};
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/* Offset from drv_data->lpss_base */
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#define GENERAL_REG 0x08
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#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
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@ -697,25 +650,124 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
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}
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/*
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* The Quark SPI data sheet gives a table, and for the given 'rate',
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* the 'dds' and 'clk_div' can be found in the table.
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* The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
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* input frequency by fractions of 2^24. It also has a divider by 5.
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*
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* There are formulas to get baud rate value for given input frequency and
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* divider parameters, such as DDS_CLK_RATE and SCR:
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*
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* Fsys = 200MHz
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*
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* Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
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* Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
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*
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* DDS_CLK_RATE either 2^n or 2^n / 5.
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* SCR is in range 0 .. 255
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*
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* Divisor = 5^i * 2^j * 2 * k
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* i = [0, 1] i = 1 iff j = 0 or j > 3
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* j = [0, 23] j = 0 iff i = 1
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* k = [1, 256]
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* Special case: j = 0, i = 1: Divisor = 2 / 5
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*
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* Accordingly to the specification the recommended values for DDS_CLK_RATE
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* are:
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* Case 1: 2^n, n = [0, 23]
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* Case 2: 2^24 * 2 / 5 (0x666666)
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* Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
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*
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* In all cases the lowest possible value is better.
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*
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* The function calculates parameters for all cases and chooses the one closest
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* to the asked baud rate.
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*/
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static u32 quark_x1000_set_clk_regvals(u32 rate, u32 *dds, u32 *clk_div)
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static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
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{
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unsigned int i;
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unsigned long xtal = 200000000;
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unsigned long fref = xtal / 2; /* mandatory division by 2,
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see (2) */
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/* case 3 */
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unsigned long fref1 = fref / 2; /* case 1 */
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unsigned long fref2 = fref * 2 / 5; /* case 2 */
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unsigned long scale;
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unsigned long q, q1, q2;
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long r, r1, r2;
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u32 mul;
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for (i = 0; i < ARRAY_SIZE(quark_spi_rate_table); i++) {
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if (rate >= quark_spi_rate_table[i].bitrate) {
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*dds = quark_spi_rate_table[i].dds_clk_rate;
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*clk_div = quark_spi_rate_table[i].clk_div;
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return quark_spi_rate_table[i].bitrate;
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/* Case 1 */
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/* Set initial value for DDS_CLK_RATE */
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mul = (1 << 24) >> 1;
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/* Calculate initial quot */
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q1 = DIV_ROUND_CLOSEST(fref1, rate);
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/* Scale q1 if it's too big */
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if (q1 > 256) {
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/* Scale q1 to range [1, 512] */
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scale = fls_long(q1 - 1);
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if (scale > 9) {
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q1 >>= scale - 9;
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mul >>= scale - 9;
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}
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/* Round the result if we have a remainder */
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q1 += q1 & 1;
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}
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/* Decrease DDS_CLK_RATE as much as we can without loss in precision */
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scale = __ffs(q1);
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q1 >>= scale;
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mul >>= scale;
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/* Get the remainder */
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r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
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/* Case 2 */
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q2 = DIV_ROUND_CLOSEST(fref2, rate);
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r2 = abs(fref2 / q2 - rate);
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/*
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* Choose the best between two: less remainder we have the better. We
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* can't go case 2 if q2 is greater than 256 since SCR register can
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* hold only values 0 .. 255.
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*/
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if (r2 >= r1 || q2 > 256) {
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/* case 1 is better */
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r = r1;
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q = q1;
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} else {
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/* case 2 is better */
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r = r2;
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q = q2;
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mul = (1 << 24) * 2 / 5;
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}
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/* Check case 3 only If the divisor is big enough */
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if (fref / rate >= 80) {
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u64 fssp;
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u32 m;
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/* Calculate initial quot */
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q1 = DIV_ROUND_CLOSEST(fref, rate);
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m = (1 << 24) / q1;
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/* Get the remainder */
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fssp = (u64)fref * m;
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do_div(fssp, 1 << 24);
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r1 = abs(fssp - rate);
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/* Choose this one if it suits better */
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if (r1 < r) {
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/* case 3 is better */
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q = 1;
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mul = m;
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}
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}
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*dds = quark_spi_rate_table[i-1].dds_clk_rate;
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*clk_div = quark_spi_rate_table[i-1].clk_div;
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return quark_spi_rate_table[i-1].bitrate;
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*dds = mul;
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return q - 1;
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}
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static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
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@ -738,7 +790,7 @@ static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
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switch (drv_data->ssp_type) {
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case QUARK_X1000_SSP:
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quark_x1000_set_clk_regvals(rate, &chip->dds_rate, &clk_div);
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clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
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default:
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clk_div = ssp_get_clk_div(drv_data, rate);
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}
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