arm64: dts: qcom: sm6115: Add USB SS qmp phy node

Add USB superspeed qmp phy node to dtsi.

Make sure that the various board dts files (which include sm4250.dtsi file)
continue to work as intended.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516150511.2346357-4-bhupesh.sharma@linaro.org
This commit is contained in:
Bhupesh Sharma 2023-05-16 20:35:10 +05:30 committed by Bjorn Andersson
parent a782318023
commit 9dd5f6dba7
3 changed files with 33 additions and 2 deletions

View File

@ -242,6 +242,9 @@
&usb_dwc3 {
maximum-speed = "high-speed";
dr_mode = "peripheral";
phys = <&usb_hsphy>;
phy-names = "usb2-phy";
};
&usb_hsphy {

View File

@ -828,6 +828,31 @@
<&apps_smmu 0x9F 0>;
};
usb_qmpphy: phy@1615000 {
compatible = "qcom,sm6115-qmp-usb3-phy";
reg = <0x0 0x01615000 0x0 0x1000>;
clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "cfg_ahb",
"ref",
"com_aux",
"pipe";
resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
<&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
reset-names = "phy", "phy_phy";
#clock-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
qfprom@1b40000 {
compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
reg = <0x0 0x01b40000 0x0 0x7000>;
@ -1278,8 +1303,8 @@
compatible = "snps,dwc3";
reg = <0x0 0x04e00000 0x0 0xcd00>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb_hsphy>;
phy-names = "usb2-phy";
phys = <&usb_hsphy>, <&usb_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
iommus = <&apps_smmu 0x120 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;

View File

@ -306,6 +306,9 @@
&usb_dwc3 {
maximum-speed = "high-speed";
dr_mode = "peripheral";
phys = <&usb_hsphy>;
phy-names = "usb2-phy";
};
&usb_hsphy {