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clk: socfpga: agilex: fix the parents of the psi_ref_clk

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The psi_ref_clk comes from the C2 node of the main_pll and periph_pll,
not the C3.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210713144621.605140-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Dinh Nguyen 2021-07-13 09:46:19 -05:00 committed by Stephen Boyd
parent e73f0f0ee7
commit 9d563236cc
1 changed files with 4 additions and 4 deletions
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8
drivers/clk/socfpga/clk-agilex.c
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@ -107,10 +107,10 @@ static const struct clk_parent_data gpio_db_free_mux[] = {
};
static const struct clk_parent_data psi_ref_free_mux[] = {
{ .fw_name = "main_pll_c3",
.name = "main_pll_c3", },
{ .fw_name = "peri_pll_c3",
.name = "peri_pll_c3", },
{ .fw_name = "main_pll_c2",
.name = "main_pll_c2", },
{ .fw_name = "peri_pll_c2",
.name = "peri_pll_c2", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",