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powerpc/64: treat low kernel text as irqs soft-masked
Treat code below __end_soft_masked as soft-masked for the purpose of alternate return. 64s already mostly does this for scv entry. This will be used to exit from interrupts without disabling MSR[EE]. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210617155116.2167984-12-npiggin@gmail.com
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@ -146,8 +146,13 @@ static inline void interrupt_enter_prepare(struct pt_regs *regs, struct interrup
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* CT_WARN_ON comes here via program_check_exception,
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* so avoid recursion.
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*/
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if (TRAP(regs) != INTERRUPT_PROGRAM)
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if (TRAP(regs) != INTERRUPT_PROGRAM) {
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CT_WARN_ON(ct_state() != CONTEXT_KERNEL);
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BUG_ON(regs->nip < (unsigned long)__end_soft_masked);
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}
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/* Move this under a debugging check */
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if (arch_irq_disabled_regs(regs))
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BUG_ON(search_kernel_restart_table(regs->nip));
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}
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#endif
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@ -238,8 +243,8 @@ static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struct inte
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !(regs->msr & MSR_PR) &&
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regs->nip < (unsigned long)__end_interrupts) {
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// Kernel code running below __end_interrupts is
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regs->nip < (unsigned long)__end_soft_masked) {
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// Kernel code running below __end_soft_masked is
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// implicitly soft-masked.
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regs->softe = IRQS_ALL_DISABLED;
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}
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@ -342,7 +342,17 @@ ret_from_mc_except:
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#define PROLOG_ADDITION_MASKABLE_GEN(n) \
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lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \
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andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \
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bne masked_interrupt_book3e_##n
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bne masked_interrupt_book3e_##n; \
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/* Kernel code below __end_soft_masked is implicitly masked */ \
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andi. r10,r11,MSR_PR; \
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bne 1f; /* user -> not masked */ \
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std r14,PACA_EXGEN+EX_R14(r13); \
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LOAD_REG_IMMEDIATE_SYM(r14, r10, __end_soft_masked); \
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mfspr r10,SPRN_SRR0; \
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cmpld r10,r14; \
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ld r14,PACA_EXGEN+EX_R14(r13); \
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blt masked_interrupt_book3e_##n; \
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1:
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/*
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* Additional regs must be re-loaded from paca before EXCEPTION_COMMON* is
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@ -430,10 +430,13 @@ DEFINE_FIXED_SYMBOL(\name\()_common_real)
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andi. r10,r12,MSR_PR
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bne 2f
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/* Kernel code running below __end_interrupts is implicitly
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* soft-masked */
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LOAD_HANDLER(r10, __end_interrupts)
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/*
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* Kernel code running below __end_soft_masked is implicitly
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* soft-masked
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*/
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LOAD_HANDLER(r10, __end_soft_masked)
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cmpld r11,r10
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li r10,IMASK
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blt- 1f
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@ -751,17 +754,17 @@ __start_interrupts:
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* scv instructions enter the kernel without changing EE, RI, ME, or HV.
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* In particular, this means we can take a maskable interrupt at any point
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* in the scv handler, which is unlike any other interrupt. This is solved
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* by treating the instruction addresses below __end_interrupts as being
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* by treating the instruction addresses below __end_soft_masked as being
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* soft-masked.
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*
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* AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
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* ensure scv is never executed with relocation off, which means AIL-0
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* should never happen.
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*
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* Before leaving the below __end_interrupts text, at least of the following
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* must be true:
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* Before leaving the following inside-__end_soft_masked text, at least of the
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* following must be true:
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* - MSR[PR]=1 (i.e., return to userspace)
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* - MSR_EE|MSR_RI is set (no reentrant exceptions)
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* - MSR_EE|MSR_RI is clear (no reentrant exceptions)
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* - Standard kernel environment is set up (stack, paca, etc)
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*
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* Call convention:
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@ -2957,7 +2960,7 @@ MASKED_INTERRUPT hsrr=1
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USE_FIXED_SECTION(virt_trampolines)
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/*
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* All code below __end_interrupts is treated as soft-masked. If
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* All code below __end_soft_masked is treated as soft-masked. If
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* any code runs here with MSR[EE]=1, it must then cope with pending
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* soft interrupt being raised (i.e., by ensuring it is replayed).
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*
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@ -632,4 +632,8 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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interrupt_return_macro srr
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#ifdef CONFIG_PPC_BOOK3S
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interrupt_return_macro hsrr
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#endif
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#endif /* CONFIG_PPC_BOOK3S */
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.globl __end_soft_masked
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__end_soft_masked:
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DEFINE_FIXED_SYMBOL(__end_soft_masked)
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