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rtc: remove sirfsoc driver
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210120154158.1860736-2-arnd@kernel.org
This commit is contained in:
Arnd Bergmann
Alexandre Belloni
parent
12b1ef321a
commit
9d0735519f
@ -1,13 +0,0 @@
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SiRFSoC Real Time Clock
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Required properties:
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- compatible: must be "sirf,prima2-sysrtc"
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- reg: address range of rtc register set.
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- interrupts: rtc alarm interrupts.
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Example:
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rtc@2000 {
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compatible = "sirf,prima2-sysrtc";
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reg = <0x2000 0x1000>;
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interrupts = <52 53 54>;
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};
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@ -1793,13 +1793,6 @@ config RTC_DRV_IMX_SC
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If you say yes here you get support for the NXP i.MX System
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If you say yes here you get support for the NXP i.MX System
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Controller RTC module.
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Controller RTC module.
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config RTC_DRV_SIRFSOC
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tristate "SiRFSOC RTC"
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depends on ARCH_SIRF
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help
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Say "yes" here to support the real time clock on SiRF SOC chips.
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This driver can also be built as a module called rtc-sirfsoc.
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config RTC_DRV_ST_LPC
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config RTC_DRV_ST_LPC
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tristate "STMicroelectronics LPC RTC"
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tristate "STMicroelectronics LPC RTC"
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depends on ARCH_STI
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depends on ARCH_STI
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@ -154,7 +154,6 @@ obj-$(CONFIG_RTC_DRV_SA1100) += rtc-sa1100.o
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obj-$(CONFIG_RTC_DRV_SC27XX) += rtc-sc27xx.o
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obj-$(CONFIG_RTC_DRV_SC27XX) += rtc-sc27xx.o
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obj-$(CONFIG_RTC_DRV_SD3078) += rtc-sd3078.o
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obj-$(CONFIG_RTC_DRV_SD3078) += rtc-sd3078.o
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obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o
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obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o
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obj-$(CONFIG_RTC_DRV_SIRFSOC) += rtc-sirfsoc.o
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obj-$(CONFIG_RTC_DRV_SNVS) += rtc-snvs.o
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obj-$(CONFIG_RTC_DRV_SNVS) += rtc-snvs.o
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obj-$(CONFIG_RTC_DRV_SPEAR) += rtc-spear.o
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obj-$(CONFIG_RTC_DRV_SPEAR) += rtc-spear.o
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obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
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obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
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@ -1,446 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* SiRFSoC Real Time Clock interface for Linux
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*
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* Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
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*/
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/rtc.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/rtc/sirfsoc_rtciobrg.h>
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#define RTC_CN 0x00
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#define RTC_ALARM0 0x04
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#define RTC_ALARM1 0x18
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#define RTC_STATUS 0x08
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#define RTC_SW_VALUE 0x40
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#define SIRFSOC_RTC_AL1E (1<<6)
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#define SIRFSOC_RTC_AL1 (1<<4)
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#define SIRFSOC_RTC_HZE (1<<3)
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#define SIRFSOC_RTC_AL0E (1<<2)
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#define SIRFSOC_RTC_HZ (1<<1)
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#define SIRFSOC_RTC_AL0 (1<<0)
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#define RTC_DIV 0x0c
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#define RTC_DEEP_CTRL 0x14
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#define RTC_CLOCK_SWITCH 0x1c
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#define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
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/* Refer to RTC DIV switch */
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#define RTC_HZ 16
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/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
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#define RTC_SHIFT 4
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#define INTR_SYSRTC_CN 0x48
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struct sirfsoc_rtc_drv {
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struct rtc_device *rtc;
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u32 rtc_base;
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u32 irq;
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unsigned irq_wake;
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/* Overflow for every 8 years extra time */
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u32 overflow_rtc;
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spinlock_t lock;
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struct regmap *regmap;
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#ifdef CONFIG_PM
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u32 saved_counter;
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u32 saved_overflow_rtc;
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#endif
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};
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static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
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{
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u32 val;
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regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
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return val;
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}
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static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
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u32 offset, u32 val)
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{
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regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
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}
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static int sirfsoc_rtc_read_alarm(struct device *dev,
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struct rtc_wkalrm *alrm)
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{
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unsigned long rtc_alarm, rtc_count;
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struct sirfsoc_rtc_drv *rtcdrv;
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rtcdrv = dev_get_drvdata(dev);
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spin_lock_irq(&rtcdrv->lock);
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rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
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rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
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memset(alrm, 0, sizeof(struct rtc_wkalrm));
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/*
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* assume alarm interval not beyond one round counter overflow_rtc:
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* 0->0xffffffff
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*/
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/* if alarm is in next overflow cycle */
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if (rtc_count > rtc_alarm)
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rtc_time64_to_tm((rtcdrv->overflow_rtc + 1)
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<< (BITS_PER_LONG - RTC_SHIFT)
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| rtc_alarm >> RTC_SHIFT, &alrm->time);
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else
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rtc_time64_to_tm(rtcdrv->overflow_rtc
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<< (BITS_PER_LONG - RTC_SHIFT)
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| rtc_alarm >> RTC_SHIFT, &alrm->time);
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if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
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alrm->enabled = 1;
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spin_unlock_irq(&rtcdrv->lock);
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return 0;
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}
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static int sirfsoc_rtc_set_alarm(struct device *dev,
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struct rtc_wkalrm *alrm)
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{
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unsigned long rtc_status_reg, rtc_alarm;
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struct sirfsoc_rtc_drv *rtcdrv;
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rtcdrv = dev_get_drvdata(dev);
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if (alrm->enabled) {
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rtc_alarm = rtc_tm_to_time64(&alrm->time);
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spin_lock_irq(&rtcdrv->lock);
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rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
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if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
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/*
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* An ongoing alarm in progress - ingore it and not
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* to return EBUSY
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*/
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dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
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}
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sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
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rtc_status_reg &= ~0x07; /* mask out the lower status bits */
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/*
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* This bit RTC_AL sets it as a wake-up source for Sleep Mode
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* Writing 1 into this bit will clear it
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*/
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rtc_status_reg |= SIRFSOC_RTC_AL0;
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/* enable the RTC alarm interrupt */
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rtc_status_reg |= SIRFSOC_RTC_AL0E;
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sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
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spin_unlock_irq(&rtcdrv->lock);
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} else {
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/*
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* if this function was called with enabled=0
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* then it could mean that the application is
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* trying to cancel an ongoing alarm
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*/
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spin_lock_irq(&rtcdrv->lock);
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rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
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if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
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/* clear the RTC status register's alarm bit */
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rtc_status_reg &= ~0x07;
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/* write 1 into SIRFSOC_RTC_AL0 to force a clear */
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rtc_status_reg |= (SIRFSOC_RTC_AL0);
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/* Clear the Alarm enable bit */
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rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
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sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
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rtc_status_reg);
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}
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spin_unlock_irq(&rtcdrv->lock);
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}
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return 0;
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}
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static int sirfsoc_rtc_read_time(struct device *dev,
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struct rtc_time *tm)
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{
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unsigned long tmp_rtc = 0;
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struct sirfsoc_rtc_drv *rtcdrv;
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rtcdrv = dev_get_drvdata(dev);
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/*
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* This patch is taken from WinCE - Need to validate this for
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* correctness. To work around sirfsoc RTC counter double sync logic
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* fail, read several times to make sure get stable value.
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*/
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do {
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tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
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cpu_relax();
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} while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
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rtc_time64_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT)
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| tmp_rtc >> RTC_SHIFT, tm);
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return 0;
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}
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static int sirfsoc_rtc_set_time(struct device *dev,
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struct rtc_time *tm)
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{
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unsigned long rtc_time;
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struct sirfsoc_rtc_drv *rtcdrv;
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rtcdrv = dev_get_drvdata(dev);
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rtc_time = rtc_tm_to_time64(tm);
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rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
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sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
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sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
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return 0;
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}
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static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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unsigned long rtc_status_reg = 0x0;
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struct sirfsoc_rtc_drv *rtcdrv;
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rtcdrv = dev_get_drvdata(dev);
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spin_lock_irq(&rtcdrv->lock);
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rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
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if (enabled)
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rtc_status_reg |= SIRFSOC_RTC_AL0E;
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else
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rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
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sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
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spin_unlock_irq(&rtcdrv->lock);
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return 0;
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}
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static const struct rtc_class_ops sirfsoc_rtc_ops = {
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.read_time = sirfsoc_rtc_read_time,
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.set_time = sirfsoc_rtc_set_time,
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.read_alarm = sirfsoc_rtc_read_alarm,
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.set_alarm = sirfsoc_rtc_set_alarm,
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.alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
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};
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static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
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{
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struct sirfsoc_rtc_drv *rtcdrv = pdata;
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unsigned long rtc_status_reg = 0x0;
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unsigned long events = 0x0;
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spin_lock(&rtcdrv->lock);
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rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
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/* this bit will be set ONLY if an alarm was active
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* and it expired NOW
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* So this is being used as an ASSERT
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*/
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if (rtc_status_reg & SIRFSOC_RTC_AL0) {
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/*
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* clear the RTC status register's alarm bit
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* mask out the lower status bits
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*/
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rtc_status_reg &= ~0x07;
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/* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
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rtc_status_reg |= (SIRFSOC_RTC_AL0);
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/* Clear the Alarm enable bit */
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rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
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}
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sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
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spin_unlock(&rtcdrv->lock);
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/* this should wake up any apps polling/waiting on the read
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* after setting the alarm
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*/
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events |= RTC_IRQF | RTC_AF;
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rtc_update_irq(rtcdrv->rtc, 1, events);
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return IRQ_HANDLED;
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}
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static const struct of_device_id sirfsoc_rtc_of_match[] = {
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{ .compatible = "sirf,prima2-sysrtc"},
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{},
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};
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static const struct regmap_config sysrtc_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.fast_io = true,
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};
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MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
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static int sirfsoc_rtc_probe(struct platform_device *pdev)
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{
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int err;
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unsigned long rtc_div;
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struct sirfsoc_rtc_drv *rtcdrv;
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struct device_node *np = pdev->dev.of_node;
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rtcdrv = devm_kzalloc(&pdev->dev,
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sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
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if (rtcdrv == NULL)
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return -ENOMEM;
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spin_lock_init(&rtcdrv->lock);
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err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
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if (err) {
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dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
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return err;
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}
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platform_set_drvdata(pdev, rtcdrv);
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/* Register rtc alarm as a wakeup source */
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device_init_wakeup(&pdev->dev, 1);
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rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
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&sysrtc_regmap_config);
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if (IS_ERR(rtcdrv->regmap)) {
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err = PTR_ERR(rtcdrv->regmap);
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dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
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err);
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|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set SYS_RTC counter in RTC_HZ HZ Units
|
|
||||||
* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
|
|
||||||
* If 16HZ, therefore RTC_DIV = 1023;
|
|
||||||
*/
|
|
||||||
rtc_div = ((32768 / RTC_HZ) / 2) - 1;
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
|
|
||||||
|
|
||||||
/* 0x3 -> RTC_CLK */
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
|
|
||||||
|
|
||||||
/* reset SYS RTC ALARM0 */
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
|
|
||||||
|
|
||||||
/* reset SYS RTC ALARM1 */
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
|
|
||||||
|
|
||||||
/* Restore RTC Overflow From Register After Command Reboot */
|
|
||||||
rtcdrv->overflow_rtc =
|
|
||||||
sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
|
|
||||||
|
|
||||||
rtcdrv->rtc = devm_rtc_allocate_device(&pdev->dev);
|
|
||||||
if (IS_ERR(rtcdrv->rtc))
|
|
||||||
return PTR_ERR(rtcdrv->rtc);
|
|
||||||
|
|
||||||
rtcdrv->rtc->ops = &sirfsoc_rtc_ops;
|
|
||||||
rtcdrv->rtc->range_max = (1ULL << 60) - 1;
|
|
||||||
|
|
||||||
rtcdrv->irq = platform_get_irq(pdev, 0);
|
|
||||||
err = devm_request_irq(&pdev->dev, rtcdrv->irq, sirfsoc_rtc_irq_handler,
|
|
||||||
IRQF_SHARED, pdev->name, rtcdrv);
|
|
||||||
if (err) {
|
|
||||||
dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
return devm_rtc_register_device(rtcdrv->rtc);
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_PM_SLEEP
|
|
||||||
static int sirfsoc_rtc_suspend(struct device *dev)
|
|
||||||
{
|
|
||||||
struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
|
|
||||||
rtcdrv->overflow_rtc =
|
|
||||||
sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
|
|
||||||
|
|
||||||
rtcdrv->saved_counter =
|
|
||||||
sirfsoc_rtc_readl(rtcdrv, RTC_CN);
|
|
||||||
rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
|
|
||||||
if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
|
|
||||||
rtcdrv->irq_wake = 1;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sirfsoc_rtc_resume(struct device *dev)
|
|
||||||
{
|
|
||||||
u32 tmp;
|
|
||||||
struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* if resume from snapshot and the rtc power is lost,
|
|
||||||
* restroe the rtc settings
|
|
||||||
*/
|
|
||||||
if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
|
|
||||||
u32 rtc_div;
|
|
||||||
/* 0x3 -> RTC_CLK */
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
|
|
||||||
/*
|
|
||||||
* Set SYS_RTC counter in RTC_HZ HZ Units
|
|
||||||
* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
|
|
||||||
* If 16HZ, therefore RTC_DIV = 1023;
|
|
||||||
*/
|
|
||||||
rtc_div = ((32768 / RTC_HZ) / 2) - 1;
|
|
||||||
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
|
|
||||||
|
|
||||||
/* reset SYS RTC ALARM0 */
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
|
|
||||||
|
|
||||||
/* reset SYS RTC ALARM1 */
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
|
|
||||||
}
|
|
||||||
rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* if current counter is small than previous,
|
|
||||||
* it means overflow in sleep
|
|
||||||
*/
|
|
||||||
tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
|
|
||||||
if (tmp <= rtcdrv->saved_counter)
|
|
||||||
rtcdrv->overflow_rtc++;
|
|
||||||
/*
|
|
||||||
*PWRC Value Be Changed When Suspend, Restore Overflow
|
|
||||||
* In Memory To Register
|
|
||||||
*/
|
|
||||||
sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
|
|
||||||
|
|
||||||
if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
|
|
||||||
disable_irq_wake(rtcdrv->irq);
|
|
||||||
rtcdrv->irq_wake = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
|
|
||||||
sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
|
|
||||||
|
|
||||||
static struct platform_driver sirfsoc_rtc_driver = {
|
|
||||||
.driver = {
|
|
||||||
.name = "sirfsoc-rtc",
|
|
||||||
.pm = &sirfsoc_rtc_pm_ops,
|
|
||||||
.of_match_table = sirfsoc_rtc_of_match,
|
|
||||||
},
|
|
||||||
.probe = sirfsoc_rtc_probe,
|
|
||||||
};
|
|
||||||
module_platform_driver(sirfsoc_rtc_driver);
|
|
||||||
|
|
||||||
MODULE_DESCRIPTION("SiRF SoC rtc driver");
|
|
||||||
MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
|
|
||||||
MODULE_LICENSE("GPL v2");
|
|
||||||
MODULE_ALIAS("platform:sirfsoc-rtc");
|
|
||||||
@ -1,21 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
||||||
/*
|
|
||||||
* RTC I/O Bridge interfaces for CSR SiRFprimaII
|
|
||||||
* ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
|
|
||||||
*
|
|
||||||
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
|
||||||
*/
|
|
||||||
#ifndef _SIRFSOC_RTC_IOBRG_H_
|
|
||||||
#define _SIRFSOC_RTC_IOBRG_H_
|
|
||||||
|
|
||||||
struct regmap_config;
|
|
||||||
|
|
||||||
extern void sirfsoc_rtc_iobrg_besyncing(void);
|
|
||||||
|
|
||||||
extern u32 sirfsoc_rtc_iobrg_readl(u32 addr);
|
|
||||||
|
|
||||||
extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr);
|
|
||||||
struct regmap *devm_regmap_init_iobg(struct device *dev,
|
|
||||||
const struct regmap_config *config);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
Loading…
Reference in New Issue
Block a user