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net: hns3: remove two duplicated register macros in hclgevf_main.h
HCLGEVF_CMDQ_INTR_SRC_REG and HCLGEVF_CMDQ_INTR_STS_REG are same as HCLGEVF_VECTOR0_CMDQ_SRC_REG and HCLGEVF_VECTOR0_CMDQ_STAT_REG, replace the former with the latter, and rename macro HCLGEVF_VECTOR0_CMDQ_STAT_REG since 'stat' is not abbreviation of 'state'. Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -46,7 +46,7 @@ static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
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HCLGEVF_CMDQ_RX_TAIL_REG,
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HCLGEVF_CMDQ_RX_HEAD_REG,
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HCLGEVF_VECTOR0_CMDQ_SRC_REG,
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HCLGEVF_CMDQ_INTR_STS_REG,
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HCLGEVF_VECTOR0_CMDQ_STATE_REG,
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HCLGEVF_CMDQ_INTR_EN_REG,
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HCLGEVF_CMDQ_INTR_GEN_REG};
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@ -1826,7 +1826,7 @@ static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
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dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
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hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
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dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
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hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG));
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hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
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dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
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hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG));
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dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
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@ -2250,7 +2250,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
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/* fetch the events from their corresponding regs */
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cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
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HCLGEVF_VECTOR0_CMDQ_STAT_REG);
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HCLGEVF_VECTOR0_CMDQ_STATE_REG);
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if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
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rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
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@ -42,8 +42,6 @@
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#define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020
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#define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024
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#define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028
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#define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100
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#define HCLGEVF_CMDQ_INTR_STS_REG 0x27104
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#define HCLGEVF_CMDQ_INTR_EN_REG 0x27108
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#define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C
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@ -88,7 +86,7 @@
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/* Vector0 interrupt CMDQ event source register(RW) */
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#define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100
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/* Vector0 interrupt CMDQ event status register(RO) */
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#define HCLGEVF_VECTOR0_CMDQ_STAT_REG 0x27104
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#define HCLGEVF_VECTOR0_CMDQ_STATE_REG 0x27104
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/* CMDQ register bits for RX event(=MBX event) */
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#define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1
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/* RST register bits for RESET event */
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