diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 7277e58b01f1..5b7f2b67791e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4554,13 +4554,18 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, static int __set_power_wells(struct i915_power_domains *power_domains, const struct i915_power_well_desc *power_well_descs, - int power_well_count) + int power_well_descs_sz, u64 skip_mask) { struct drm_i915_private *i915 = container_of(power_domains, struct drm_i915_private, power_domains); u64 power_well_ids = 0; - int i; + int power_well_count = 0; + int i, plt_idx = 0; + + for (i = 0; i < power_well_descs_sz; i++) + if (!(BIT_ULL(power_well_descs[i].id) & skip_mask)) + power_well_count++; power_domains->power_well_count = power_well_count; power_domains->power_wells = @@ -4570,10 +4575,14 @@ __set_power_wells(struct i915_power_domains *power_domains, if (!power_domains->power_wells) return -ENOMEM; - for (i = 0; i < power_well_count; i++) { + for (i = 0; i < power_well_descs_sz; i++) { enum i915_power_well_id id = power_well_descs[i].id; - power_domains->power_wells[i].desc = &power_well_descs[i]; + if (BIT_ULL(id) & skip_mask) + continue; + + power_domains->power_wells[plt_idx++].desc = + &power_well_descs[i]; if (id == DISP_PW_ID_NONE) continue; @@ -4586,9 +4595,12 @@ __set_power_wells(struct i915_power_domains *power_domains, return 0; } -#define set_power_wells(power_domains, __power_well_descs) \ +#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \ __set_power_wells(power_domains, __power_well_descs, \ - ARRAY_SIZE(__power_well_descs)) + ARRAY_SIZE(__power_well_descs), skip_mask) + +#define set_power_wells(power_domains, __power_well_descs) \ + set_power_wells_mask(power_domains, __power_well_descs, 0) /** * intel_power_domains_init - initializes the power domain structures