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rtl8xxxu: Implement init_statistics for 8723bu
Vendor driver implements this for 8723b and 8821 series Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -5981,6 +5981,29 @@ static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
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rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
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}
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static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
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{
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u32 val32;
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/* Time duration for NHM unit: 4us, 0x2710=40ms */
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rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
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rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
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rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
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rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
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/* TH8 */
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val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
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val32 |= 0xff;
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rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
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/* Enable CCK */
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val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
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val32 |= BIT(8) | BIT(9) | BIT(10);
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rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
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/* Max power amongst all RX antennas */
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val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
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val32 |= BIT(7);
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rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
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}
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static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
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{
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struct rtl8xxxu_priv *priv = hw->priv;
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@ -6371,6 +6394,9 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
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rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
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if (priv->fops->init_statistics)
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priv->fops->init_statistics(priv);
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rtl8723a_phy_lc_calibrate(priv);
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priv->fops->phy_iq_calibrate(priv);
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@ -8021,6 +8047,7 @@ static struct rtl8xxxu_fileops rtl8723bu_fops = {
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.init_bt = rtl8723bu_init_bt,
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.parse_rx_desc = rtl8723bu_parse_rx_desc,
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.init_aggregation = rtl8723bu_init_aggregation,
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.init_statistics = rtl8723bu_init_statistics,
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.writeN_block_size = 1024,
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.mbox_ext_reg = REG_HMBOX_EXT0_8723B,
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.mbox_ext_width = 4,
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@ -1134,6 +1134,7 @@ struct rtl8xxxu_fileops {
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int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb,
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struct ieee80211_rx_status *rx_status);
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void (*init_aggregation) (struct rtl8xxxu_priv *priv);
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void (*init_statistics) (struct rtl8xxxu_priv *priv);
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int writeN_block_size;
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u16 mbox_ext_reg;
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char mbox_ext_width;
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@ -833,6 +833,11 @@
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#define REG_FPGA0_ANALOG3 0x0888
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#define REG_FPGA0_ANALOG4 0x088c
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#define REG_NHM_TH9_TH10_8723B 0x0890
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#define REG_NHM_TIMER_8723B 0x0894
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#define REG_NHM_TH3_TO_TH0_8723B 0x0898
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#define REG_NHM_TH7_TO_TH4_8723B 0x089c
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#define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */
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#define REG_FPGA0_XB_LSSI_READBACK 0x08a4
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#define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */
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@ -869,6 +874,8 @@
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#define REG_OFDM0_TR_MUX_PAR 0x0c08
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#define REG_OFDM0_FA_RSTC 0x0c0c
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#define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14
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#define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c
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