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https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-26 21:54:11 +08:00
soc: devicetree updates for 6.13
This release adds the devicetree files for an impressive number of new
SoC variants, though as expected these are all related to others we
already support:
- The microchip sam9x7 devicetree is now added, after the device driver
and platform code has already made it in. This is likely the last ARMv5
(!) platform to ever get added, updating the 20+ year old at91/sam9
platform wtih DDR3 memory and gigabit ethernet.
- On the Apple platform, there are now devicetree files for a number of
A-series SoCs in addition to the M-series ones, these are used
primarily in phones and tablets, but are closely related to the
already supported chips.
- Samsung Exynos 8895 and Exynos 990 are more phone SoCs used in older
Samsung Galaxy phones.
- Qualcomm Snapdragon 778G (SM7325) is another phone SoC, closely related
to the Snapdragon 7c+ Gen 3 (SC7280) used in low-end laptops.
- Rockchip RK3528 and RK3576 are new variants of their TV box and Tablet
chips, still using the older ARMv8.0 cores from RK3328/RK3399 but
with a newer process and other improvements from the RK35xx (otherwise
ARMv8.2) chips. RK3566T and RK3399-S are also added, these are just
lower-cost versions of their normal counterparts.
- TI J742S2 is a feature-reduced version of the J784s4
industrial/automotive SoC, with fewer CPU cores.
- Sophgo SG2002 is an embedded SoC with one RISC-V (C906) and one ARM
(Cortex-A53) core, at this point support is only added for running
on the RISC-V side on the LicheeRV Nano board.
A total of 92 new .dts files describing individual machines is added,
which must be a new record. The majority of these is for the newly added
chips above, notably all the Apple phones and tablets. The other new
machines include nine industrial/embedded boards with NXP i.MX6 or i.MX8
SoCs, eight for Rockchips RK35XX and one or two each for Rockchips RV1109,
RK3308, Allwinner A33, Tegra 234, Qualcomm qcs9100/sc8280xp/x1e80100,
TI AM625 and Starfive JH7110.
As usual there are also many newlyad added features in existing boards
as well as cleanups and minor bugfixes.
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Merge tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"This release adds the devicetree files for an impressive number of new
SoC variants, though as expected these are all related to others we
already support:
- The microchip sam9x7 devicetree is now added, after the device
driver and platform code has already made it in. This is likely the
last ARMv5 (!) platform to ever get added, updating the 20+ year
old at91/sam9 platform with DDR3 memory and gigabit ethernet.
- On the Apple platform, there are now devicetree files for a number
of A-series SoCs in addition to the M-series ones, these are used
primarily in phones and tablets, but are closely related to the
already supported chips.
- Samsung Exynos 8895 and Exynos 990 are more phone SoCs used in
older Samsung Galaxy phones.
- Qualcomm Snapdragon 778G (SM7325) is another phone SoC, closely
related to the Snapdragon 7c+ Gen 3 (SC7280) used in low-end
laptops.
- Rockchip RK3528 and RK3576 are new variants of their TV box and
Tablet chips, still using the older ARMv8.0 cores from
RK3328/RK3399 but with a newer process and other improvements from
the RK35xx (otherwise ARMv8.2) chips. RK3566T and RK3399-S are also
added, these are just lower-cost versions of their normal
counterparts.
- TI J742S2 is a feature-reduced version of the J784s4
industrial/automotive SoC, with fewer CPU cores.
- Sophgo SG2002 is an embedded SoC with one RISC-V (C906) and one ARM
(Cortex-A53) core, at this point support is only added for running
on the RISC-V side on the LicheeRV Nano board.
A total of 92 new .dts files describing individual machines is added,
which must be a new record. The majority of these is for the newly
added chips above, notably all the Apple phones and tablets. The other
new machines include nine industrial/embedded boards with NXP i.MX6 or
i.MX8 SoCs, eight for Rockchips RK35XX and one or two each for
Rockchips RV1109, RK3308, Allwinner A33, Tegra 234, Qualcomm
qcs9100/sc8280xp/x1e80100, TI AM625 and Starfive JH7110.
As usual there are also many newly added features in existing boards
as well as cleanups and minor bugfixes"
* tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (718 commits)
arm64: dts: apm: Remove unused and undocumented "bus_num" property
arm: dts: spear13xx: Remove unused and undocumented "pl022,slave-tx-disable" property
arm64: dts: amd: Remove unused and undocumented "amd,zlib-support" property
arm64: dts: lg131x: Update spi clock properties
arm64: dts: seattle: Update spi clock properties
arm64: dts: rockchip: use less broad pinctrl for pcie3x1 on Radxa E25
arm64: dts: rockchip: add Radxa ROCK 5C
dt-bindings: arm: rockchip: add Radxa ROCK 5C
arm64: dts: rockchip: orangepi-5-plus: Enable GPU
arm64: dts: rockchip: enable USB3 on NanoPC-T6
arm64: dts: rockchip: adapt regulator nodenames to preferred form
arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi GenBook
arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi 4B
arm64: dts: rockchip: Enable HDMI0 for rk3588 Cool Pi CM5 EVB
arm64: dts: rockchip: Enable HDMI on NanoPi R6C/R6S
arm64: dts: rockchip: Enable GPU on NanoPi R6C/R6S
arm64: dts: rockchip: Enable HDMI on Hardkernel ODROID-M2
arm64: dts: rockchip: Remove non-removable flag from sdmmc on rk3576-sige5
arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer
...
This commit is contained in:
Linus Torvalds
commit
9c39d5ab45
@ -12,7 +12,58 @@ maintainers:
|
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description: |
|
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ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
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|
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This currently includes devices based on the "M1" SoC:
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This currently includes devices based on the "A7" SoC:
|
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|
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- iPhone 5s
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- iPad Air (1)
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- iPad mini 2
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- iPad mini 3
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Devices based on the "A8" SoC:
|
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|
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- iPhone 6
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- iPhone 6 Plus
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- iPad mini 4
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- iPod touch 6
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- Apple TV HD
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|
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Device based on the "A8X" SoC:
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|
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- iPad Air 2
|
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|
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Devices based on the "A9" SoC:
|
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|
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- iPhone 6s
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- iPhone 6s Plus
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- iPhone SE (2016)
|
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- iPad 5
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|
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Devices based on the "A9X" SoC:
|
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|
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- iPad Pro (9.7-inch)
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- iPad Pro (12.9-inch)
|
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|
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Devices based on the "A10" SoC:
|
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|
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- iPhone 7
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- iPhone 7 Plus
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- iPod touch 7
|
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- iPad 6
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- iPad 7
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|
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Devices based on the "A10X" SoC:
|
||||
|
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- Apple TV 4K (1st generation)
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- iPad Pro (2nd Generation) (10.5 Inch)
|
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- iPad Pro (2nd Generation) (12.9 Inch)
|
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|
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Devices based on the "A11" SoC:
|
||||
|
||||
- iPhone 8
|
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- iPhone 8 Plus
|
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- iPhone X
|
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|
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Devices based on the "M1" SoC:
|
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|
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- Mac mini (M1, 2020)
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- MacBook Pro (13-inch, M1, 2020)
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@ -65,6 +116,113 @@ properties:
|
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const: "/"
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compatible:
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oneOf:
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- description: Apple A7 SoC based platforms
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items:
|
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- enum:
|
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- apple,j71 # iPad Air (Wi-Fi)
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- apple,j72 # iPad Air (Cellular)
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- apple,j73 # iPad Air (Cellular, China)
|
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- apple,j85 # iPad mini 2 (Wi-Fi)
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- apple,j85m # iPad mini 3 (Wi-Fi)
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- apple,j86 # iPad mini 2 (Cellular)
|
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- apple,j86m # iPad mini 3 (Cellular)
|
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- apple,j87 # iPad mini 2 (Cellular, China)
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- apple,j87m # iPad mini 3 (Cellular, China)
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- apple,n51 # iPhone 5s (GSM)
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- apple,n53 # iPhone 5s (LTE)
|
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- const: apple,s5l8960x
|
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- const: apple,arm-platform
|
||||
|
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- description: Apple A8 SoC based platforms
|
||||
items:
|
||||
- enum:
|
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- apple,j42d # Apple TV HD
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- apple,j96 # iPad mini 4 (Wi-Fi)
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- apple,j97 # iPad mini 4 (Cellular)
|
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- apple,n56 # iPhone 6 Plus
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- apple,n61 # iPhone 6
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- apple,n102 # iPod touch 6
|
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- const: apple,t7000
|
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- const: apple,arm-platform
|
||||
|
||||
- description: Apple A8X SoC based platforms
|
||||
items:
|
||||
- enum:
|
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- apple,j81 # iPad Air 2 (Wi-Fi)
|
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- apple,j82 # iPad Air 2 (Cellular)
|
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- const: apple,t7001
|
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- const: apple,arm-platform
|
||||
|
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- description: Apple Samsung A9 SoC based platforms
|
||||
items:
|
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- enum:
|
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- apple,j71s # iPad 5 (Wi-Fi) (S8000)
|
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- apple,j72s # iPad 5 (Cellular) (S8000)
|
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- apple,n66 # iPhone 6s Plus (S8000)
|
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- apple,n69u # iPhone SE (S8000)
|
||||
- apple,n71 # iPhone 6S (S8000)
|
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- const: apple,s8000
|
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- const: apple,arm-platform
|
||||
|
||||
- description: Apple TSMC A9 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j71t # iPad 5 (Wi-Fi) (S8003)
|
||||
- apple,j72t # iPad 5 (Cellular) (S8003)
|
||||
- apple,n66m # iPhone 6s Plus (S8003)
|
||||
- apple,n69 # iPhone SE (S8003)
|
||||
- apple,n71m # iPhone 6S (S8003)
|
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- const: apple,s8003
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple A9X SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j127 # iPad Pro (9.7-inch) (Wi-Fi)
|
||||
- apple,j128 # iPad Pro (9.7-inch) (Cellular)
|
||||
- apple,j98a # iPad Pro (12.9-inch) (Wi-Fi)
|
||||
- apple,j99a # iPad Pro (12.9-inch) (Cellular)
|
||||
- const: apple,s8001
|
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- const: apple,arm-platform
|
||||
|
||||
- description: Apple A10 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,d10 # iPhone 7 (Qualcomm)
|
||||
- apple,d11 # iPhone 7 (Intel)
|
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- apple,d101 # iPhone 7 Plus (Qualcomm)
|
||||
- apple,d111 # iPhone 7 Plus (Intel)
|
||||
- apple,j71b # iPad 6 (Wi-Fi)
|
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- apple,j72b # iPad 6 (Cellular)
|
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- apple,j171 # iPad 7 (Wi-Fi)
|
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- apple,j172 # iPad 7 (Cellular)
|
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- apple,n112 # iPod touch 7
|
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- const: apple,t8010
|
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- const: apple,arm-platform
|
||||
|
||||
- description: Apple A10X SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j105a # Apple TV 4K (1st Generation)
|
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- apple,j120 # iPad Pro 2 (12.9-inch) (Wi-Fi)
|
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- apple,j121 # iPad Pro 2 (12.9-inch) (Cellular)
|
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- apple,j207 # iPad Pro 2 (10.5-inch) (Wi-Fi)
|
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- apple,j208 # iPad Pro 2 (10.5-inch) (Cellular)
|
||||
- const: apple,t8011
|
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- const: apple,arm-platform
|
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|
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- description: Apple A11 SoC based platforms
|
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items:
|
||||
- enum:
|
||||
- apple,d20 # iPhone 8 (Global)
|
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- apple,d21 # iPhone 8 Plus (Global)
|
||||
- apple,d22 # iPhone X (Global)
|
||||
- apple,d201 # iPhone 8 (GSM)
|
||||
- apple,d211 # iPhone 8 Plus (GSM)
|
||||
- apple,d221 # iPhone X (GSM)
|
||||
- const: apple,t8015
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple M1 SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
|
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@ -106,6 +106,12 @@ properties:
|
||||
- const: microchip,sam9x60
|
||||
- const: atmel,at91sam9
|
||||
|
||||
- description: Microchip SAM9X7 Evaluation Boards
|
||||
items:
|
||||
- const: microchip,sam9x75-curiosity
|
||||
- const: microchip,sam9x7
|
||||
- const: atmel,at91sam9
|
||||
|
||||
- description: Nattis v2 board with Natte v2 power board
|
||||
items:
|
||||
- const: axentia,nattis-2
|
||||
|
||||
@ -87,8 +87,14 @@ properties:
|
||||
enum:
|
||||
- apple,avalanche
|
||||
- apple,blizzard
|
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- apple,icestorm
|
||||
- apple,cyclone
|
||||
- apple,firestorm
|
||||
- apple,hurricane-zephyr
|
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- apple,icestorm
|
||||
- apple,mistral
|
||||
- apple,monsoon
|
||||
- apple,twister
|
||||
- apple,typhoon
|
||||
- arm,arm710t
|
||||
- arm,arm720t
|
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- arm,arm740t
|
||||
@ -202,10 +208,14 @@ properties:
|
||||
- qcom,kryo560
|
||||
- qcom,kryo570
|
||||
- qcom,kryo660
|
||||
- qcom,kryo670
|
||||
- qcom,kryo685
|
||||
- qcom,kryo780
|
||||
- qcom,oryon
|
||||
- qcom,scorpion
|
||||
- samsung,mongoose-m2
|
||||
- samsung,mongoose-m3
|
||||
- samsung,mongoose-m5
|
||||
|
||||
enable-method:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
|
||||
@ -379,7 +379,9 @@ properties:
|
||||
|
||||
- description: i.MX6Q PHYTEC phyFLEX-i.MX6
|
||||
items:
|
||||
- const: phytec,imx6q-pbab01 # PHYTEC phyFLEX carrier board
|
||||
- enum:
|
||||
- comvetia,imx6q-lxr # Comvetia LXR board
|
||||
- phytec,imx6q-pbab01 # PHYTEC phyFLEX carrier board
|
||||
- const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
|
||||
- const: fsl,imx6q
|
||||
|
||||
@ -523,9 +525,11 @@ properties:
|
||||
- const: dfi,fs700e-m60
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6DL DHCOM PicoITX Board
|
||||
- description: i.MX6DL DHCOM based Boards
|
||||
items:
|
||||
- const: dh,imx6dl-dhcom-picoitx
|
||||
- enum:
|
||||
- dh,imx6dl-dhcom-pdk2 # i.MX6DL DHCOM SoM on PDK2 board
|
||||
- dh,imx6dl-dhcom-picoitx # i.MX6DL DHCOM SoM on PicoITX board
|
||||
- const: dh,imx6dl-dhcom-som
|
||||
- const: fsl,imx6dl
|
||||
|
||||
@ -620,6 +624,14 @@ properties:
|
||||
- kobo,librah2o
|
||||
- const: fsl,imx6sll
|
||||
|
||||
- description: i.MX6SLL Kobo Clara 2e Rev. A/B
|
||||
items:
|
||||
- enum:
|
||||
- kobo,clara2e-a
|
||||
- kobo,clara2e-b
|
||||
- const: kobo,clara2e
|
||||
- const: fsl,imx6sll
|
||||
|
||||
- description: i.MX6SX based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -995,6 +1007,7 @@ properties:
|
||||
- menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board
|
||||
- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
|
||||
- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
|
||||
- toradex,verdin-imx8mm-nonwifi-ivy # Verdin iMX8M Mini Module on Ivy
|
||||
- toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow
|
||||
- toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia
|
||||
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
|
||||
@ -1006,6 +1019,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-imx8mm-wifi-ivy # Verdin iMX8M Mini Wi-Fi / BT Module on Ivy
|
||||
- toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
|
||||
@ -1082,12 +1096,14 @@ properties:
|
||||
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
|
||||
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
|
||||
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
|
||||
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
|
||||
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
|
||||
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
|
||||
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
|
||||
- ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modules
|
||||
@ -1097,11 +1113,19 @@ properties:
|
||||
- const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Boundary Device Nitrogen8MP Universal SMARC Carrier Board
|
||||
items:
|
||||
- const: boundary,imx8mp-nitrogen-smarc-universal-board
|
||||
- const: boundary,imx8mp-nitrogen-smarc-som
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MP DHCOM based Boards
|
||||
items:
|
||||
- enum:
|
||||
- dh,imx8mp-dhcom-drc02 # i.MX8MP DHCOM SoM on DRC02 board
|
||||
- dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
|
||||
- dh,imx8mp-dhcom-pdk3 # i.MX8MP DHCOM SoM on PDK3 board
|
||||
- dh,imx8mp-dhcom-picoitx # i.MX8MP DHCOM SoM on PicoITX board
|
||||
- const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
@ -1112,6 +1136,19 @@ properties:
|
||||
- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Kontron i.MX8MP OSM-S SoM based Boards
|
||||
items:
|
||||
- const: kontron,imx8mp-bl-osm-s # Kontron BL i.MX8MP OSM-S Board
|
||||
- const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Kontron i.MX8MP SMARC based Boards
|
||||
items:
|
||||
- const: kontron,imx8mp-smarc-eval-carrier # Kontron i.MX8MP SMARC Eval Carrier
|
||||
- const: kontron,imx8mp-smarc # Kontron i.MX8MP SMARC Module
|
||||
- const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: PHYTEC phyCORE-i.MX8MP SoM based boards
|
||||
items:
|
||||
- const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK
|
||||
@ -1137,6 +1174,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
|
||||
- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
|
||||
- toradex,verdin-imx8mp-nonwifi-ivy # Verdin iMX8M Plus Module on Ivy
|
||||
- toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow
|
||||
- toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia
|
||||
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
|
||||
@ -1148,6 +1186,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-imx8mp-wifi-ivy # Verdin iMX8M Plus Wi-Fi / BT Module on Ivy
|
||||
- toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
|
||||
|
||||
@ -93,6 +93,34 @@ properties:
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Output port node. This port connects the MMSYS/VDOSYS output to
|
||||
the first component of one display pipeline, for example one of
|
||||
the available OVL or RDMA blocks.
|
||||
Some MediaTek SoCs support multiple display outputs per MMSYS.
|
||||
properties:
|
||||
endpoint@0:
|
||||
$ref: /schemas/graph.yaml#/properties/endpoint
|
||||
description: Output to the primary display pipeline
|
||||
|
||||
endpoint@1:
|
||||
$ref: /schemas/graph.yaml#/properties/endpoint
|
||||
description: Output to the secondary display pipeline
|
||||
|
||||
endpoint@2:
|
||||
$ref: /schemas/graph.yaml#/properties/endpoint
|
||||
description: Output to the tertiary display pipeline
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- endpoint@0
|
||||
- required:
|
||||
- endpoint@1
|
||||
- required:
|
||||
- endpoint@2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -45,6 +45,7 @@ description: |
|
||||
qcs8550
|
||||
qcm2290
|
||||
qcm6490
|
||||
qcs9100
|
||||
qdu1000
|
||||
qrb2210
|
||||
qrb4210
|
||||
@ -76,6 +77,7 @@ description: |
|
||||
sm6375
|
||||
sm7125
|
||||
sm7225
|
||||
sm7325
|
||||
sm8150
|
||||
sm8250
|
||||
sm8350
|
||||
@ -821,6 +823,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,thinkpad-x13s
|
||||
- microsoft,arcata
|
||||
- qcom,sc8280xp-crd
|
||||
- qcom,sc8280xp-qrd
|
||||
- const: qcom,sc8280xp
|
||||
@ -912,6 +915,13 @@ properties:
|
||||
- qcom,sa8775p-ride-r3
|
||||
- const: qcom,sa8775p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs9100-ride
|
||||
- qcom,qcs9100-ride-r3
|
||||
- const: qcom,qcs9100
|
||||
- const: qcom,sa8775p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- google,cheza
|
||||
@ -989,6 +999,11 @@ properties:
|
||||
- fairphone,fp4
|
||||
- const: qcom,sm7225
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- nothing,spacewar
|
||||
- const: qcom,sm7325
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- microsoft,surface-duo
|
||||
@ -1058,6 +1073,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- asus,vivobook-s15
|
||||
- dell,xps13-9345
|
||||
- lenovo,yoga-slim7x
|
||||
- microsoft,romulus13
|
||||
- microsoft,romulus15
|
||||
|
||||
@ -49,11 +49,23 @@ properties:
|
||||
- anbernic,rg-arc-s
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: ArmSoM Sige5 board
|
||||
items:
|
||||
- const: armsom,sige5
|
||||
- const: rockchip,rk3576
|
||||
|
||||
- description: ArmSoM Sige7 board
|
||||
items:
|
||||
- const: armsom,sige7
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: ArmSoM LM7 SoM
|
||||
items:
|
||||
- enum:
|
||||
- armsom,w3
|
||||
- const: armsom,lm7
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Asus Tinker board
|
||||
items:
|
||||
- const: asus,rk3288-tinker
|
||||
@ -232,6 +244,11 @@ properties:
|
||||
- friendlyarm,nanopi-r2s-plus
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: FriendlyElec NanoPi R3S
|
||||
items:
|
||||
- const: friendlyarm,nanopi-r3s
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: FriendlyElec NanoPi4 series boards
|
||||
items:
|
||||
- enum:
|
||||
@ -760,6 +777,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- powkiddy,rgb10max3
|
||||
- powkiddy,rgb20sx
|
||||
- powkiddy,rgb30
|
||||
- powkiddy,rk2023
|
||||
- powkiddy,x55
|
||||
@ -789,6 +807,11 @@ properties:
|
||||
- const: radxa,cm3i
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa E20C
|
||||
items:
|
||||
- const: radxa,e20c
|
||||
- const: rockchip,rk3528
|
||||
|
||||
- description: Radxa Rock
|
||||
items:
|
||||
- const: radxa,rock
|
||||
@ -872,6 +895,11 @@ properties:
|
||||
- const: radxa,rock-5b
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Radxa ROCK 5C
|
||||
items:
|
||||
- const: radxa,rock-5c
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Radxa ROCK S0
|
||||
items:
|
||||
- const: radxa,rock-s0
|
||||
@ -884,6 +912,11 @@ properties:
|
||||
- radxa,zero-3w
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Relfor SAIB board
|
||||
items:
|
||||
- const: relfor,saib
|
||||
- const: rockchip,rv1109
|
||||
|
||||
- description: Rikomagic MK808 v1
|
||||
items:
|
||||
- const: rikomagic,mk808
|
||||
@ -978,6 +1011,11 @@ properties:
|
||||
- const: rockchip,rk3588-evb1-v10
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Rockchip RK3588S Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3588s-evb1-v10
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Rockchip RV1108 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rv1108-evb
|
||||
@ -1051,7 +1089,9 @@ properties:
|
||||
|
||||
- description: Xunlong Orange Pi 5
|
||||
items:
|
||||
- const: xunlong,orangepi-5
|
||||
- enum:
|
||||
- xunlong,orangepi-5
|
||||
- xunlong,orangepi-5b
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Zkmagic A95X Z2
|
||||
@ -1069,6 +1109,11 @@ properties:
|
||||
- const: rockchip,rk3568-evb1-v10
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Sinovoip RK3308 Banana Pi P2 Pro
|
||||
items:
|
||||
- const: sinovoip,rk3308-bpi-p2pro
|
||||
- const: rockchip,rk3308
|
||||
|
||||
- description: Sinovoip RK3568 Banana Pi R2 Pro
|
||||
items:
|
||||
- const: sinovoip,rk3568-bpi-r2pro
|
||||
|
||||
@ -224,6 +224,24 @@ properties:
|
||||
- winlink,e850-96 # WinLink E850-96
|
||||
- const: samsung,exynos850
|
||||
|
||||
- description: Exynos8895 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,dreamlte # Samsung Galaxy S8 (SM-G950F)
|
||||
- const: samsung,exynos8895
|
||||
|
||||
- description: Exynos9810 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,starlte # Samsung Galaxy S9 (SM-G960F)
|
||||
- const: samsung,exynos9810
|
||||
|
||||
- description: Exynos990 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,c1s # Samsung Galaxy Note20 5G (SM-N981B)
|
||||
- const: samsung,exynos990
|
||||
|
||||
- description: Exynos Auto v9 based boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -846,6 +846,12 @@ properties:
|
||||
- const: allwinner,sun50i-h64
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: RerVision A33-Vstar (with A33-Core1 SoM)
|
||||
items:
|
||||
- const: rervision,a33-vstar
|
||||
- const: rervision,a33-core1
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: RerVision H3-DVK
|
||||
items:
|
||||
- const: rervision,h3-dvk
|
||||
|
||||
@ -217,6 +217,11 @@ properties:
|
||||
- const: nvidia,p3737-0000+p3701-0000
|
||||
- const: nvidia,p3701-0000
|
||||
- const: nvidia,tegra234
|
||||
- description: Jetson AGX Orin Developer Kit with Industrial Module
|
||||
items:
|
||||
- const: nvidia,p3737-0000+p3701-0008
|
||||
- const: nvidia,p3701-0008
|
||||
- const: nvidia,tegra234
|
||||
- description: NVIDIA IGX Orin Development Kit
|
||||
items:
|
||||
- const: nvidia,p3740-0002+p3701-0008
|
||||
|
||||
@ -56,6 +56,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
|
||||
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
|
||||
- toradex,verdin-am62-nonwifi-ivy # Verdin AM62 Module on Ivy
|
||||
- toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
|
||||
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
|
||||
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
|
||||
@ -67,6 +68,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-am62-wifi-ivy # Verdin AM62 Wi-Fi / BT Module on Ivy
|
||||
- toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
|
||||
@ -144,6 +146,12 @@ properties:
|
||||
- ti,j722s-evm
|
||||
- const: ti,j722s
|
||||
|
||||
- description: K3 J742S2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- ti,j742s2-evm
|
||||
- const: ti,j742s2
|
||||
|
||||
- description: K3 J784s4 SoC
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SA8775P
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SA8775p.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sa8775p-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Camera AHB clock from GCC
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: MMCX power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
clock-controller@ade0000 {
|
||||
compatible = "qcom,sa8775p-camcc";
|
||||
reg = <0x0ade0000 0x20000>;
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
power-domains = <&rpmhpd SA8775P_MMCX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,79 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller on SA8775P
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SA8775P.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sa8775p-dispcc0
|
||||
- qcom,sa8775p-dispcc1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: GCC AHB clock source
|
||||
- description: Board XO source
|
||||
- description: Board XO_AO source
|
||||
- description: Sleep clock source
|
||||
- description: Link clock from DP0 PHY
|
||||
- description: VCO DIV clock from DP0 PHY
|
||||
- description: Link clock from DP1 PHY
|
||||
- description: VCO DIV clock from DP1 PHY
|
||||
- description: Byte clock from DSI0 PHY
|
||||
- description: Pixel clock from DSI0 PHY
|
||||
- description: Byte clock from DSI1 PHY
|
||||
- description: Pixel clock from DSI1 PHY
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: MMCX power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sa8775p-dispcc0";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&dp_phy0 0>,
|
||||
<&dp_phy0 1>,
|
||||
<&dp_phy1 2>,
|
||||
<&dp_phy1 3>,
|
||||
<&dsi_phy0 0>,
|
||||
<&dsi_phy0 1>,
|
||||
<&dsi_phy1 2>,
|
||||
<&dsi_phy1 3>;
|
||||
power-domains = <&rpmhpd SA8775P_MMCX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller on SA8775P
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module provides the clocks, resets and power
|
||||
domains on SA8775P.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sa8775p-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Video AHB clock from GCC
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep Clock source
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: MMCX power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
videocc: clock-controller@abf0000 {
|
||||
compatible = "qcom,sa8775p-videocc";
|
||||
reg = <0x0abf0000 0x10000>;
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
power-domains = <&rpmhpd SA8775P_MMCX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Battery Backup Function (VBATTB)
|
||||
|
||||
description:
|
||||
Renesas VBATTB is an always on powered module (backed by battery) which
|
||||
controls the RTC clock (VBATTCLK), tamper detection logic and a small
|
||||
general usage memory (128B).
|
||||
|
||||
maintainers:
|
||||
- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a08g045-vbattb
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: tamper detector interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: VBATTB module clock
|
||||
- description: RTC input clock (crystal or external clock device)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bclk
|
||||
- const: rtx
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: VBATTB module reset
|
||||
|
||||
quartz-load-femtofarads:
|
||||
description: load capacitance of the on board crystal
|
||||
enum: [ 4000, 7000, 9000, 12500 ]
|
||||
default: 4000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- power-domains
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r9a08g045-cpg.h>
|
||||
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
clock-controller@1005c000 {
|
||||
compatible = "renesas,r9a08g045-vbattb";
|
||||
reg = <0x1005c000 0x1000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
|
||||
clock-names = "bclk", "rtx";
|
||||
assigned-clocks = <&vbattb VBATTB_MUX>;
|
||||
assigned-clock-parents = <&vbattb VBATTB_XC>;
|
||||
#clock-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A08G045_VBAT_BRESETN>;
|
||||
quartz-load-femtofarads = <12500>;
|
||||
};
|
||||
@ -0,0 +1,239 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos8895 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |
|
||||
Exynos8895 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that root tree
|
||||
is an external clock: OSCCLK (26 MHz). This external clock must be defined
|
||||
as a fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynos8895.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos8895-cmu-fsys0
|
||||
- samsung,exynos8895-cmu-fsys1
|
||||
- samsung,exynos8895-cmu-peric0
|
||||
- samsung,exynos8895-cmu-peric1
|
||||
- samsung,exynos8895-cmu-peris
|
||||
- samsung,exynos8895-cmu-top
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-fsys0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS0 BUS clock (from CMU_TOP)
|
||||
- description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
|
||||
- description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
|
||||
- description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
|
||||
- description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: dpgtc
|
||||
- const: mmc
|
||||
- const: ufs
|
||||
- const: usbdrd30
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-fsys1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS1 BUS clock (from CMU_TOP)
|
||||
- description: CMU_FSYS1 PCIE clock (from CMU_TOP)
|
||||
- description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
|
||||
- description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: pcie
|
||||
- const: ufs
|
||||
- const: mmc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-peric0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC0 BUS clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 USI00 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 USI01 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 USI02 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC0 USI03 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: uart
|
||||
- const: usi0
|
||||
- const: usi1
|
||||
- const: usi2
|
||||
- const: usi3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC1 BUS clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 UART_BT clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI04 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI05 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI06 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI07 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI08 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI09 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI10 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI11 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI12 clock (from CMU_TOP)
|
||||
- description: CMU_PERIC1 USI13 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: speedy
|
||||
- const: cam0
|
||||
- const: cam1
|
||||
- const: uart
|
||||
- const: usi4
|
||||
- const: usi5
|
||||
- const: usi6
|
||||
- const: usi7
|
||||
- const: usi8
|
||||
- const: usi9
|
||||
- const: usi10
|
||||
- const: usi11
|
||||
- const: usi12
|
||||
- const: usi13
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-peris
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIS BUS clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos8895-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos8895.h>
|
||||
|
||||
cmu_fsys1: clock-controller@11400000 {
|
||||
compatible = "samsung,exynos8895-cmu-fsys1";
|
||||
reg = <0x11400000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
|
||||
<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
|
||||
<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
|
||||
<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
|
||||
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
|
||||
};
|
||||
|
||||
...
|
||||
@ -99,14 +99,35 @@ allOf:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx8qxp-dsp
|
||||
- fsl,imx8qm-dsp
|
||||
- fsl,imx8qxp-hifi4
|
||||
then:
|
||||
properties:
|
||||
power-domains:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx8qm-dsp
|
||||
- fsl,imx8qm-hifi4
|
||||
then:
|
||||
properties:
|
||||
power-domains:
|
||||
minItems: 4
|
||||
else:
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx8mp-dsp
|
||||
- fsl,imx8mp-hifi4
|
||||
- fsl,imx8ulp-dsp
|
||||
- fsl,imx8ulp-hifi4
|
||||
then:
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
@ -157,10 +178,8 @@ examples:
|
||||
<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
|
||||
<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
|
||||
clock-names = "ipg", "ocram", "core";
|
||||
power-domains = <&pd IMX_SC_R_MU_13A>,
|
||||
<&pd IMX_SC_R_MU_13B>,
|
||||
<&pd IMX_SC_R_DSP>,
|
||||
<&pd IMX_SC_R_DSP_RAM>;
|
||||
power-domains = <&pd IMX_SC_R_MU_13B>,
|
||||
<&pd IMX_SC_R_MU_2A>;
|
||||
mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
|
||||
mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
|
||||
memory-region = <&dsp_reserved>;
|
||||
|
||||
@ -23,6 +23,9 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-chipid
|
||||
- samsung,exynos8895-chipid
|
||||
- samsung,exynos9810-chipid
|
||||
- samsung,exynos990-chipid
|
||||
- samsung,exynosautov9-chipid
|
||||
- samsung,exynosautov920-chipid
|
||||
- const: samsung,exynos850-chipid
|
||||
|
||||
@ -197,7 +197,7 @@ examples:
|
||||
reg = <0 0x596e8000 0 0x88000>;
|
||||
clocks = <&adma_lpcg 0>, <&adma_lpcg 1>, <&adma_lpcg 2>;
|
||||
clock-names = "ipg", "ocram", "core";
|
||||
power-domains = <&pd 0>, <&pd 1>, <&pd 2>, <&pd 3>;
|
||||
power-domains = <&pd 0>, <&pd 1>;
|
||||
mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
|
||||
mboxes = <&mhu_tx 2 0>, //data-transfer protocol with 5 windows, mhu-tx
|
||||
<&mhu_tx 3 0>, //data-transfer protocol with 7 windows, mhu-tx
|
||||
|
||||
@ -15,9 +15,13 @@ properties:
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun20i-d1-usb-phy
|
||||
- allwinner,sun50i-a64-usb-phy
|
||||
oneOf:
|
||||
- enum:
|
||||
- allwinner,sun20i-d1-usb-phy
|
||||
- allwinner,sun50i-a64-usb-phy
|
||||
- items:
|
||||
- const: allwinner,sun50i-a100-usb-phy
|
||||
- const: allwinner,sun20i-d1-usb-phy
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -18,6 +18,11 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apple,s5l8960x-pinctrl
|
||||
- apple,t7000-pinctrl
|
||||
- apple,s8000-pinctrl
|
||||
- apple,t8010-pinctrl
|
||||
- apple,t8015-pinctrl
|
||||
- apple,t8103-pinctrl
|
||||
- apple,t8112-pinctrl
|
||||
- apple,t6000-pinctrl
|
||||
|
||||
@ -30,6 +30,7 @@ properties:
|
||||
- enum:
|
||||
- fsl,imx6qp-gpc
|
||||
- fsl,imx6sl-gpc
|
||||
- fsl,imx6sll-gpc
|
||||
- fsl,imx6sx-gpc
|
||||
- fsl,imx6ul-gpc
|
||||
- const: fsl,imx6q-gpc
|
||||
|
||||
@ -26,6 +26,7 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- deepcomputing,fml13v01
|
||||
- milkv,mars
|
||||
- pine64,star64
|
||||
- starfive,visionfive-2-v1.2a
|
||||
|
||||
@ -36,6 +36,7 @@ properties:
|
||||
- description: Temperature sensor event
|
||||
- description: Brown-out event on either of the support regulators
|
||||
- description: Brown-out event on either the core, gpu or soc regulators
|
||||
minItems: 2
|
||||
|
||||
tempmon:
|
||||
type: object
|
||||
@ -43,7 +44,7 @@ properties:
|
||||
$ref: /schemas/thermal/imx-thermal.yaml
|
||||
|
||||
patternProperties:
|
||||
"regulator-((1p1)|(2p5)|(3p0)|(vddcore)|(vddpu)|(vddsoc))$":
|
||||
"regulator-((1p1)|(2p5)|(3p0)|(vdd1p0d)|(vdd1p2)|(vddcore)|(vddpcie)|(vddpu)|(vddsoc))$":
|
||||
type: object
|
||||
unevaluatedProperties: false
|
||||
$ref: /schemas/regulator/anatop-regulator.yaml
|
||||
@ -52,6 +53,23 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx7d-anatop
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -15,13 +15,19 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- atmel,at91rm9200-tcb
|
||||
- atmel,at91sam9x5-tcb
|
||||
- atmel,sama5d2-tcb
|
||||
- const: simple-mfd
|
||||
- const: syscon
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,at91rm9200-tcb
|
||||
- atmel,at91sam9x5-tcb
|
||||
- atmel,sama5d2-tcb
|
||||
- const: simple-mfd
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: microchip,sam9x7-tcb
|
||||
- const: atmel,sama5d2-tcb
|
||||
- const: simple-mfd
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -33,9 +33,11 @@ properties:
|
||||
- rockchip,rk3576-usb-grf
|
||||
- rockchip,rk3576-usbdpphy-grf
|
||||
- rockchip,rk3576-vo0-grf
|
||||
- rockchip,rk3576-vo1-grf
|
||||
- rockchip,rk3576-vop-grf
|
||||
- rockchip,rk3588-bigcore0-grf
|
||||
- rockchip,rk3588-bigcore1-grf
|
||||
- rockchip,rk3588-dcphy-grf
|
||||
- rockchip,rk3588-hdptxphy-grf
|
||||
- rockchip,rk3588-ioc
|
||||
- rockchip,rk3588-php-grf
|
||||
@ -80,6 +82,7 @@ properties:
|
||||
- rockchip,rk3568-pmugrf
|
||||
- rockchip,rk3576-ioc-grf
|
||||
- rockchip,rk3576-pmu0-grf
|
||||
- rockchip,rk3576-usb2phy-grf
|
||||
- rockchip,rk3588-usb2phy-grf
|
||||
- rockchip,rv1108-grf
|
||||
- rockchip,rv1108-pmugrf
|
||||
@ -233,6 +236,7 @@ allOf:
|
||||
- rockchip,rk3308-usb2phy-grf
|
||||
- rockchip,rk3328-usb2phy-grf
|
||||
- rockchip,rk3399-grf
|
||||
- rockchip,rk3576-usb2phy-grf
|
||||
- rockchip,rk3588-usb2phy-grf
|
||||
- rockchip,rv1108-grf
|
||||
|
||||
@ -283,6 +287,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,rk3576-vo1-grf
|
||||
- rockchip,rk3588-vo-grf
|
||||
- rockchip,rk3588-vo0-grf
|
||||
- rockchip,rk3588-vo1-grf
|
||||
|
||||
@ -53,6 +53,8 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-pmu
|
||||
- samsung,exynos8895-pmu
|
||||
- samsung,exynos9810-pmu
|
||||
- samsung,exynosautov9-pmu
|
||||
- samsung,exynosautov920-pmu
|
||||
- tesla,fsd-pmu
|
||||
|
||||
@ -33,6 +33,7 @@ properties:
|
||||
- samsung,exynos5420-mct
|
||||
- samsung,exynos5433-mct
|
||||
- samsung,exynos850-mct
|
||||
- samsung,exynos8895-mct
|
||||
- tesla,fsd-mct
|
||||
- const: samsung,exynos4210-mct
|
||||
|
||||
@ -133,6 +134,7 @@ allOf:
|
||||
- samsung,exynos5420-mct
|
||||
- samsung,exynos5433-mct
|
||||
- samsung,exynos850-mct
|
||||
- samsung,exynos8895-mct
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
|
||||
@ -23,6 +23,7 @@ properties:
|
||||
- enum:
|
||||
- allwinner,sun8i-a83t-musb
|
||||
- allwinner,sun20i-d1-musb
|
||||
- allwinner,sun50i-a100-musb
|
||||
- allwinner,sun50i-h6-musb
|
||||
- const: allwinner,sun8i-a33-musb
|
||||
- items:
|
||||
|
||||
@ -28,6 +28,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- allwinner,sun4i-a10-ehci
|
||||
- allwinner,sun50i-a100-ehci
|
||||
- allwinner,sun50i-a64-ehci
|
||||
- allwinner,sun50i-h6-ehci
|
||||
- allwinner,sun50i-h616-ehci
|
||||
|
||||
@ -15,6 +15,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- allwinner,sun4i-a10-ohci
|
||||
- allwinner,sun50i-a100-ohci
|
||||
- allwinner,sun50i-a64-ohci
|
||||
- allwinner,sun50i-h6-ohci
|
||||
- allwinner,sun50i-h616-ohci
|
||||
|
||||
@ -312,6 +312,8 @@ patternProperties:
|
||||
description: Colorful GRP, Shenzhen Xueyushi Technology Ltd.
|
||||
"^compulab,.*":
|
||||
description: CompuLab Ltd.
|
||||
"^comvetia,.*":
|
||||
description: ComVetia AG
|
||||
"^congatec,.*":
|
||||
description: congatec GmbH
|
||||
"^coolpi,.*":
|
||||
@ -356,6 +358,8 @@ patternProperties:
|
||||
description: DataImage, Inc.
|
||||
"^davicom,.*":
|
||||
description: DAVICOM Semiconductor, Inc.
|
||||
"^deepcomputing,.*":
|
||||
description: DeepComputing (HK) Limited
|
||||
"^dell,.*":
|
||||
description: Dell Inc.
|
||||
"^delta,.*":
|
||||
@ -1045,6 +1049,8 @@ patternProperties:
|
||||
description: Nokia
|
||||
"^nordic,.*":
|
||||
description: Nordic Semiconductor
|
||||
"^nothing,.*":
|
||||
description: Nothing Technology Limited
|
||||
"^novatek,.*":
|
||||
description: Novatek
|
||||
"^novtech,.*":
|
||||
@ -1224,6 +1230,8 @@ patternProperties:
|
||||
description: Unisoc Communications, Inc.
|
||||
"^realtek,.*":
|
||||
description: Realtek Semiconductor Corp.
|
||||
"^relfor,.*":
|
||||
description: Relfor Labs Pvt. Ltd.
|
||||
"^remarkable,.*":
|
||||
description: reMarkable AS
|
||||
"^renesas,.*":
|
||||
@ -1386,6 +1394,8 @@ patternProperties:
|
||||
description: Sophgo Technology Inc.
|
||||
"^sourceparts,.*":
|
||||
description: Source Parts Inc.
|
||||
"^spacemit,.*":
|
||||
description: SpacemiT (Hangzhou) Technology Co. Ltd
|
||||
"^spansion,.*":
|
||||
description: Spansion Inc.
|
||||
"^sparkfun,.*":
|
||||
|
||||
@ -16,6 +16,11 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apple,s5l8960x-wdt
|
||||
- apple,t7000-wdt
|
||||
- apple,s8000-wdt
|
||||
- apple,t8010-wdt
|
||||
- apple,t8015-wdt
|
||||
- apple,t8103-wdt
|
||||
- apple,t8112-wdt
|
||||
- apple,t6000-wdt
|
||||
|
||||
@ -32,6 +32,7 @@ properties:
|
||||
- rockchip,rk3576-wdt
|
||||
- rockchip,rk3588-wdt
|
||||
- rockchip,rv1108-wdt
|
||||
- rockchip,rv1126-wdt
|
||||
- const: snps,dw-wdt
|
||||
|
||||
reg:
|
||||
|
||||
@ -215,6 +215,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
|
||||
sun8i-a33-olinuxino.dtb \
|
||||
sun8i-a33-q8-tablet.dtb \
|
||||
sun8i-a33-sinlinx-sina33.dtb \
|
||||
sun8i-a33-vstar.dtb \
|
||||
sun8i-a83t-allwinner-h8homlet-v2.dtb \
|
||||
sun8i-a83t-bananapi-m3.dtb \
|
||||
sun8i-a83t-cubietruck-plus.dtb \
|
||||
@ -268,7 +269,3 @@ dtb-$(CONFIG_MACH_SUNIV) += \
|
||||
suniv-f1c100s-licheepi-nano.dtb \
|
||||
suniv-f1c200s-lctech-pi.dtb \
|
||||
suniv-f1c200s-popstick-v1.1.dtb
|
||||
dtb-$(CONFIG_MACH_SUNIV) += \
|
||||
suniv-f1c100s-licheepi-nano.dtb \
|
||||
suniv-f1c200s-lctech-pi.dtb \
|
||||
suniv-f1c200s-popstick-v1.1.dtb
|
||||
|
||||
96
arch/arm/boot/dts/allwinner/sun8i-a33-vstar-core1.dtsi
Normal file
96
arch/arm/boot/dts/allwinner/sun8i-a33-vstar-core1.dtsi
Normal file
@ -0,0 +1,96 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2024 Icenowy Zheng <uwu@icenowy.me>
|
||||
*/
|
||||
|
||||
#include "sun8i-a33.dtsi"
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_8bit_pins>;
|
||||
vmmc-supply = <®_dcdc1>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
cap-mmc-hw-reset;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc2_8bit_pins {
|
||||
/* Increase drive strength for DDR modes */
|
||||
drive-strength = <40>;
|
||||
};
|
||||
|
||||
&r_rsb {
|
||||
status = "okay";
|
||||
|
||||
axp22x: pmic@3a3 {
|
||||
compatible = "x-powers,axp223";
|
||||
reg = <0x3a3>;
|
||||
interrupt-parent = <&r_intc>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
|
||||
eldoin-supply = <®_dcdc1>;
|
||||
x-powers,drive-vbus-en;
|
||||
};
|
||||
};
|
||||
|
||||
#include "axp223.dtsi"
|
||||
|
||||
®_aldo1 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-io";
|
||||
};
|
||||
|
||||
®_aldo2 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <2350000>;
|
||||
regulator-max-microvolt = <2650000>;
|
||||
regulator-name = "vdd-dll";
|
||||
};
|
||||
|
||||
®_aldo3 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-avcc";
|
||||
};
|
||||
|
||||
®_dc5ldo {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "vdd-cpus";
|
||||
};
|
||||
|
||||
®_dcdc1 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-3v3";
|
||||
};
|
||||
|
||||
®_dcdc2 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "vdd-sys";
|
||||
};
|
||||
|
||||
®_dcdc3 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "vdd-cpu";
|
||||
};
|
||||
|
||||
®_dcdc5 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vcc-dram";
|
||||
};
|
||||
|
||||
®_rtc_ldo {
|
||||
regulator-name = "vcc-rtc";
|
||||
};
|
||||
205
arch/arm/boot/dts/allwinner/sun8i-a33-vstar.dts
Normal file
205
arch/arm/boot/dts/allwinner/sun8i-a33-vstar.dts
Normal file
@ -0,0 +1,205 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2024 Icenowy Zheng <uwu@icenowy.me>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sun8i-a33-vstar-core1.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Rervision A33-Vstar";
|
||||
compatible = "rervision,a33-vstar",
|
||||
"rervision,a33-core1",
|
||||
"allwinner,sun8i-a33";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
ethernet0 = &r8152;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
reg_usb1_vbus: regulator-usb1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
|
||||
};
|
||||
|
||||
wifi_pwrseq: pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
|
||||
clocks = <&rtc CLK_OSC32K_FANOUT>;
|
||||
clock-names = "ext_clock";
|
||||
};
|
||||
};
|
||||
|
||||
&ac_power_supply {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&codec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dai {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
hub@1 {
|
||||
/* Onboard GL850G hub which needs no extra power sequence */
|
||||
compatible = "usb5e3,608";
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
r8152: ethernet@4 {
|
||||
/*
|
||||
* Onboard Realtek RTL8152 USB Ethernet,
|
||||
* with no MAC address programmed
|
||||
*/
|
||||
compatible = "usbbda,8152";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lradc {
|
||||
vref-supply = <®_aldo3>;
|
||||
status = "okay";
|
||||
|
||||
button-191 {
|
||||
label = "V+";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
channel = <0>;
|
||||
voltage = <191011>;
|
||||
};
|
||||
|
||||
button-391 {
|
||||
label = "V-";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
channel = <0>;
|
||||
voltage = <391304>;
|
||||
};
|
||||
|
||||
button-600 {
|
||||
label = "BACK";
|
||||
linux,code = <KEY_BACK>;
|
||||
channel = <0>;
|
||||
voltage = <600000>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
vmmc-supply = <®_dcdc1>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pg_pins>;
|
||||
vmmc-supply = <®_dldo1>;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
|
||||
brcmf: wifi@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&r_pio>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same
|
||||
* time, with the two being in sync. Since this is not really
|
||||
* supported right now, just use the two as always on, and we will fix
|
||||
* it later.
|
||||
*/
|
||||
®_dldo1 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-wifi0";
|
||||
};
|
||||
|
||||
®_dldo2 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-wifi1";
|
||||
};
|
||||
|
||||
®_drivevbus {
|
||||
regulator-name = "usb0-vbus";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sound {
|
||||
/* TODO: on-board microphone */
|
||||
|
||||
simple-audio-card,widgets = "Headphone", "Headphone Jack";
|
||||
simple-audio-card,routing =
|
||||
"Left DAC", "DACL",
|
||||
"Right DAC", "DACR",
|
||||
"Headphone Jack", "HP";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pb_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
clocks = <&rtc CLK_OSC32K_FANOUT>;
|
||||
clock-names = "lpo";
|
||||
vbat-supply = <®_dldo1>;
|
||||
device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
|
||||
host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
|
||||
shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
|
||||
};
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_power_supply {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
|
||||
usb0_vbus_power-supply = <&usb_power_supply>;
|
||||
usb0_vbus-supply = <®_drivevbus>;
|
||||
usb1_vbus-supply = <®_usb1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -280,8 +280,8 @@
|
||||
|
||||
reg_dcdc5: dcdc5 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1425000>;
|
||||
regulator-max-microvolt = <1575000>;
|
||||
regulator-min-microvolt = <1450000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-name = "vcc-dram";
|
||||
};
|
||||
|
||||
|
||||
@ -1,6 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_MACH_MESON6) += \
|
||||
meson6-atv1200.dtb
|
||||
dtb-$(CONFIG_MACH_MESON8) += \
|
||||
meson8-minix-neo-x8.dtb \
|
||||
meson8b-ec100.dtb \
|
||||
|
||||
@ -1,33 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright 2014 Carlo Caione <carlo@caione.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "meson6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Geniatech ATV1200";
|
||||
compatible = "geniatech,atv1200", "amlogic,meson6";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
};
|
||||
@ -1,73 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright 2014 Carlo Caione <carlo@caione.org>
|
||||
*/
|
||||
|
||||
#include "meson.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Amlogic Meson6 SoC";
|
||||
compatible = "amlogic,meson6";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x200>;
|
||||
};
|
||||
|
||||
cpu@201 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x201>;
|
||||
};
|
||||
};
|
||||
|
||||
apb2: bus@d0000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0xd0000000 0x40000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xd0000000 0x40000>;
|
||||
};
|
||||
|
||||
clk81: clk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
}; /* end of / */
|
||||
|
||||
&efuse {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timer_abcde {
|
||||
clocks = <&xtal>, <&clk81>;
|
||||
clock-names = "xtal", "pclk";
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
clocks = <&xtal>, <&clk81>, <&clk81>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
clocks = <&xtal>, <&clk81>, <&clk81>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_B {
|
||||
clocks = <&xtal>, <&clk81>, <&clk81>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_C {
|
||||
clocks = <&xtal>, <&clk81>, <&clk81>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
@ -19,7 +19,7 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
@ -93,5 +93,6 @@
|
||||
ðmac {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ð_pins>;
|
||||
pnictrl-names = "default";
|
||||
pinctrl-names = "default";
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
@ -196,7 +196,7 @@
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc {
|
||||
soc-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
thermal-sensors = <&thermal_sensor>;
|
||||
@ -346,17 +346,16 @@
|
||||
reg = <0xe0 0x18>;
|
||||
};
|
||||
|
||||
pinctrl_aobus: pinctrl@84 {
|
||||
pinctrl_aobus: pinctrl@14 {
|
||||
compatible = "amlogic,meson8-aobus-pinctrl";
|
||||
reg = <0x84 0xc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x0 0x14 0x1c>;
|
||||
|
||||
gpio_ao: ao-bank@14 {
|
||||
reg = <0x14 0x4>,
|
||||
<0x2c 0x4>,
|
||||
<0x24 0x8>;
|
||||
gpio_ao: bank@0 {
|
||||
reg = <0x0 0x4>,
|
||||
<0x18 0x4>,
|
||||
<0x10 0x8>;
|
||||
reg-names = "mux", "pull", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -461,18 +460,17 @@
|
||||
reg = <0x8758 0x1c>;
|
||||
};
|
||||
|
||||
pinctrl_cbus: pinctrl@9880 {
|
||||
pinctrl_cbus: pinctrl@8030 {
|
||||
compatible = "amlogic,meson8-cbus-pinctrl";
|
||||
reg = <0x9880 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x0 0x8030 0x108>;
|
||||
|
||||
gpio: banks@80b0 {
|
||||
reg = <0x80b0 0x28>,
|
||||
<0x80e8 0x18>,
|
||||
<0x8120 0x18>,
|
||||
<0x8030 0x30>;
|
||||
gpio: bank@80 {
|
||||
reg = <0x80 0x28>,
|
||||
<0xb8 0x18>,
|
||||
<0xf0 0x18>,
|
||||
<0x00 0x30>;
|
||||
reg-names = "mux", "pull", "pull-enable", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -589,7 +587,7 @@
|
||||
};
|
||||
|
||||
&ahb_sram {
|
||||
ao_arc_sram: ao-arc-sram@0 {
|
||||
ao_arc_sram: aoarc-sram@0 {
|
||||
compatible = "amlogic,meson8-ao-arc-sram";
|
||||
reg = <0x0 0x8000>;
|
||||
pool;
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
@ -98,6 +98,10 @@
|
||||
compatible = "amlogic,gx-sound-card";
|
||||
model = "M8B-EC100";
|
||||
|
||||
clocks = <&clkc CLKID_MPLL0>,
|
||||
<&clkc CLKID_MPLL1>,
|
||||
<&clkc CLKID_MPLL2>;
|
||||
|
||||
assigned-clocks = <&clkc CLKID_MPLL0>,
|
||||
<&clkc CLKID_MPLL1>,
|
||||
<&clkc CLKID_MPLL2>;
|
||||
@ -427,7 +431,7 @@
|
||||
"NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",
|
||||
"NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",
|
||||
"NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",
|
||||
"nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS",
|
||||
"nWE_S1 NAND_nWE (EMMC)", "", "", "", "SPI_CS",
|
||||
/* Bank DIF */
|
||||
"RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV",
|
||||
"RMII_50M_IN", "GPIODIF_4", "GPIODIF_5",
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
@ -378,6 +378,6 @@
|
||||
compatible = "usb5e3,610";
|
||||
reg = <1>;
|
||||
vdd-supply = <&p5v0>;
|
||||
reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -173,7 +173,7 @@
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc {
|
||||
soc-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
thermal-sensors = <&thermal_sensor>;
|
||||
@ -308,17 +308,16 @@
|
||||
reg = <0xe0 0x18>;
|
||||
};
|
||||
|
||||
pinctrl_aobus: pinctrl@84 {
|
||||
pinctrl_aobus: pinctrl@14 {
|
||||
compatible = "amlogic,meson8b-aobus-pinctrl";
|
||||
reg = <0x84 0xc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x0 0x14 0x1c>;
|
||||
|
||||
gpio_ao: ao-bank@14 {
|
||||
reg = <0x14 0x4>,
|
||||
<0x2c 0x4>,
|
||||
<0x24 0x8>;
|
||||
gpio_ao: bank@0 {
|
||||
reg = <0x0 0x4>,
|
||||
<0x18 0x4>,
|
||||
<0x10 0x8>;
|
||||
reg-names = "mux", "pull", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -415,18 +414,17 @@
|
||||
reg = <0x8758 0x1c>;
|
||||
};
|
||||
|
||||
pinctrl_cbus: pinctrl@9880 {
|
||||
pinctrl_cbus: pinctrl@8030 {
|
||||
compatible = "amlogic,meson8b-cbus-pinctrl";
|
||||
reg = <0x9880 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x0 0x8030 0x108>;
|
||||
|
||||
gpio: banks@80b0 {
|
||||
reg = <0x80b0 0x28>,
|
||||
<0x80e8 0x18>,
|
||||
<0x8120 0x18>,
|
||||
<0x8030 0x38>;
|
||||
gpio: bank@80 {
|
||||
reg = <0x80 0x28>,
|
||||
<0xb8 0x18>,
|
||||
<0xf0 0x18>,
|
||||
<0x00 0x38>;
|
||||
reg-names = "mux", "pull", "pull-enable", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
@ -535,7 +533,7 @@
|
||||
};
|
||||
|
||||
&ahb_sram {
|
||||
ao_arc_sram: ao-arc-sram@0 {
|
||||
ao_arc_sram: aoarc-sram@0 {
|
||||
compatible = "amlogic,meson8b-ao-arc-sram";
|
||||
reg = <0x0 0x8000>;
|
||||
pool;
|
||||
|
||||
@ -26,7 +26,7 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
|
||||
@ -135,7 +135,7 @@
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c01";
|
||||
pagesize = <8>;
|
||||
reg = <0x50>;
|
||||
@ -211,7 +211,7 @@
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
at24@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
pagesize = <8>;
|
||||
reg = <0x50>;
|
||||
|
||||
@ -251,6 +251,7 @@
|
||||
led-controller@2b {
|
||||
compatible = "cznic,turris-omnia-leds";
|
||||
reg = <0x2b>;
|
||||
interrupts-extended = <&mcu 11 IRQ_TYPE_NONE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
@ -44,7 +44,7 @@
|
||||
i2c@11100 {
|
||||
status = "okay";
|
||||
|
||||
s24c02: s24c02@50 {
|
||||
s24c02: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
# Enables support for device-tree overlays
|
||||
DTC_FLAGS_at91-sam9x60_curiosity := -@
|
||||
DTC_FLAGS_at91-sam9x60ek := -@
|
||||
DTC_FLAGS_at91-sam9x75_curiosity := -@
|
||||
DTC_FLAGS_at91-sama5d27_som1_ek := -@
|
||||
DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@
|
||||
DTC_FLAGS_at91-sama5d29_curiosity := -@
|
||||
@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
|
||||
dtb-$(CONFIG_SOC_SAM9X60) += \
|
||||
at91-sam9x60_curiosity.dtb \
|
||||
at91-sam9x60ek.dtb
|
||||
dtb-$(CONFIG_SOC_SAM9X7) += \
|
||||
at91-sam9x75_curiosity.dtb
|
||||
dtb-$(CONFIG_SOC_SAM_V7) += \
|
||||
at91-kizbox2-2.dtb \
|
||||
at91-kizbox3-hs.dtb \
|
||||
|
||||
@ -98,23 +98,27 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
red {
|
||||
led-red {
|
||||
label = "red";
|
||||
gpios = <&pioC 10 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
green {
|
||||
led-green {
|
||||
label = "green";
|
||||
gpios = <&pioA 5 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
yellow {
|
||||
led-yellow {
|
||||
label = "yellow";
|
||||
gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
blue {
|
||||
led-blue {
|
||||
label = "blue";
|
||||
gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
@ -146,23 +146,23 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_green {
|
||||
led-power-green {
|
||||
label = "power_green";
|
||||
gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
power_red {
|
||||
led-power-red {
|
||||
label = "power_red";
|
||||
gpios = <&pioA 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
tx_green {
|
||||
led-tx-green {
|
||||
label = "tx_green";
|
||||
gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
tx_red {
|
||||
led-tx-red {
|
||||
label = "tx_red";
|
||||
gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
@ -85,7 +85,7 @@
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
pmic: act8865@5b {
|
||||
act8865: pmic@5b {
|
||||
compatible = "active-semi,act8865";
|
||||
reg = <0x5b>;
|
||||
status = "okay";
|
||||
|
||||
@ -53,17 +53,17 @@
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
status = "okay"; /* Conflict with pwm0. */
|
||||
|
||||
red {
|
||||
led-red {
|
||||
label = "red";
|
||||
gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
green {
|
||||
led-green {
|
||||
label = "green";
|
||||
gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
blue {
|
||||
led-blue {
|
||||
label = "blue";
|
||||
gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
@ -260,6 +260,37 @@
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
status = "okay";
|
||||
|
||||
power-monitor@17 {
|
||||
compatible = "microchip,pac1934";
|
||||
reg = <0x17>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
channel@1 {
|
||||
reg = <0x1>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDDIOM";
|
||||
};
|
||||
|
||||
channel@2 {
|
||||
reg = <0x2>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDDCORE";
|
||||
};
|
||||
|
||||
channel@3 {
|
||||
reg = <0x3>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDD3V3_MPU";
|
||||
};
|
||||
|
||||
channel@4 {
|
||||
reg = <0x4>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDD3V3";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_exp: mcp23008@20 {
|
||||
compatible = "microchip,mcp23008";
|
||||
reg = <0x20>;
|
||||
|
||||
324
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
Normal file
324
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
Normal file
@ -0,0 +1,324 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
|
||||
*
|
||||
* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
|
||||
*
|
||||
* Author: Varshini Rajendran <varshini.rajendran@microchip.com>
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "sam9x7.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Microchip SAM9X75 Curiosity";
|
||||
compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c6;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_key_gpio_default>;
|
||||
|
||||
button-user {
|
||||
label = "USER";
|
||||
gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_0>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
led-controller {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_red: led-red {
|
||||
label = "red";
|
||||
gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&pinctrl_red_led_gpio_default>;
|
||||
};
|
||||
|
||||
led_green: led-green {
|
||||
label = "green";
|
||||
gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&pinctrl_green_led_gpio_default>;
|
||||
};
|
||||
|
||||
led_blue: led-blue {
|
||||
label = "blue";
|
||||
gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&pinctrl_blue_led_gpio_default>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
memory@20000000 {
|
||||
reg = <0x20000000 0x10000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
};
|
||||
|
||||
&classd {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_classd_default>;
|
||||
atmel,pwm-type = "diff";
|
||||
atmel,non-overlap-time = <10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dbgu {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dma0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flx6 {
|
||||
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flx6_default>;
|
||||
i2c-analog-filter;
|
||||
i2c-digital-filter;
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
status = "okay";
|
||||
|
||||
pmic@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
|
||||
regulators {
|
||||
vdd_3v3: VDD_IO {
|
||||
regulator-name = "VDD_IO";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
vddioddr: VDD_DDR {
|
||||
regulator-name = "VDD_DDR";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
vddcore: VDD_CORE {
|
||||
regulator-name = "VDD_CORE";
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
dcdc4: VDD_OTHER {
|
||||
regulator-name = "VDD_OTHER";
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-ramp-delay = <3125>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
vldo1: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vldo2: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2s_default>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_xtal {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
classd {
|
||||
pinctrl_classd_default: classd-default {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu {
|
||||
pinctrl_dbgu_default: dbgu-default {
|
||||
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
flexcom {
|
||||
pinctrl_flx6_default: flx6-default {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
pinctrl_key_gpio_default: key-gpio-default {
|
||||
atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s {
|
||||
pinctrl_i2s_default: i2s-default {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE>, /* I2SCK */
|
||||
<AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE>, /* I2SWS */
|
||||
<AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE>, /* I2SDIN */
|
||||
<AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE>, /* I2SDOUT */
|
||||
<AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>; /* I2SMCK */
|
||||
};
|
||||
};
|
||||
|
||||
led-controller {
|
||||
pinctrl_red_led_gpio_default: red-led-gpio-default {
|
||||
atmel,pins = <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
|
||||
};
|
||||
pinctrl_green_led_gpio_default: green-led-gpio-default {
|
||||
atmel,pins = <AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
|
||||
};
|
||||
pinctrl_blue_led_gpio_default: blue-led-gpio-default {
|
||||
atmel,pins = <AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc0 {
|
||||
pinctrl_sdmmc0_default: sdmmc0-default {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>, /* PA2 CK periph A with pullup */
|
||||
<AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>, /* PA1 CMD periph A with pullup */
|
||||
<AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>, /* PA0 DAT0 periph A */
|
||||
<AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>, /* PA3 DAT1 periph A with pullup */
|
||||
<AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>, /* PA4 DAT2 periph A with pullup */
|
||||
<AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA5 DAT3 periph A with pullup */
|
||||
};
|
||||
};
|
||||
}; /* pinctrl */
|
||||
|
||||
&poweroff {
|
||||
debounce-delay-us = <976>;
|
||||
status = "okay";
|
||||
|
||||
input@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&rtt {
|
||||
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdmmc0_default>;
|
||||
cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&tcb {
|
||||
timer0: timer@0 {
|
||||
compatible = "atmel,tcb-timer";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
timer1: timer@1 {
|
||||
compatible = "atmel,tcb-timer";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&trng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
@ -106,7 +106,7 @@
|
||||
scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
at24@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
|
||||
@ -75,7 +75,7 @@
|
||||
scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
mcp16502@5b {
|
||||
pmic@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
|
||||
@ -149,7 +149,7 @@
|
||||
i2c-sda-hold-time-ns = <350>;
|
||||
status = "okay";
|
||||
|
||||
mcp16502@5b {
|
||||
pmic@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
|
||||
@ -195,7 +195,38 @@
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
status = "okay";
|
||||
|
||||
mcp16502@5b {
|
||||
power-monitor@10 {
|
||||
compatible = "microchip,pac1934";
|
||||
reg = <0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
channel@1 {
|
||||
reg = <0x1>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDD3V3_1";
|
||||
};
|
||||
|
||||
channel@2 {
|
||||
reg = <0x2>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDD3V3_2";
|
||||
};
|
||||
|
||||
channel@3 {
|
||||
reg = <0x3>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDDCORE";
|
||||
};
|
||||
|
||||
channel@4 {
|
||||
reg = <0x4>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDDIODDR";
|
||||
};
|
||||
};
|
||||
|
||||
pmic@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
|
||||
@ -231,7 +231,7 @@
|
||||
scl-gpios = <&pioA PIN_PC7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
at24@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
|
||||
@ -411,7 +411,7 @@
|
||||
scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
at24@54 {
|
||||
eeprom@54 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x54>;
|
||||
pagesize = <16>;
|
||||
|
||||
@ -87,7 +87,7 @@
|
||||
i2c1: i2c@f0018000 {
|
||||
status = "okay";
|
||||
|
||||
pmic: act8865@5b {
|
||||
act8865: pmic@5b {
|
||||
compatible = "active-semi,act8865";
|
||||
reg = <0x5b>;
|
||||
status = "disabled";
|
||||
|
||||
@ -186,6 +186,37 @@
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
status = "okay";
|
||||
|
||||
power-monitor@1f {
|
||||
compatible = "microchip,pac1934";
|
||||
reg = <0x1f>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
channel@1 {
|
||||
reg = <0x1>;
|
||||
shunt-resistor-micro-ohms = <47000>;
|
||||
label = "VDD3V3";
|
||||
};
|
||||
|
||||
channel@2 {
|
||||
reg = <0x2>;
|
||||
shunt-resistor-micro-ohms = <47000>;
|
||||
label = "VDDIODDR";
|
||||
};
|
||||
|
||||
channel@3 {
|
||||
reg = <0x3>;
|
||||
shunt-resistor-micro-ohms = <47000>;
|
||||
label = "VDDCORE";
|
||||
};
|
||||
|
||||
channel@4 {
|
||||
reg = <0x4>;
|
||||
shunt-resistor-micro-ohms = <47000>;
|
||||
label = "VDDCPU";
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x51>;
|
||||
|
||||
@ -244,7 +244,38 @@
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
status = "okay";
|
||||
|
||||
mcp16502@5b {
|
||||
power-monitor@10 {
|
||||
compatible = "microchip,pac1934";
|
||||
reg = <0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
channel@1 {
|
||||
reg = <0x1>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDD3V3";
|
||||
};
|
||||
|
||||
channel@2 {
|
||||
reg = <0x2>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDDIODDR";
|
||||
};
|
||||
|
||||
channel@3 {
|
||||
reg = <0x3>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDDCORE";
|
||||
};
|
||||
|
||||
channel@4 {
|
||||
reg = <0x4>;
|
||||
shunt-resistor-micro-ohms = <10000>;
|
||||
label = "VDDCPU";
|
||||
};
|
||||
};
|
||||
|
||||
pmic@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
|
||||
@ -127,19 +127,19 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds2 {
|
||||
led-ds2 {
|
||||
label = "green";
|
||||
gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
ds4 {
|
||||
led-ds4 {
|
||||
label = "yellow";
|
||||
gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds6 {
|
||||
led-ds6 {
|
||||
label = "red";
|
||||
gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
@ -165,7 +165,7 @@
|
||||
i2c-gpio-0 {
|
||||
status = "okay";
|
||||
|
||||
24c512@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x50>;
|
||||
};
|
||||
@ -174,13 +174,13 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds1 {
|
||||
led-ds1 {
|
||||
label = "ds1";
|
||||
gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds5 {
|
||||
led-ds5 {
|
||||
label = "ds5";
|
||||
gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
@ -192,19 +192,19 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds8 {
|
||||
led-ds8 {
|
||||
label = "ds8";
|
||||
gpios = <&pioA 13 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
ds7 {
|
||||
led-ds7 {
|
||||
label = "ds7";
|
||||
gpios = <&pioA 14 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "nand-disk";
|
||||
};
|
||||
|
||||
ds1 {
|
||||
led-ds1 {
|
||||
label = "ds1";
|
||||
gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
||||
@ -219,13 +219,13 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
d3 {
|
||||
led-d3 {
|
||||
label = "d3";
|
||||
gpios = <&pioB 7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
d2 {
|
||||
led-d2 {
|
||||
label = "d2";
|
||||
gpios = <&pioC 29 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "nand-disk";
|
||||
@ -253,7 +253,7 @@
|
||||
i2c-gpio-0 {
|
||||
status = "okay";
|
||||
|
||||
24c512@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x50>;
|
||||
pagesize = <128>;
|
||||
|
||||
@ -14,13 +14,13 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds1 {
|
||||
led-ds1 {
|
||||
label = "ds1";
|
||||
gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds5 {
|
||||
led-ds5 {
|
||||
label = "ds5";
|
||||
gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
@ -220,7 +220,7 @@
|
||||
i2c-gpio-0 {
|
||||
status = "okay";
|
||||
|
||||
24c512@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x50>;
|
||||
vcc-supply = <®_3v3>;
|
||||
|
||||
@ -753,7 +753,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trng@fffcc000 {
|
||||
trng: rng@fffcc000 {
|
||||
compatible = "atmel,at91sam9g45-trng";
|
||||
reg = <0xfffcc000 0x100>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
@ -186,6 +186,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -388,6 +389,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -439,6 +441,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -486,7 +489,7 @@
|
||||
clock-names = "sha_clk";
|
||||
};
|
||||
|
||||
trng: trng@f0030000 {
|
||||
trng: rng@f0030000 {
|
||||
compatible = "microchip,sam9x60-trng";
|
||||
reg = <0xf0030000 0x100>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
@ -598,6 +601,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -649,6 +653,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -700,6 +705,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -751,6 +757,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -821,6 +828,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -891,6 +899,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -961,6 +970,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -1086,6 +1096,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
@ -1137,6 +1148,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
|
||||
clock-names = "usart";
|
||||
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
atmel,fifo-size = <16>;
|
||||
|
||||
1220
arch/arm/boot/dts/microchip/sam9x7.dtsi
Normal file
1220
arch/arm/boot/dts/microchip/sam9x7.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@ -1019,7 +1019,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
trng@fc01c000 {
|
||||
trng: rng@fc01c000 {
|
||||
compatible = "atmel,at91sam9g45-trng";
|
||||
reg = <0xfc01c000 0x100>;
|
||||
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
@ -419,7 +419,7 @@
|
||||
clock-names = "tdes_clk";
|
||||
};
|
||||
|
||||
trng@f8040000 {
|
||||
trng: rng@f8040000 {
|
||||
compatible = "atmel,at91sam9g45-trng";
|
||||
reg = <0xf8040000 0x100>;
|
||||
interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
i2c1: i2c@f0018000 {
|
||||
status = "okay";
|
||||
|
||||
24c256@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c256";
|
||||
reg = <0x50>;
|
||||
pagesize = <64>;
|
||||
|
||||
@ -79,7 +79,7 @@
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
pmic: act8865@5b {
|
||||
act8865: pmic@5b {
|
||||
compatible = "active-semi,act8865";
|
||||
reg = <0x5b>;
|
||||
status = "disabled";
|
||||
|
||||
@ -658,7 +658,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trng@fc030000 {
|
||||
trng: rng@fc030000 {
|
||||
compatible = "atmel,at91sam9g45-trng";
|
||||
reg = <0xfc030000 0x100>;
|
||||
interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
@ -73,6 +73,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
||||
imx6dl-cubox-i-emmc-som-v15.dtb \
|
||||
imx6dl-cubox-i-som-v15.dtb \
|
||||
imx6dl-dfi-fs700-m60.dtb \
|
||||
imx6dl-dhcom-pdk2.dtb \
|
||||
imx6dl-dhcom-picoitx.dtb \
|
||||
imx6dl-eckelmann-ci4x10.dtb \
|
||||
imx6dl-emcon-avari.dtb \
|
||||
@ -211,6 +212,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
||||
imx6q-kontron-samx6i-ads2.dtb \
|
||||
imx6q-kp-tpc.dtb \
|
||||
imx6q-logicpd.dtb \
|
||||
imx6q-lxr.dtb \
|
||||
imx6q-marsboard.dtb \
|
||||
imx6q-mba6a.dtb \
|
||||
imx6q-mba6b.dtb \
|
||||
@ -290,6 +292,8 @@ dtb-$(CONFIG_SOC_IMX6SL) += \
|
||||
dtb-$(CONFIG_SOC_IMX6SLL) += \
|
||||
imx6sll-evk.dtb \
|
||||
imx6sll-kobo-clarahd.dtb \
|
||||
imx6sll-kobo-clara2e-a.dtb \
|
||||
imx6sll-kobo-clara2e-b.dtb \
|
||||
imx6sll-kobo-librah2o.dtb
|
||||
dtb-$(CONFIG_SOC_IMX6SX) += \
|
||||
imx6sx-nitrogen6sx.dtb \
|
||||
|
||||
@ -44,40 +44,38 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx35-eukrea {
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
|
||||
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000
|
||||
MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
|
||||
MX35_PAD_FEC_COL__FEC_COL 0x80000000
|
||||
MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000
|
||||
MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000
|
||||
MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX35_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000
|
||||
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000
|
||||
MX35_PAD_FEC_CRS__FEC_CRS 0x80000000
|
||||
MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000
|
||||
MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000
|
||||
MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000
|
||||
MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000
|
||||
MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000
|
||||
MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
|
||||
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000
|
||||
MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
|
||||
MX35_PAD_FEC_COL__FEC_COL 0x80000000
|
||||
MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000
|
||||
MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000
|
||||
MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX35_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000
|
||||
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000
|
||||
MX35_PAD_FEC_CRS__FEC_CRS 0x80000000
|
||||
MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000
|
||||
MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000
|
||||
MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000
|
||||
MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000
|
||||
MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000
|
||||
MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000
|
||||
MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000
|
||||
MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tsc2007_1: tsc2007grp-1 {
|
||||
fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>;
|
||||
};
|
||||
pinctrl_tsc2007_1: tsc2007-1-grp {
|
||||
fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -69,57 +69,55 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx35-eukrea {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000
|
||||
MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000
|
||||
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000
|
||||
MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000
|
||||
MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000
|
||||
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000
|
||||
MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_bp1: bp1grp {
|
||||
fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>;
|
||||
};
|
||||
pinctrl_bp1: bp1grp {
|
||||
fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
|
||||
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
|
||||
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
|
||||
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
|
||||
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
|
||||
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
|
||||
MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
|
||||
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
|
||||
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
|
||||
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
|
||||
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
|
||||
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
|
||||
MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_led1: led1grp {
|
||||
fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>;
|
||||
};
|
||||
pinctrl_led1: led1grp {
|
||||
fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>;
|
||||
};
|
||||
|
||||
pinctrl_reg_lcd_3v3: reg-lcd-3v3 {
|
||||
fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>;
|
||||
};
|
||||
pinctrl_reg_lcd_3v3: reg-lcd-3v3grp {
|
||||
fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
|
||||
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
|
||||
MX35_PAD_CTS1__UART1_CTS 0x1c5
|
||||
MX35_PAD_RTS1__UART1_RTS 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
|
||||
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
|
||||
MX35_PAD_CTS1__UART1_CTS 0x1c5
|
||||
MX35_PAD_RTS1__UART1_RTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5
|
||||
MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5
|
||||
MX35_PAD_RTS2__UART2_RTS 0x1c5
|
||||
MX35_PAD_CTS2__UART2_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5
|
||||
MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5
|
||||
MX35_PAD_RTS2__UART2_RTS 0x1c5
|
||||
MX35_PAD_CTS2__UART2_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -24,26 +24,24 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx35-pdk {
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
|
||||
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
|
||||
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
|
||||
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
|
||||
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
|
||||
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
|
||||
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
|
||||
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
|
||||
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
|
||||
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
|
||||
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
|
||||
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
|
||||
MX35_PAD_CTS1__UART1_CTS 0x1c5
|
||||
MX35_PAD_RTS1__UART1_RTS 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
|
||||
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
|
||||
MX35_PAD_CTS1__UART1_CTS 0x1c5
|
||||
MX35_PAD_RTS1__UART1_RTS 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -156,7 +156,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@43fac000 {
|
||||
iomuxc: pinctrl@43fac000 {
|
||||
compatible = "fsl,imx35-iomuxc";
|
||||
reg = <0x43fac000 0x4000>;
|
||||
};
|
||||
|
||||
@ -52,40 +52,38 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx50-evk {
|
||||
pinctrl_cspi: cspigrp {
|
||||
fsl,pins = <
|
||||
MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
|
||||
MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
|
||||
MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
|
||||
MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
|
||||
MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84
|
||||
>;
|
||||
};
|
||||
pinctrl_cspi: cspigrp {
|
||||
fsl,pins = <
|
||||
MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
|
||||
MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
|
||||
MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
|
||||
MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
|
||||
MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX50_PAD_SSI_RXFS__FEC_MDC 0x80
|
||||
MX50_PAD_SSI_RXC__FEC_MDIO 0x80
|
||||
MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
|
||||
MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
|
||||
MX50_PAD_DISP_D2__FEC_RX_DV 0x80
|
||||
MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
|
||||
MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
|
||||
MX50_PAD_DISP_D5__FEC_TX_EN 0x80
|
||||
MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
|
||||
MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
|
||||
>;
|
||||
};
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX50_PAD_SSI_RXFS__FEC_MDC 0x80
|
||||
MX50_PAD_SSI_RXC__FEC_MDIO 0x80
|
||||
MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
|
||||
MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
|
||||
MX50_PAD_DISP_D2__FEC_RX_DV 0x80
|
||||
MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
|
||||
MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
|
||||
MX50_PAD_DISP_D5__FEC_TX_EN 0x80
|
||||
MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
|
||||
MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
|
||||
MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
|
||||
MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
|
||||
MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
|
||||
MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
|
||||
MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
|
||||
MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -283,7 +283,7 @@
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@53fa8000 {
|
||||
iomuxc: pinctrl@53fa8000 {
|
||||
compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
};
|
||||
|
||||
@ -37,36 +37,34 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-apf51 {
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -113,102 +113,100 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx51-apf51dev {
|
||||
pinctrl_backlight: backlightgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
|
||||
>;
|
||||
};
|
||||
pinctrl_backlight: backlightgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
|
||||
MX51_PAD_EIM_EB3__GPIO2_23 0x0C5
|
||||
MX51_PAD_EIM_CS4__GPIO2_29 0x100
|
||||
MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
|
||||
MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
|
||||
MX51_PAD_GPIO1_2__GPIO1_2 0x0C5
|
||||
MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
|
||||
>;
|
||||
};
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
|
||||
MX51_PAD_EIM_EB3__GPIO2_23 0x0C5
|
||||
MX51_PAD_EIM_CS4__GPIO2_29 0x100
|
||||
MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
|
||||
MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
|
||||
MX51_PAD_GPIO1_2__GPIO1_2 0x0C5
|
||||
MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
|
||||
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
|
||||
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
|
||||
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
|
||||
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
|
||||
>;
|
||||
};
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -474,246 +474,244 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-babbage {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
|
||||
>;
|
||||
};
|
||||
pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_clk26mhz_osc: clk26mhzoscgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI1_PIN12__GPIO3_1 0x85
|
||||
>;
|
||||
};
|
||||
pinctrl_clk26mhz_osc: clk26mhzoscgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI1_PIN12__GPIO3_1 0x85
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_clk26mhz_usb: clk26mhzusbgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D17__GPIO2_1 0x85
|
||||
>;
|
||||
};
|
||||
pinctrl_clk26mhz_usb: clk26mhzusbgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D17__GPIO2_1 0x85
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
|
||||
>;
|
||||
};
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
MX51_PAD_GPIO1_0__GPIO1_0 0x100
|
||||
MX51_PAD_GPIO1_1__GPIO1_1 0x100
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
MX51_PAD_GPIO1_0__GPIO1_0 0x100
|
||||
MX51_PAD_GPIO1_1__GPIO1_1 0x100
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
|
||||
MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
|
||||
MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
|
||||
MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
|
||||
MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
|
||||
MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
|
||||
MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
|
||||
MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
|
||||
MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
|
||||
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
|
||||
MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
|
||||
MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
|
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
|
||||
MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
|
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
|
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
|
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
|
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
|
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
|
||||
MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
|
||||
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
|
||||
>;
|
||||
};
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
|
||||
MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
|
||||
MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
|
||||
MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
|
||||
MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
|
||||
MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
|
||||
MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
|
||||
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
|
||||
MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
|
||||
MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
|
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
|
||||
MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
|
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
|
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
|
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
|
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
|
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
|
||||
MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
|
||||
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpiokeysgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_A27__GPIO2_21 0x5
|
||||
>;
|
||||
};
|
||||
pinctrl_gpio_keys: gpiokeysgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_A27__GPIO2_21 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_leds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D22__GPIO2_6 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_gpio_leds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D22__GPIO2_6 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
|
||||
>;
|
||||
};
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp2: ipudisp2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
|
||||
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
|
||||
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
|
||||
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
|
||||
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
|
||||
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
|
||||
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
|
||||
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
|
||||
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
|
||||
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
|
||||
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
|
||||
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
|
||||
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
|
||||
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
|
||||
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
|
||||
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
|
||||
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
|
||||
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
|
||||
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
|
||||
MX51_PAD_DI_GP4__DI2_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
pinctrl_ipu_disp2: ipudisp2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
|
||||
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
|
||||
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
|
||||
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
|
||||
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
|
||||
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
|
||||
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
|
||||
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
|
||||
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
|
||||
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
|
||||
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
|
||||
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
|
||||
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
|
||||
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
|
||||
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
|
||||
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
|
||||
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
|
||||
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
|
||||
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
|
||||
MX51_PAD_DI_GP4__DI2_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_kpp: kppgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
|
||||
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
|
||||
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
|
||||
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
|
||||
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
|
||||
>;
|
||||
};
|
||||
pinctrl_kpp: kppgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
|
||||
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
|
||||
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
|
||||
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
|
||||
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
|
||||
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
|
||||
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
|
||||
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
|
||||
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
|
||||
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
|
||||
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
|
||||
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
|
||||
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1reg: usbh1reggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D21__GPIO2_5 0x85
|
||||
>;
|
||||
};
|
||||
pinctrl_usbh1reg: usbh1reggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D21__GPIO2_5 0x85
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotgreg: usbotgreggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_7__GPIO1_7 0x85
|
||||
>;
|
||||
};
|
||||
pinctrl_usbotgreg: usbotgreggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_7__GPIO1_7 0x85
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -78,49 +78,47 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-digi-connectcore-jsk {
|
||||
pinctrl_owire: owiregrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000
|
||||
>;
|
||||
};
|
||||
pinctrl_owire: owiregrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
|
||||
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
|
||||
>;
|
||||
};
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
|
||||
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -215,162 +215,160 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-digi-connectcore-som {
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
|
||||
>;
|
||||
};
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed
|
||||
MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c2_gpio: i2c2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed
|
||||
MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_nfc: nfcgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D0__NANDF_D0 0x80000000
|
||||
MX51_PAD_NANDF_D1__NANDF_D1 0x80000000
|
||||
MX51_PAD_NANDF_D2__NANDF_D2 0x80000000
|
||||
MX51_PAD_NANDF_D3__NANDF_D3 0x80000000
|
||||
MX51_PAD_NANDF_D4__NANDF_D4 0x80000000
|
||||
MX51_PAD_NANDF_D5__NANDF_D5 0x80000000
|
||||
MX51_PAD_NANDF_D6__NANDF_D6 0x80000000
|
||||
MX51_PAD_NANDF_D7__NANDF_D7 0x80000000
|
||||
MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000
|
||||
MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000
|
||||
MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000
|
||||
MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000
|
||||
MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000
|
||||
MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000
|
||||
MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_nfc: nfcgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D0__NANDF_D0 0x80000000
|
||||
MX51_PAD_NANDF_D1__NANDF_D1 0x80000000
|
||||
MX51_PAD_NANDF_D2__NANDF_D2 0x80000000
|
||||
MX51_PAD_NANDF_D3__NANDF_D3 0x80000000
|
||||
MX51_PAD_NANDF_D4__NANDF_D4 0x80000000
|
||||
MX51_PAD_NANDF_D5__NANDF_D5 0x80000000
|
||||
MX51_PAD_NANDF_D6__NANDF_D6 0x80000000
|
||||
MX51_PAD_NANDF_D7__NANDF_D7 0x80000000
|
||||
MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000
|
||||
MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000
|
||||
MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000
|
||||
MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000
|
||||
MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000
|
||||
MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000
|
||||
MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lan9221: lan9221grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
pinctrl_lan9221: lan9221grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mc13892: mc13892grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
pinctrl_mc13892: mc13892grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mma7455l: mma7455lgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */
|
||||
MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */
|
||||
>;
|
||||
};
|
||||
pinctrl_mma7455l: mma7455lgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */
|
||||
MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim: weimgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_DA0__EIM_DA0 0x80000000
|
||||
MX51_PAD_EIM_DA1__EIM_DA1 0x80000000
|
||||
MX51_PAD_EIM_DA2__EIM_DA2 0x80000000
|
||||
MX51_PAD_EIM_DA3__EIM_DA3 0x80000000
|
||||
MX51_PAD_EIM_DA4__EIM_DA4 0x80000000
|
||||
MX51_PAD_EIM_DA5__EIM_DA5 0x80000000
|
||||
MX51_PAD_EIM_DA6__EIM_DA6 0x80000000
|
||||
MX51_PAD_EIM_DA7__EIM_DA7 0x80000000
|
||||
MX51_PAD_EIM_DA8__EIM_DA8 0x80000000
|
||||
MX51_PAD_EIM_DA9__EIM_DA9 0x80000000
|
||||
MX51_PAD_EIM_DA10__EIM_DA10 0x80000000
|
||||
MX51_PAD_EIM_DA11__EIM_DA11 0x80000000
|
||||
MX51_PAD_EIM_DA12__EIM_DA12 0x80000000
|
||||
MX51_PAD_EIM_DA13__EIM_DA13 0x80000000
|
||||
MX51_PAD_EIM_DA14__EIM_DA14 0x80000000
|
||||
MX51_PAD_EIM_DA15__EIM_DA15 0x80000000
|
||||
MX51_PAD_EIM_A16__EIM_A16 0x80000000
|
||||
MX51_PAD_EIM_A17__EIM_A17 0x80000000
|
||||
MX51_PAD_EIM_A18__EIM_A18 0x80000000
|
||||
MX51_PAD_EIM_A19__EIM_A19 0x80000000
|
||||
MX51_PAD_EIM_A20__EIM_A20 0x80000000
|
||||
MX51_PAD_EIM_A21__EIM_A21 0x80000000
|
||||
MX51_PAD_EIM_A22__EIM_A22 0x80000000
|
||||
MX51_PAD_EIM_A23__EIM_A23 0x80000000
|
||||
MX51_PAD_EIM_A24__EIM_A24 0x80000000
|
||||
MX51_PAD_EIM_A25__EIM_A25 0x80000000
|
||||
MX51_PAD_EIM_A26__EIM_A26 0x80000000
|
||||
MX51_PAD_EIM_A27__EIM_A27 0x80000000
|
||||
MX51_PAD_EIM_D16__EIM_D16 0x80000000
|
||||
MX51_PAD_EIM_D17__EIM_D17 0x80000000
|
||||
MX51_PAD_EIM_D18__EIM_D18 0x80000000
|
||||
MX51_PAD_EIM_D19__EIM_D19 0x80000000
|
||||
MX51_PAD_EIM_D20__EIM_D20 0x80000000
|
||||
MX51_PAD_EIM_D21__EIM_D21 0x80000000
|
||||
MX51_PAD_EIM_D22__EIM_D22 0x80000000
|
||||
MX51_PAD_EIM_D23__EIM_D23 0x80000000
|
||||
MX51_PAD_EIM_D24__EIM_D24 0x80000000
|
||||
MX51_PAD_EIM_D25__EIM_D25 0x80000000
|
||||
MX51_PAD_EIM_D26__EIM_D26 0x80000000
|
||||
MX51_PAD_EIM_D27__EIM_D27 0x80000000
|
||||
MX51_PAD_EIM_D28__EIM_D28 0x80000000
|
||||
MX51_PAD_EIM_D29__EIM_D29 0x80000000
|
||||
MX51_PAD_EIM_D30__EIM_D30 0x80000000
|
||||
MX51_PAD_EIM_D31__EIM_D31 0x80000000
|
||||
MX51_PAD_EIM_OE__EIM_OE 0x80000000
|
||||
MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000
|
||||
MX51_PAD_EIM_LBA__EIM_LBA 0x80000000
|
||||
MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */
|
||||
>;
|
||||
};
|
||||
pinctrl_weim: weimgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_DA0__EIM_DA0 0x80000000
|
||||
MX51_PAD_EIM_DA1__EIM_DA1 0x80000000
|
||||
MX51_PAD_EIM_DA2__EIM_DA2 0x80000000
|
||||
MX51_PAD_EIM_DA3__EIM_DA3 0x80000000
|
||||
MX51_PAD_EIM_DA4__EIM_DA4 0x80000000
|
||||
MX51_PAD_EIM_DA5__EIM_DA5 0x80000000
|
||||
MX51_PAD_EIM_DA6__EIM_DA6 0x80000000
|
||||
MX51_PAD_EIM_DA7__EIM_DA7 0x80000000
|
||||
MX51_PAD_EIM_DA8__EIM_DA8 0x80000000
|
||||
MX51_PAD_EIM_DA9__EIM_DA9 0x80000000
|
||||
MX51_PAD_EIM_DA10__EIM_DA10 0x80000000
|
||||
MX51_PAD_EIM_DA11__EIM_DA11 0x80000000
|
||||
MX51_PAD_EIM_DA12__EIM_DA12 0x80000000
|
||||
MX51_PAD_EIM_DA13__EIM_DA13 0x80000000
|
||||
MX51_PAD_EIM_DA14__EIM_DA14 0x80000000
|
||||
MX51_PAD_EIM_DA15__EIM_DA15 0x80000000
|
||||
MX51_PAD_EIM_A16__EIM_A16 0x80000000
|
||||
MX51_PAD_EIM_A17__EIM_A17 0x80000000
|
||||
MX51_PAD_EIM_A18__EIM_A18 0x80000000
|
||||
MX51_PAD_EIM_A19__EIM_A19 0x80000000
|
||||
MX51_PAD_EIM_A20__EIM_A20 0x80000000
|
||||
MX51_PAD_EIM_A21__EIM_A21 0x80000000
|
||||
MX51_PAD_EIM_A22__EIM_A22 0x80000000
|
||||
MX51_PAD_EIM_A23__EIM_A23 0x80000000
|
||||
MX51_PAD_EIM_A24__EIM_A24 0x80000000
|
||||
MX51_PAD_EIM_A25__EIM_A25 0x80000000
|
||||
MX51_PAD_EIM_A26__EIM_A26 0x80000000
|
||||
MX51_PAD_EIM_A27__EIM_A27 0x80000000
|
||||
MX51_PAD_EIM_D16__EIM_D16 0x80000000
|
||||
MX51_PAD_EIM_D17__EIM_D17 0x80000000
|
||||
MX51_PAD_EIM_D18__EIM_D18 0x80000000
|
||||
MX51_PAD_EIM_D19__EIM_D19 0x80000000
|
||||
MX51_PAD_EIM_D20__EIM_D20 0x80000000
|
||||
MX51_PAD_EIM_D21__EIM_D21 0x80000000
|
||||
MX51_PAD_EIM_D22__EIM_D22 0x80000000
|
||||
MX51_PAD_EIM_D23__EIM_D23 0x80000000
|
||||
MX51_PAD_EIM_D24__EIM_D24 0x80000000
|
||||
MX51_PAD_EIM_D25__EIM_D25 0x80000000
|
||||
MX51_PAD_EIM_D26__EIM_D26 0x80000000
|
||||
MX51_PAD_EIM_D27__EIM_D27 0x80000000
|
||||
MX51_PAD_EIM_D28__EIM_D28 0x80000000
|
||||
MX51_PAD_EIM_D29__EIM_D29 0x80000000
|
||||
MX51_PAD_EIM_D30__EIM_D30 0x80000000
|
||||
MX51_PAD_EIM_D31__EIM_D31 0x80000000
|
||||
MX51_PAD_EIM_OE__EIM_OE 0x80000000
|
||||
MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000
|
||||
MX51_PAD_EIM_LBA__EIM_LBA 0x80000000
|
||||
MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -44,43 +44,41 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-eukrea {
|
||||
pinctrl_tsc2007_1: tsc2007grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
|
||||
MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
|
||||
>;
|
||||
};
|
||||
pinctrl_tsc2007_1: tsc2007-1-grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
|
||||
MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed
|
||||
MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed
|
||||
MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -112,117 +112,115 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-eukrea {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
pinctrl_can: cangrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */
|
||||
MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */
|
||||
>;
|
||||
};
|
||||
pinctrl_can: cangrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */
|
||||
MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */
|
||||
>;
|
||||
};
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_rtscts: uart3rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_COL4__UART3_RTS 0x1c5
|
||||
MX51_PAD_KEY_COL5__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
pinctrl_uart3_rtscts: uart3rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_COL4__UART3_RTS 0x1c5
|
||||
MX51_PAD_KEY_COL5__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_backlight_1: backlightgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5
|
||||
>;
|
||||
};
|
||||
pinctrl_backlight_1: backlight1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1_cd: esdhc1_cd {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_0__GPIO1_0 0xd5
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1_cd: esdhc1_cdgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_0__GPIO1_0 0xd5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpiokeys_1: gpiokeysgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D9__GPIO3_31 0x1f5
|
||||
>;
|
||||
};
|
||||
pinctrl_gpiokeys_1: gpiokeys1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D9__GPIO3_31 0x1f5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpioled: gpioledgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D10__GPIO3_30 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_gpioled: gpioled1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D10__GPIO3_30 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
|
||||
>;
|
||||
};
|
||||
pinctrl_reg_lcd_3v3: reg_lcd_3v3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
|
||||
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
|
||||
>;
|
||||
};
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
|
||||
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
|
||||
>;
|
||||
};
|
||||
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -399,7 +399,7 @@
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@73fa8000 {
|
||||
iomuxc: pinctrl@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
};
|
||||
|
||||
@ -101,67 +101,65 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-ard {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_1__GPIO1_1 0x80000000
|
||||
MX53_PAD_GPIO_9__GPIO1_9 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_GPIO_10__GPIO4_0 0x80000000
|
||||
MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000
|
||||
MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000
|
||||
MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000
|
||||
MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000
|
||||
MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000
|
||||
MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000
|
||||
MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000
|
||||
MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000
|
||||
MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000
|
||||
MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000
|
||||
MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000
|
||||
MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000
|
||||
MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000
|
||||
MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000
|
||||
MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000
|
||||
MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000
|
||||
MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000
|
||||
MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000
|
||||
MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000
|
||||
MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000
|
||||
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000
|
||||
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000
|
||||
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000
|
||||
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000
|
||||
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000
|
||||
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000
|
||||
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000
|
||||
MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
|
||||
MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
|
||||
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_1__GPIO1_1 0x80000000
|
||||
MX53_PAD_GPIO_9__GPIO1_9 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_GPIO_10__GPIO4_0 0x80000000
|
||||
MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000
|
||||
MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000
|
||||
MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000
|
||||
MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000
|
||||
MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000
|
||||
MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000
|
||||
MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000
|
||||
MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000
|
||||
MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000
|
||||
MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000
|
||||
MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000
|
||||
MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000
|
||||
MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000
|
||||
MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000
|
||||
MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000
|
||||
MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000
|
||||
MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000
|
||||
MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000
|
||||
MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000
|
||||
MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000
|
||||
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000
|
||||
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000
|
||||
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000
|
||||
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000
|
||||
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000
|
||||
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000
|
||||
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000
|
||||
MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
|
||||
MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
|
||||
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
|
||||
MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
|
||||
MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
|
||||
MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
|
||||
MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
|
||||
MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
|
||||
MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -102,38 +102,36 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx53-kp-ddc {
|
||||
pinctrl_disp: dispgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4
|
||||
MX53_PAD_GPIO_1__PWM2_PWMO 0x4
|
||||
>;
|
||||
};
|
||||
pinctrl_disp: dispgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4
|
||||
MX53_PAD_GPIO_1__PWM2_PWMO 0x4
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -98,56 +98,54 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_kp_common>;
|
||||
|
||||
imx53-kp-common {
|
||||
pinctrl_buzzer: buzzergrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_buzzer: buzzergrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpiobuttons: gpiobuttonsgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_RW__GPIO2_26 0x1e4
|
||||
MX53_PAD_EIM_D22__GPIO3_22 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_gpiobuttons: gpiobuttonsgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_RW__GPIO2_26 0x1e4
|
||||
MX53_PAD_EIM_D22__GPIO3_22 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_kp_common: kpcommongrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
|
||||
MX53_PAD_GPIO_19__GPIO4_5 0x1e4
|
||||
MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4
|
||||
MX53_PAD_PATA_DATA7__GPIO2_7 0xe0
|
||||
MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4
|
||||
MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4
|
||||
MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4
|
||||
MX53_PAD_EIM_D17__GPIO3_17 0x1e4
|
||||
MX53_PAD_EIM_D18__GPIO3_18 0x1e4
|
||||
MX53_PAD_EIM_D21__GPIO3_21 0x1e4
|
||||
MX53_PAD_EIM_D29__GPIO3_29 0x1e4
|
||||
MX53_PAD_EIM_DA11__GPIO3_11 0x1e4
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x1e4
|
||||
MX53_PAD_EIM_DA14__GPIO3_14 0x1e4
|
||||
MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4
|
||||
MX53_PAD_SD1_CMD__GPIO1_18 0x1e4
|
||||
MX53_PAD_SD1_CLK__GPIO1_20 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_kp_common: kpcommongrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
|
||||
MX53_PAD_GPIO_19__GPIO4_5 0x1e4
|
||||
MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4
|
||||
MX53_PAD_PATA_DATA7__GPIO2_7 0xe0
|
||||
MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4
|
||||
MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4
|
||||
MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4
|
||||
MX53_PAD_EIM_D17__GPIO3_17 0x1e4
|
||||
MX53_PAD_EIM_D18__GPIO3_18 0x1e4
|
||||
MX53_PAD_EIM_D21__GPIO3_21 0x1e4
|
||||
MX53_PAD_EIM_D29__GPIO3_29 0x1e4
|
||||
MX53_PAD_EIM_DA11__GPIO3_11 0x1e4
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x1e4
|
||||
MX53_PAD_EIM_DA14__GPIO3_14 0x1e4
|
||||
MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4
|
||||
MX53_PAD_SD1_CMD__GPIO1_18 0x1e4
|
||||
MX53_PAD_SD1_CLK__GPIO1_20 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_leds: ledgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_EB2__GPIO2_30 0x1d4
|
||||
MX53_PAD_EIM_D28__GPIO3_28 0x1d4
|
||||
MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4
|
||||
>;
|
||||
};
|
||||
pinctrl_leds: ledgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_EB2__GPIO2_30 0x1d4
|
||||
MX53_PAD_EIM_D28__GPIO3_28 0x1d4
|
||||
MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4
|
||||
MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4
|
||||
MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -77,41 +77,39 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-m53evk {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_nand: nandgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
||||
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
||||
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
||||
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
||||
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
||||
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
||||
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
||||
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
|
||||
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
|
||||
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
|
||||
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
|
||||
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
|
||||
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
|
||||
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
|
||||
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
|
||||
>;
|
||||
};
|
||||
pinctrl_nand: nandgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
||||
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
||||
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
||||
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
||||
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
||||
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
||||
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
||||
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
|
||||
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
|
||||
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
|
||||
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
|
||||
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
|
||||
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
|
||||
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
|
||||
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -156,155 +156,153 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-m53evk {
|
||||
pinctrl_usb: usbgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_2__GPIO1_2 0x80000000
|
||||
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_usb: usbgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_2__GPIO1_2 0x80000000
|
||||
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_4__GPIO1_4 0x000b0
|
||||
>;
|
||||
};
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_4__GPIO1_4 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
led_pin_gpio: led_gpio {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
|
||||
MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
|
||||
>;
|
||||
};
|
||||
led_pin_gpio: ledgpiogrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
|
||||
MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
|
||||
MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
|
||||
MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
|
||||
MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
|
||||
MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
|
||||
MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
|
||||
MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
|
||||
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
|
||||
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can2: can2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
|
||||
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_can2: can2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
|
||||
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
|
||||
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
|
||||
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
|
||||
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
|
||||
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
|
||||
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
|
||||
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
|
||||
MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
|
||||
MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
|
||||
MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
|
||||
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
|
||||
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
|
||||
MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
|
||||
MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
|
||||
MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
|
||||
>;
|
||||
};
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
|
||||
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
|
||||
>;
|
||||
};
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
|
||||
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user