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fsl/fman: don't touch liodn base regs reserved on non-PAMU SoCs
The liodn base registers are specific to PAMU based NXP systems and are reserved on SMMU based ones. Don't access them unless PAMU is compiled in. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -634,6 +634,9 @@ static void set_port_liodn(struct fman *fman, u8 port_id,
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{
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u32 tmp;
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iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]);
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if (!IS_ENABLED(CONFIG_FSL_PAMU))
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return;
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/* set LIODN base for this port */
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tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]);
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if (port_id % 2) {
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@ -644,7 +647,6 @@ static void set_port_liodn(struct fman *fman, u8 port_id,
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tmp |= liodn_base << DMA_LIODN_SHIFT;
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}
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iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]);
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iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]);
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}
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static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
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@ -1942,6 +1944,8 @@ static int fman_init(struct fman *fman)
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fman->liodn_offset[i] =
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ioread32be(&fman->bmi_regs->fmbm_spliodn[i - 1]);
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if (!IS_ENABLED(CONFIG_FSL_PAMU))
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continue;
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liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]);
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if (i % 2) {
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/* FMDM_PLR LSB holds LIODN base for odd ports */
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