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https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-11 12:28:41 +08:00
Merge remote-tracking branches 'spi/fix/fsl-dspi', 'spi/fix/omap2-mcspi', 'spi/fix/pxa2xx' and 'spi/fix/ti-qspi' into spi-linus
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commit
9b1f189e6d
@ -385,8 +385,8 @@ static int dspi_transfer_one_message(struct spi_master *master,
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dspi->cur_chip = spi_get_ctldata(spi);
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dspi->cs = spi->chip_select;
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dspi->cs_change = 0;
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if (dspi->cur_transfer->transfer_list.next
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== &dspi->cur_msg->transfers)
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if (list_is_last(&dspi->cur_transfer->transfer_list,
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&dspi->cur_msg->transfers) || transfer->cs_change)
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dspi->cs_change = 1;
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dspi->void_write_data = dspi->cur_chip->void_write_data;
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@ -423,12 +423,16 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi,
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if (mcspi_dma->dma_tx) {
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struct dma_async_tx_descriptor *tx;
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struct scatterlist sg;
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dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
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xfer->tx_sg.nents, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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sg_init_table(&sg, 1);
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sg_dma_address(&sg) = xfer->tx_dma;
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sg_dma_len(&sg) = xfer->len;
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (tx) {
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tx->callback = omap2_mcspi_tx_callback;
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tx->callback_param = spi;
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@ -474,15 +478,20 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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if (mcspi_dma->dma_rx) {
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struct dma_async_tx_descriptor *tx;
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struct scatterlist sg;
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dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
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if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
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dma_count -= es;
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, xfer->rx_sg.sgl,
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xfer->rx_sg.nents, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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sg_init_table(&sg, 1);
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sg_dma_address(&sg) = xfer->rx_dma;
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sg_dma_len(&sg) = dma_count;
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
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DMA_CTRL_ACK);
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if (tx) {
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tx->callback = omap2_mcspi_rx_callback;
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tx->callback_param = spi;
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@ -496,6 +505,8 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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omap2_mcspi_set_dma_req(spi, 1, 1);
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wait_for_completion(&mcspi_dma->dma_rx_completion);
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dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
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DMA_FROM_DEVICE);
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if (mcspi->fifo_depth > 0)
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return count;
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@ -608,6 +619,8 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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if (tx != NULL) {
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wait_for_completion(&mcspi_dma->dma_tx_completion);
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dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
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DMA_TO_DEVICE);
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if (mcspi->fifo_depth > 0) {
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irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
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@ -1074,16 +1087,6 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
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gpio_free(spi->cs_gpio);
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}
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static bool omap2_mcspi_can_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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if (xfer->len < DMA_MIN_BYTES)
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return false;
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return true;
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}
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static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
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struct spi_device *spi, struct spi_transfer *t)
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{
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@ -1265,6 +1268,32 @@ static int omap2_mcspi_transfer_one(struct spi_master *master,
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return -EINVAL;
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}
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if (len < DMA_MIN_BYTES)
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goto skip_dma_map;
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if (mcspi_dma->dma_tx && tx_buf != NULL) {
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t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
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len, DMA_TO_DEVICE);
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if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
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dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
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'T', len);
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return -EINVAL;
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}
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}
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if (mcspi_dma->dma_rx && rx_buf != NULL) {
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t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
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dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
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'R', len);
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if (tx_buf != NULL)
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dma_unmap_single(mcspi->dev, t->tx_dma,
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len, DMA_TO_DEVICE);
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return -EINVAL;
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}
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}
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skip_dma_map:
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return omap2_mcspi_work_one(mcspi, spi, t);
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}
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@ -1348,7 +1377,6 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
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master->transfer_one = omap2_mcspi_transfer_one;
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master->set_cs = omap2_mcspi_set_cs;
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master->cleanup = omap2_mcspi_cleanup;
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master->can_dma = omap2_mcspi_can_dma;
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master->dev.of_node = node;
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master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
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master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
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@ -126,7 +126,7 @@ static const struct lpss_config lpss_platforms[] = {
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.reg_general = -1,
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.reg_ssp = 0x20,
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.reg_cs_ctrl = 0x24,
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.reg_capabilities = 0xfc,
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.reg_capabilities = -1,
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.rx_threshold = 1,
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.tx_threshold_lo = 32,
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.tx_threshold_hi = 56,
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@ -94,6 +94,7 @@ struct ti_qspi {
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#define QSPI_FLEN(n) ((n - 1) << 0)
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#define QSPI_WLEN_MAX_BITS 128
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#define QSPI_WLEN_MAX_BYTES 16
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#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
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/* STATUS REGISTER */
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#define BUSY 0x01
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@ -235,16 +236,16 @@ static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
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return -ETIMEDOUT;
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}
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static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
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int count)
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{
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int wlen, count, xfer_len;
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int wlen, xfer_len;
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unsigned int cmd;
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const u8 *txbuf;
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u32 data;
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txbuf = t->tx_buf;
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cmd = qspi->cmd | QSPI_WR_SNGL;
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count = t->len;
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wlen = t->bits_per_word >> 3; /* in bytes */
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xfer_len = wlen;
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@ -304,9 +305,10 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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return 0;
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}
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static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
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int count)
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{
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int wlen, count;
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int wlen;
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unsigned int cmd;
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u8 *rxbuf;
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@ -323,7 +325,6 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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cmd |= QSPI_RD_SNGL;
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break;
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}
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count = t->len;
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wlen = t->bits_per_word >> 3; /* in bytes */
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while (count) {
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@ -354,12 +355,13 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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return 0;
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}
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static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
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int count)
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{
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int ret;
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if (t->tx_buf) {
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ret = qspi_write_msg(qspi, t);
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ret = qspi_write_msg(qspi, t, count);
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if (ret) {
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dev_dbg(qspi->dev, "Error while writing\n");
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return ret;
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@ -367,7 +369,7 @@ static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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}
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if (t->rx_buf) {
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ret = qspi_read_msg(qspi, t);
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ret = qspi_read_msg(qspi, t, count);
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if (ret) {
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dev_dbg(qspi->dev, "Error while reading\n");
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return ret;
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@ -450,7 +452,8 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
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struct spi_device *spi = m->spi;
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struct spi_transfer *t;
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int status = 0, ret;
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int frame_length;
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unsigned int frame_len_words, transfer_len_words;
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int wlen;
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/* setup device control reg */
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qspi->dc = 0;
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@ -462,14 +465,15 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
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if (spi->mode & SPI_CS_HIGH)
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qspi->dc |= QSPI_CSPOL(spi->chip_select);
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frame_length = (m->frame_length << 3) / spi->bits_per_word;
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frame_length = clamp(frame_length, 0, QSPI_FRAME);
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frame_len_words = 0;
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list_for_each_entry(t, &m->transfers, transfer_list)
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frame_len_words += t->len / (t->bits_per_word >> 3);
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frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
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/* setup command reg */
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qspi->cmd = 0;
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qspi->cmd |= QSPI_EN_CS(spi->chip_select);
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qspi->cmd |= QSPI_FLEN(frame_length);
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qspi->cmd |= QSPI_FLEN(frame_len_words);
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ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
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@ -479,16 +483,23 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
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ti_qspi_disable_memory_map(spi);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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qspi->cmd |= QSPI_WLEN(t->bits_per_word);
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qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
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QSPI_WLEN(t->bits_per_word));
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ret = qspi_transfer_msg(qspi, t);
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wlen = t->bits_per_word >> 3;
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transfer_len_words = min(t->len / wlen, frame_len_words);
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ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
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if (ret) {
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dev_dbg(qspi->dev, "transfer message failed\n");
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mutex_unlock(&qspi->list_lock);
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return -EINVAL;
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}
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m->actual_length += t->len;
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m->actual_length += transfer_len_words * wlen;
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frame_len_words -= transfer_len_words;
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if (frame_len_words == 0)
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break;
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}
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mutex_unlock(&qspi->list_lock);
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