mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-11 12:28:41 +08:00
Merge remote-tracking branches 'spi/fix/fsl-dspi', 'spi/fix/omap2-mcspi', 'spi/fix/pxa2xx' and 'spi/fix/ti-qspi' into spi-linus
This commit is contained in:
commit
9b1f189e6d
@ -385,8 +385,8 @@ static int dspi_transfer_one_message(struct spi_master *master,
|
|||||||
dspi->cur_chip = spi_get_ctldata(spi);
|
dspi->cur_chip = spi_get_ctldata(spi);
|
||||||
dspi->cs = spi->chip_select;
|
dspi->cs = spi->chip_select;
|
||||||
dspi->cs_change = 0;
|
dspi->cs_change = 0;
|
||||||
if (dspi->cur_transfer->transfer_list.next
|
if (list_is_last(&dspi->cur_transfer->transfer_list,
|
||||||
== &dspi->cur_msg->transfers)
|
&dspi->cur_msg->transfers) || transfer->cs_change)
|
||||||
dspi->cs_change = 1;
|
dspi->cs_change = 1;
|
||||||
dspi->void_write_data = dspi->cur_chip->void_write_data;
|
dspi->void_write_data = dspi->cur_chip->void_write_data;
|
||||||
|
|
||||||
|
@ -423,12 +423,16 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi,
|
|||||||
|
|
||||||
if (mcspi_dma->dma_tx) {
|
if (mcspi_dma->dma_tx) {
|
||||||
struct dma_async_tx_descriptor *tx;
|
struct dma_async_tx_descriptor *tx;
|
||||||
|
struct scatterlist sg;
|
||||||
|
|
||||||
dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
|
dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
|
||||||
|
|
||||||
tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
|
sg_init_table(&sg, 1);
|
||||||
xfer->tx_sg.nents, DMA_MEM_TO_DEV,
|
sg_dma_address(&sg) = xfer->tx_dma;
|
||||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
sg_dma_len(&sg) = xfer->len;
|
||||||
|
|
||||||
|
tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
|
||||||
|
DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||||
if (tx) {
|
if (tx) {
|
||||||
tx->callback = omap2_mcspi_tx_callback;
|
tx->callback = omap2_mcspi_tx_callback;
|
||||||
tx->callback_param = spi;
|
tx->callback_param = spi;
|
||||||
@ -474,15 +478,20 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
|
|||||||
|
|
||||||
if (mcspi_dma->dma_rx) {
|
if (mcspi_dma->dma_rx) {
|
||||||
struct dma_async_tx_descriptor *tx;
|
struct dma_async_tx_descriptor *tx;
|
||||||
|
struct scatterlist sg;
|
||||||
|
|
||||||
dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
|
dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
|
||||||
|
|
||||||
if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
|
if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
|
||||||
dma_count -= es;
|
dma_count -= es;
|
||||||
|
|
||||||
tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, xfer->rx_sg.sgl,
|
sg_init_table(&sg, 1);
|
||||||
xfer->rx_sg.nents, DMA_DEV_TO_MEM,
|
sg_dma_address(&sg) = xfer->rx_dma;
|
||||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
sg_dma_len(&sg) = dma_count;
|
||||||
|
|
||||||
|
tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
|
||||||
|
DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
|
||||||
|
DMA_CTRL_ACK);
|
||||||
if (tx) {
|
if (tx) {
|
||||||
tx->callback = omap2_mcspi_rx_callback;
|
tx->callback = omap2_mcspi_rx_callback;
|
||||||
tx->callback_param = spi;
|
tx->callback_param = spi;
|
||||||
@ -496,6 +505,8 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
|
|||||||
omap2_mcspi_set_dma_req(spi, 1, 1);
|
omap2_mcspi_set_dma_req(spi, 1, 1);
|
||||||
|
|
||||||
wait_for_completion(&mcspi_dma->dma_rx_completion);
|
wait_for_completion(&mcspi_dma->dma_rx_completion);
|
||||||
|
dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
|
||||||
|
DMA_FROM_DEVICE);
|
||||||
|
|
||||||
if (mcspi->fifo_depth > 0)
|
if (mcspi->fifo_depth > 0)
|
||||||
return count;
|
return count;
|
||||||
@ -608,6 +619,8 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
|
|||||||
|
|
||||||
if (tx != NULL) {
|
if (tx != NULL) {
|
||||||
wait_for_completion(&mcspi_dma->dma_tx_completion);
|
wait_for_completion(&mcspi_dma->dma_tx_completion);
|
||||||
|
dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
|
||||||
|
DMA_TO_DEVICE);
|
||||||
|
|
||||||
if (mcspi->fifo_depth > 0) {
|
if (mcspi->fifo_depth > 0) {
|
||||||
irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
|
irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
|
||||||
@ -1074,16 +1087,6 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
|
|||||||
gpio_free(spi->cs_gpio);
|
gpio_free(spi->cs_gpio);
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool omap2_mcspi_can_dma(struct spi_master *master,
|
|
||||||
struct spi_device *spi,
|
|
||||||
struct spi_transfer *xfer)
|
|
||||||
{
|
|
||||||
if (xfer->len < DMA_MIN_BYTES)
|
|
||||||
return false;
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
|
static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
|
||||||
struct spi_device *spi, struct spi_transfer *t)
|
struct spi_device *spi, struct spi_transfer *t)
|
||||||
{
|
{
|
||||||
@ -1265,6 +1268,32 @@ static int omap2_mcspi_transfer_one(struct spi_master *master,
|
|||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (len < DMA_MIN_BYTES)
|
||||||
|
goto skip_dma_map;
|
||||||
|
|
||||||
|
if (mcspi_dma->dma_tx && tx_buf != NULL) {
|
||||||
|
t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
|
||||||
|
len, DMA_TO_DEVICE);
|
||||||
|
if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
|
||||||
|
dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
|
||||||
|
'T', len);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (mcspi_dma->dma_rx && rx_buf != NULL) {
|
||||||
|
t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
|
||||||
|
DMA_FROM_DEVICE);
|
||||||
|
if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
|
||||||
|
dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
|
||||||
|
'R', len);
|
||||||
|
if (tx_buf != NULL)
|
||||||
|
dma_unmap_single(mcspi->dev, t->tx_dma,
|
||||||
|
len, DMA_TO_DEVICE);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
skip_dma_map:
|
||||||
return omap2_mcspi_work_one(mcspi, spi, t);
|
return omap2_mcspi_work_one(mcspi, spi, t);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1348,7 +1377,6 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
|
|||||||
master->transfer_one = omap2_mcspi_transfer_one;
|
master->transfer_one = omap2_mcspi_transfer_one;
|
||||||
master->set_cs = omap2_mcspi_set_cs;
|
master->set_cs = omap2_mcspi_set_cs;
|
||||||
master->cleanup = omap2_mcspi_cleanup;
|
master->cleanup = omap2_mcspi_cleanup;
|
||||||
master->can_dma = omap2_mcspi_can_dma;
|
|
||||||
master->dev.of_node = node;
|
master->dev.of_node = node;
|
||||||
master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
|
master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
|
||||||
master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
|
master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
|
||||||
|
@ -126,7 +126,7 @@ static const struct lpss_config lpss_platforms[] = {
|
|||||||
.reg_general = -1,
|
.reg_general = -1,
|
||||||
.reg_ssp = 0x20,
|
.reg_ssp = 0x20,
|
||||||
.reg_cs_ctrl = 0x24,
|
.reg_cs_ctrl = 0x24,
|
||||||
.reg_capabilities = 0xfc,
|
.reg_capabilities = -1,
|
||||||
.rx_threshold = 1,
|
.rx_threshold = 1,
|
||||||
.tx_threshold_lo = 32,
|
.tx_threshold_lo = 32,
|
||||||
.tx_threshold_hi = 56,
|
.tx_threshold_hi = 56,
|
||||||
|
@ -94,6 +94,7 @@ struct ti_qspi {
|
|||||||
#define QSPI_FLEN(n) ((n - 1) << 0)
|
#define QSPI_FLEN(n) ((n - 1) << 0)
|
||||||
#define QSPI_WLEN_MAX_BITS 128
|
#define QSPI_WLEN_MAX_BITS 128
|
||||||
#define QSPI_WLEN_MAX_BYTES 16
|
#define QSPI_WLEN_MAX_BYTES 16
|
||||||
|
#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
|
||||||
|
|
||||||
/* STATUS REGISTER */
|
/* STATUS REGISTER */
|
||||||
#define BUSY 0x01
|
#define BUSY 0x01
|
||||||
@ -235,16 +236,16 @@ static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
|
|||||||
return -ETIMEDOUT;
|
return -ETIMEDOUT;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
|
||||||
|
int count)
|
||||||
{
|
{
|
||||||
int wlen, count, xfer_len;
|
int wlen, xfer_len;
|
||||||
unsigned int cmd;
|
unsigned int cmd;
|
||||||
const u8 *txbuf;
|
const u8 *txbuf;
|
||||||
u32 data;
|
u32 data;
|
||||||
|
|
||||||
txbuf = t->tx_buf;
|
txbuf = t->tx_buf;
|
||||||
cmd = qspi->cmd | QSPI_WR_SNGL;
|
cmd = qspi->cmd | QSPI_WR_SNGL;
|
||||||
count = t->len;
|
|
||||||
wlen = t->bits_per_word >> 3; /* in bytes */
|
wlen = t->bits_per_word >> 3; /* in bytes */
|
||||||
xfer_len = wlen;
|
xfer_len = wlen;
|
||||||
|
|
||||||
@ -304,9 +305,10 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
|
||||||
|
int count)
|
||||||
{
|
{
|
||||||
int wlen, count;
|
int wlen;
|
||||||
unsigned int cmd;
|
unsigned int cmd;
|
||||||
u8 *rxbuf;
|
u8 *rxbuf;
|
||||||
|
|
||||||
@ -323,7 +325,6 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
|||||||
cmd |= QSPI_RD_SNGL;
|
cmd |= QSPI_RD_SNGL;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
count = t->len;
|
|
||||||
wlen = t->bits_per_word >> 3; /* in bytes */
|
wlen = t->bits_per_word >> 3; /* in bytes */
|
||||||
|
|
||||||
while (count) {
|
while (count) {
|
||||||
@ -354,12 +355,13 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
|
||||||
|
int count)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
if (t->tx_buf) {
|
if (t->tx_buf) {
|
||||||
ret = qspi_write_msg(qspi, t);
|
ret = qspi_write_msg(qspi, t, count);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
dev_dbg(qspi->dev, "Error while writing\n");
|
dev_dbg(qspi->dev, "Error while writing\n");
|
||||||
return ret;
|
return ret;
|
||||||
@ -367,7 +369,7 @@ static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (t->rx_buf) {
|
if (t->rx_buf) {
|
||||||
ret = qspi_read_msg(qspi, t);
|
ret = qspi_read_msg(qspi, t, count);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
dev_dbg(qspi->dev, "Error while reading\n");
|
dev_dbg(qspi->dev, "Error while reading\n");
|
||||||
return ret;
|
return ret;
|
||||||
@ -450,7 +452,8 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
|
|||||||
struct spi_device *spi = m->spi;
|
struct spi_device *spi = m->spi;
|
||||||
struct spi_transfer *t;
|
struct spi_transfer *t;
|
||||||
int status = 0, ret;
|
int status = 0, ret;
|
||||||
int frame_length;
|
unsigned int frame_len_words, transfer_len_words;
|
||||||
|
int wlen;
|
||||||
|
|
||||||
/* setup device control reg */
|
/* setup device control reg */
|
||||||
qspi->dc = 0;
|
qspi->dc = 0;
|
||||||
@ -462,14 +465,15 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
|
|||||||
if (spi->mode & SPI_CS_HIGH)
|
if (spi->mode & SPI_CS_HIGH)
|
||||||
qspi->dc |= QSPI_CSPOL(spi->chip_select);
|
qspi->dc |= QSPI_CSPOL(spi->chip_select);
|
||||||
|
|
||||||
frame_length = (m->frame_length << 3) / spi->bits_per_word;
|
frame_len_words = 0;
|
||||||
|
list_for_each_entry(t, &m->transfers, transfer_list)
|
||||||
frame_length = clamp(frame_length, 0, QSPI_FRAME);
|
frame_len_words += t->len / (t->bits_per_word >> 3);
|
||||||
|
frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
|
||||||
|
|
||||||
/* setup command reg */
|
/* setup command reg */
|
||||||
qspi->cmd = 0;
|
qspi->cmd = 0;
|
||||||
qspi->cmd |= QSPI_EN_CS(spi->chip_select);
|
qspi->cmd |= QSPI_EN_CS(spi->chip_select);
|
||||||
qspi->cmd |= QSPI_FLEN(frame_length);
|
qspi->cmd |= QSPI_FLEN(frame_len_words);
|
||||||
|
|
||||||
ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
|
ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
|
||||||
|
|
||||||
@ -479,16 +483,23 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
|
|||||||
ti_qspi_disable_memory_map(spi);
|
ti_qspi_disable_memory_map(spi);
|
||||||
|
|
||||||
list_for_each_entry(t, &m->transfers, transfer_list) {
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
||||||
qspi->cmd |= QSPI_WLEN(t->bits_per_word);
|
qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
|
||||||
|
QSPI_WLEN(t->bits_per_word));
|
||||||
|
|
||||||
ret = qspi_transfer_msg(qspi, t);
|
wlen = t->bits_per_word >> 3;
|
||||||
|
transfer_len_words = min(t->len / wlen, frame_len_words);
|
||||||
|
|
||||||
|
ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
dev_dbg(qspi->dev, "transfer message failed\n");
|
dev_dbg(qspi->dev, "transfer message failed\n");
|
||||||
mutex_unlock(&qspi->list_lock);
|
mutex_unlock(&qspi->list_lock);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
m->actual_length += t->len;
|
m->actual_length += transfer_len_words * wlen;
|
||||||
|
frame_len_words -= transfer_len_words;
|
||||||
|
if (frame_len_words == 0)
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
mutex_unlock(&qspi->list_lock);
|
mutex_unlock(&qspi->list_lock);
|
||||||
|
Loading…
Reference in New Issue
Block a user