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arm64: dts: imx8: add basic mipi subsystem
Add basic mipi subsystem for imx8qm and imx8qxp. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li
Shawn Guo
parent
cb53240c04
commit
9b0a5fac03
129
arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
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129
arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
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// SPDX-License-Identifier: GPL-2.0-only and MIT
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/*
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* Copyright 2024 NXP
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*/
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mipi0_subsys: bus@56220000 {
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compatible = "simple-bus";
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interrupt-parent = <&irqsteer_mipi0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x56220000 0x0 0x56220000 0x10000>;
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irqsteer_mipi0: interrupt-controller@56220000 {
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compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
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reg = <0x56220000 0x1000>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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};
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mipi0_lis_lpcg: clock-controller@56223000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223000 0x4>;
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#clock-cells = <1>;
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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};
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mipi0_pwm_lpcg: clock-controller@5622300c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5622300c 0x4>;
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#clock-cells = <1>;
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power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
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};
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mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223014 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
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};
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mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223018 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
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};
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mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5622301c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi0_i2c0_lpcg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
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};
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mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223024 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
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};
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mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223028 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
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};
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mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5622302c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi0_i2c1_lpcg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
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};
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pwm_mipi0: pwm@56224000 {
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compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
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reg = <0x56224000 0x1000>;
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clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
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<&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "per";
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assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <3>;
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power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
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status = "disabled";
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};
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i2c0_mipi0: i2c@56226000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x56226000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8>;
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clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
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<&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
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clock-names = "per", "ipg";
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assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
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status = "disabled";
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};
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};
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138
arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
Normal file
138
arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
Normal file
@ -0,0 +1,138 @@
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// SPDX-License-Identifier: GPL-2.0-only and MIT
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/*
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* Copyright 2024 NXP
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*/
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mipi1_subsys: bus@57220000 {
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compatible = "simple-bus";
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interrupt-parent = <&irqsteer_mipi1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x57220000 0x0 0x57220000 0x10000>;
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irqsteer_mipi1: interrupt-controller@57220000 {
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compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
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reg = <0x57220000 0x1000>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_MIPI_1>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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};
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mipi1_lis_lpcg: clock-controller@57223000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223000 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi1_lis_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1>;
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};
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mipi1_pwm_lpcg: clock-controller@5722300c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5722300c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
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<&dsi_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "mipi1_pwm_lpcg_clk",
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"mipi1_pwm_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
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};
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mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5722301c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi1_i2c0_lpcg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
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};
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mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223014 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
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};
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mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223018 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
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};
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mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223024 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
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};
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mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223028 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
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};
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mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5722302c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "mipi1_i2c1_lpcg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
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};
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pwm_mipi1: pwm@57224000 {
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compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
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reg = <0x57224000 0x1000>;
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clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
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<&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "per";
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assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <3>;
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power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
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status = "disabled";
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};
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i2c0_mipi1: i2c@57226000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x57226000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8>;
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interrupt-parent = <&irqsteer_mipi1>;
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clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
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<&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
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clock-names = "per", "ipg";
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assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
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status = "disabled";
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};
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};
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