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spi: add support for microchip fpga spi controllers
Add a driver for Microchip FPGA SPI controllers, specifically supporting the "hard" controllers on PolarFire SoC. Co-developed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220607073833.2331539-2-conor.dooley@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Conor Dooley
Mark Brown
parent
6ff40f00e5
commit
9ac8d17694
@ -575,6 +575,15 @@ config SPI_MESON_SPIFC
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This enables master mode support for the SPIFC (SPI flash
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This enables master mode support for the SPIFC (SPI flash
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controller) available in Amlogic Meson SoCs.
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controller) available in Amlogic Meson SoCs.
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config SPI_MICROCHIP_CORE
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tristate "Microchip FPGA SPI controllers"
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depends on SPI_MASTER
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help
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This enables the SPI driver for Microchip FPGA SPI controllers.
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Say Y or M here if you want to use the "hard" controllers on
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PolarFire SoC.
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If built as a module, it will be called spi-microchip-core.
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config SPI_MT65XX
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config SPI_MT65XX
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tristate "MediaTek SPI controller"
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tristate "MediaTek SPI controller"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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depends on ARCH_MEDIATEK || COMPILE_TEST
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@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
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obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o
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obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o
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obj-$(CONFIG_SPI_MESON_SPICC) += spi-meson-spicc.o
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obj-$(CONFIG_SPI_MESON_SPICC) += spi-meson-spicc.o
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obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o
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obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o
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obj-$(CONFIG_SPI_MICROCHIP_CORE) += spi-microchip-core.o
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obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
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obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
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obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
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obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
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632
drivers/spi/spi-microchip-core.c
Normal file
632
drivers/spi/spi-microchip-core.c
Normal file
@ -0,0 +1,632 @@
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* Microchip CoreSPI SPI controller driver
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*
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* Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Daire McNamara <daire.mcnamara@microchip.com>
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#define MAX_LEN (0xffff)
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#define MAX_CS (8)
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#define DEFAULT_FRAMESIZE (8)
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#define FIFO_DEPTH (32)
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#define CLK_GEN_MODE1_MAX (255)
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#define CLK_GEN_MODE0_MAX (15)
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#define CLK_GEN_MIN (0)
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#define MODE_X_MASK_SHIFT (24)
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#define CONTROL_ENABLE BIT(0)
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#define CONTROL_MASTER BIT(1)
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#define CONTROL_RX_DATA_INT BIT(4)
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#define CONTROL_TX_DATA_INT BIT(5)
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#define CONTROL_RX_OVER_INT BIT(6)
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#define CONTROL_TX_UNDER_INT BIT(7)
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#define CONTROL_SPO BIT(24)
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#define CONTROL_SPH BIT(25)
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#define CONTROL_SPS BIT(26)
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#define CONTROL_FRAMEURUN BIT(27)
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#define CONTROL_CLKMODE BIT(28)
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#define CONTROL_BIGFIFO BIT(29)
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#define CONTROL_OENOFF BIT(30)
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#define CONTROL_RESET BIT(31)
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#define CONTROL_MODE_MASK GENMASK(3, 2)
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#define MOTOROLA_MODE (0)
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#define CONTROL_FRAMECNT_MASK GENMASK(23, 8)
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#define CONTROL_FRAMECNT_SHIFT (8)
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#define STATUS_ACTIVE BIT(14)
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#define STATUS_SSEL BIT(13)
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#define STATUS_FRAMESTART BIT(12)
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#define STATUS_TXFIFO_EMPTY_NEXT_READ BIT(11)
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#define STATUS_TXFIFO_EMPTY BIT(10)
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#define STATUS_TXFIFO_FULL_NEXT_WRITE BIT(9)
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#define STATUS_TXFIFO_FULL BIT(8)
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#define STATUS_RXFIFO_EMPTY_NEXT_READ BIT(7)
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#define STATUS_RXFIFO_EMPTY BIT(6)
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#define STATUS_RXFIFO_FULL_NEXT_WRITE BIT(5)
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#define STATUS_RXFIFO_FULL BIT(4)
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#define STATUS_TX_UNDERRUN BIT(3)
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#define STATUS_RX_OVERFLOW BIT(2)
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#define STATUS_RXDAT_RXED BIT(1)
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#define STATUS_TXDAT_SENT BIT(0)
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#define INT_TXDONE BIT(0)
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#define INT_RXRDY BIT(1)
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#define INT_RX_CHANNEL_OVERFLOW BIT(2)
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#define INT_TX_CHANNEL_UNDERRUN BIT(3)
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#define INT_ENABLE_MASK (CONTROL_RX_DATA_INT | CONTROL_TX_DATA_INT | \
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CONTROL_RX_OVER_INT | CONTROL_TX_UNDER_INT)
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#define REG_CONTROL (0x00)
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#define REG_FRAME_SIZE (0x04)
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#define REG_STATUS (0x08)
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#define REG_INT_CLEAR (0x0c)
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#define REG_RX_DATA (0x10)
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#define REG_TX_DATA (0x14)
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#define REG_CLK_GEN (0x18)
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#define REG_SLAVE_SELECT (0x1c)
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#define SSEL_MASK GENMASK(7, 0)
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#define SSEL_DIRECT BIT(8)
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#define SSELOUT_SHIFT 9
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#define SSELOUT BIT(SSELOUT_SHIFT)
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#define REG_MIS (0x20)
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#define REG_RIS (0x24)
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#define REG_CONTROL2 (0x28)
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#define REG_COMMAND (0x2c)
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#define REG_PKTSIZE (0x30)
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#define REG_CMD_SIZE (0x34)
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#define REG_HWSTATUS (0x38)
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#define REG_STAT8 (0x3c)
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#define REG_CTRL2 (0x48)
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#define REG_FRAMESUP (0x50)
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struct mchp_corespi {
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void __iomem *regs;
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struct clk *clk;
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const u8 *tx_buf;
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u8 *rx_buf;
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u32 clk_gen; /* divider for spi output clock generated by the controller */
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u32 clk_mode;
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int irq;
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int tx_len;
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int rx_len;
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int pending;
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};
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static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg)
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{
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return readl(spi->regs + reg);
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}
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static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val)
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{
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writel(val, spi->regs + reg);
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}
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static inline void mchp_corespi_enable(struct mchp_corespi *spi)
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{
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u32 control = mchp_corespi_read(spi, REG_CONTROL);
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control |= CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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static inline void mchp_corespi_disable(struct mchp_corespi *spi)
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{
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u32 control = mchp_corespi_read(spi, REG_CONTROL);
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control &= ~CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi)
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{
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u8 data;
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int fifo_max, i = 0;
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fifo_max = min(spi->rx_len, FIFO_DEPTH);
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while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) {
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data = mchp_corespi_read(spi, REG_RX_DATA);
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if (spi->rx_buf)
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*spi->rx_buf++ = data;
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i++;
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}
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spi->rx_len -= i;
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spi->pending -= i;
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}
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static void mchp_corespi_enable_ints(struct mchp_corespi *spi)
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{
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u32 control, mask = INT_ENABLE_MASK;
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mchp_corespi_disable(spi);
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control = mchp_corespi_read(spi, REG_CONTROL);
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control |= mask;
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mchp_corespi_write(spi, REG_CONTROL, control);
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control |= CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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static void mchp_corespi_disable_ints(struct mchp_corespi *spi)
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{
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u32 control, mask = INT_ENABLE_MASK;
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mchp_corespi_disable(spi);
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control = mchp_corespi_read(spi, REG_CONTROL);
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control &= ~mask;
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mchp_corespi_write(spi, REG_CONTROL, control);
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control |= CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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static inline void mchp_corespi_set_xfer_size(struct mchp_corespi *spi, int len)
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{
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u32 control;
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u16 lenpart;
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/*
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* Disable the SPI controller. Writes to transfer length have
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* no effect when the controller is enabled.
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*/
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mchp_corespi_disable(spi);
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/*
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* The lower 16 bits of the frame count are stored in the control reg
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* for legacy reasons, but the upper 16 written to a different register:
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* FRAMESUP. While both the upper and lower bits can be *READ* from the
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* FRAMESUP register, writing to the lower 16 bits is a NOP
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*/
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lenpart = len & 0xffff;
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control = mchp_corespi_read(spi, REG_CONTROL);
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control &= ~CONTROL_FRAMECNT_MASK;
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control |= lenpart << CONTROL_FRAMECNT_SHIFT;
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mchp_corespi_write(spi, REG_CONTROL, control);
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lenpart = len & 0xffff0000;
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mchp_corespi_write(spi, REG_FRAMESUP, lenpart);
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control |= CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi)
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{
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u8 byte;
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int fifo_max, i = 0;
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fifo_max = min(spi->tx_len, FIFO_DEPTH);
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mchp_corespi_set_xfer_size(spi, fifo_max);
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while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) {
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byte = spi->tx_buf ? *spi->tx_buf++ : 0xaa;
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mchp_corespi_write(spi, REG_TX_DATA, byte);
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i++;
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}
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spi->tx_len -= i;
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spi->pending += i;
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}
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static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt)
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{
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u32 control;
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/*
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* Disable the SPI controller. Writes to the frame size have
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* no effect when the controller is enabled.
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*/
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mchp_corespi_disable(spi);
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mchp_corespi_write(spi, REG_FRAME_SIZE, bt);
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control = mchp_corespi_read(spi, REG_CONTROL);
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control |= CONTROL_ENABLE;
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mchp_corespi_write(spi, REG_CONTROL, control);
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}
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static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
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{
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u32 reg;
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struct mchp_corespi *corespi = spi_master_get_devdata(spi->master);
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reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
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reg &= ~BIT(spi->chip_select);
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reg |= !disable << spi->chip_select;
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mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
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}
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static int mchp_corespi_setup(struct spi_device *spi)
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{
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struct mchp_corespi *corespi = spi_master_get_devdata(spi->master);
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u32 reg;
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/*
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* Active high slaves need to be specifically set to their inactive
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* states during probe by adding them to the "control group" & thus
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* driving their select line low.
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*/
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if (spi->mode & SPI_CS_HIGH) {
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reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
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reg |= BIT(spi->chip_select);
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mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
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}
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return 0;
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}
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static void mchp_corespi_init(struct spi_master *master, struct mchp_corespi *spi)
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{
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unsigned long clk_hz;
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u32 control = mchp_corespi_read(spi, REG_CONTROL);
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control |= CONTROL_MASTER;
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control &= ~CONTROL_MODE_MASK;
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control |= MOTOROLA_MODE;
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mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
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/* max. possible spi clock rate is the apb clock rate */
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clk_hz = clk_get_rate(spi->clk);
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master->max_speed_hz = clk_hz;
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/*
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* The controller must be configured so that it doesn't remove Chip
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* Select until the entire message has been transferred, even if at
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* some points TX FIFO becomes empty.
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*
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* BIGFIFO mode is also enabled, which sets the fifo depth to 32 frames
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* for the 8 bit transfers that this driver uses.
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*/
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control = mchp_corespi_read(spi, REG_CONTROL);
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control |= CONTROL_SPS | CONTROL_BIGFIFO;
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mchp_corespi_write(spi, REG_CONTROL, control);
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mchp_corespi_enable_ints(spi);
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/*
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* It is required to enable direct mode, otherwise control over the chip
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* select is relinquished to the hardware. SSELOUT is enabled too so we
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* can deal with active high slaves.
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*/
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||||||
|
mchp_corespi_write(spi, REG_SLAVE_SELECT, SSELOUT | SSEL_DIRECT);
|
||||||
|
|
||||||
|
control = mchp_corespi_read(spi, REG_CONTROL);
|
||||||
|
|
||||||
|
control &= ~CONTROL_RESET;
|
||||||
|
control |= CONTROL_ENABLE;
|
||||||
|
|
||||||
|
mchp_corespi_write(spi, REG_CONTROL, control);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi)
|
||||||
|
{
|
||||||
|
u32 control;
|
||||||
|
|
||||||
|
mchp_corespi_disable(spi);
|
||||||
|
|
||||||
|
control = mchp_corespi_read(spi, REG_CONTROL);
|
||||||
|
if (spi->clk_mode)
|
||||||
|
control |= CONTROL_CLKMODE;
|
||||||
|
else
|
||||||
|
control &= ~CONTROL_CLKMODE;
|
||||||
|
|
||||||
|
mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen);
|
||||||
|
mchp_corespi_write(spi, REG_CONTROL, control);
|
||||||
|
mchp_corespi_write(spi, REG_CONTROL, control | CONTROL_ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int mode)
|
||||||
|
{
|
||||||
|
u32 control, mode_val;
|
||||||
|
|
||||||
|
switch (mode & SPI_MODE_X_MASK) {
|
||||||
|
case SPI_MODE_0:
|
||||||
|
mode_val = 0;
|
||||||
|
break;
|
||||||
|
case SPI_MODE_1:
|
||||||
|
mode_val = CONTROL_SPH;
|
||||||
|
break;
|
||||||
|
case SPI_MODE_2:
|
||||||
|
mode_val = CONTROL_SPO;
|
||||||
|
break;
|
||||||
|
case SPI_MODE_3:
|
||||||
|
mode_val = CONTROL_SPH | CONTROL_SPO;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Disable the SPI controller. Writes to the frame size have
|
||||||
|
* no effect when the controller is enabled.
|
||||||
|
*/
|
||||||
|
mchp_corespi_disable(spi);
|
||||||
|
|
||||||
|
control = mchp_corespi_read(spi, REG_CONTROL);
|
||||||
|
control &= ~(SPI_MODE_X_MASK << MODE_X_MASK_SHIFT);
|
||||||
|
control |= mode_val;
|
||||||
|
|
||||||
|
mchp_corespi_write(spi, REG_CONTROL, control);
|
||||||
|
|
||||||
|
control |= CONTROL_ENABLE;
|
||||||
|
mchp_corespi_write(spi, REG_CONTROL, control);
|
||||||
|
}
|
||||||
|
|
||||||
|
static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
|
||||||
|
{
|
||||||
|
struct spi_master *master = dev_id;
|
||||||
|
struct mchp_corespi *spi = spi_master_get_devdata(master);
|
||||||
|
u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf;
|
||||||
|
bool finalise = false;
|
||||||
|
|
||||||
|
/* Interrupt line may be shared and not for us at all */
|
||||||
|
if (intfield == 0)
|
||||||
|
return IRQ_NONE;
|
||||||
|
|
||||||
|
if (intfield & INT_TXDONE) {
|
||||||
|
mchp_corespi_write(spi, REG_INT_CLEAR, INT_TXDONE);
|
||||||
|
|
||||||
|
if (spi->rx_len)
|
||||||
|
mchp_corespi_read_fifo(spi);
|
||||||
|
|
||||||
|
if (spi->tx_len)
|
||||||
|
mchp_corespi_write_fifo(spi);
|
||||||
|
|
||||||
|
if (!spi->rx_len)
|
||||||
|
finalise = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (intfield & INT_RXRDY)
|
||||||
|
mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY);
|
||||||
|
|
||||||
|
if (intfield & INT_RX_CHANNEL_OVERFLOW) {
|
||||||
|
mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW);
|
||||||
|
finalise = true;
|
||||||
|
dev_err(&master->dev,
|
||||||
|
"%s: RX OVERFLOW: rxlen: %d, txlen: %d\n", __func__,
|
||||||
|
spi->rx_len, spi->tx_len);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (intfield & INT_TX_CHANNEL_UNDERRUN) {
|
||||||
|
mchp_corespi_write(spi, REG_INT_CLEAR, INT_TX_CHANNEL_UNDERRUN);
|
||||||
|
finalise = true;
|
||||||
|
dev_err(&master->dev,
|
||||||
|
"%s: TX UNDERFLOW: rxlen: %d, txlen: %d\n", __func__,
|
||||||
|
spi->rx_len, spi->tx_len);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (finalise)
|
||||||
|
spi_finalize_current_transfer(master);
|
||||||
|
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mchp_corespi_calculate_clkgen(struct mchp_corespi *spi,
|
||||||
|
unsigned long target_hz)
|
||||||
|
{
|
||||||
|
unsigned long clk_hz, spi_hz, clk_gen;
|
||||||
|
|
||||||
|
clk_hz = clk_get_rate(spi->clk);
|
||||||
|
spi_hz = min(target_hz, clk_hz);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* There are two possible clock modes for the controller generated
|
||||||
|
* clock's division ratio:
|
||||||
|
* CLK_MODE = 0: 1 / (2^(CLK_GEN + 1)) where CLK_GEN = 0 to 15.
|
||||||
|
* CLK_MODE = 1: 1 / (2 * CLK_GEN + 1) where CLK_GEN = 0 to 255.
|
||||||
|
* First try mode 1, fall back to 0 and if we have tried both modes and
|
||||||
|
* we /still/ can't get a good setting, we then throw the toys out of
|
||||||
|
* the pram and give up
|
||||||
|
* clk_gen is the register name for the clock divider on MPFS.
|
||||||
|
*/
|
||||||
|
clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
|
||||||
|
if (clk_gen > CLK_GEN_MODE1_MAX || clk_gen <= CLK_GEN_MIN) {
|
||||||
|
clk_gen = DIV_ROUND_UP(clk_hz, spi_hz);
|
||||||
|
clk_gen = fls(clk_gen) - 1;
|
||||||
|
|
||||||
|
if (clk_gen > CLK_GEN_MODE0_MAX)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
spi->clk_mode = 0;
|
||||||
|
} else {
|
||||||
|
spi->clk_mode = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
spi->clk_gen = clk_gen;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mchp_corespi_transfer_one(struct spi_master *master,
|
||||||
|
struct spi_device *spi_dev,
|
||||||
|
struct spi_transfer *xfer)
|
||||||
|
{
|
||||||
|
struct mchp_corespi *spi = spi_master_get_devdata(master);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&master->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
mchp_corespi_set_clk_gen(spi);
|
||||||
|
|
||||||
|
spi->tx_buf = xfer->tx_buf;
|
||||||
|
spi->rx_buf = xfer->rx_buf;
|
||||||
|
spi->tx_len = xfer->len;
|
||||||
|
spi->rx_len = xfer->len;
|
||||||
|
spi->pending = 0;
|
||||||
|
|
||||||
|
mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)
|
||||||
|
? FIFO_DEPTH : spi->tx_len);
|
||||||
|
|
||||||
|
if (spi->tx_len)
|
||||||
|
mchp_corespi_write_fifo(spi);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mchp_corespi_prepare_message(struct spi_master *master,
|
||||||
|
struct spi_message *msg)
|
||||||
|
{
|
||||||
|
struct spi_device *spi_dev = msg->spi;
|
||||||
|
struct mchp_corespi *spi = spi_master_get_devdata(master);
|
||||||
|
|
||||||
|
mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
|
||||||
|
mchp_corespi_set_mode(spi, spi_dev->mode);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mchp_corespi_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct spi_master *master;
|
||||||
|
struct mchp_corespi *spi;
|
||||||
|
struct resource *res;
|
||||||
|
u32 num_cs;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
master = spi_alloc_master(&pdev->dev, sizeof(*spi));
|
||||||
|
if (!master)
|
||||||
|
return dev_err_probe(&pdev->dev, -ENOMEM,
|
||||||
|
"unable to allocate master for SPI controller\n");
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, master);
|
||||||
|
|
||||||
|
if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))
|
||||||
|
num_cs = MAX_CS;
|
||||||
|
|
||||||
|
master->num_chipselect = num_cs;
|
||||||
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
||||||
|
master->setup = mchp_corespi_setup;
|
||||||
|
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||||
|
master->transfer_one = mchp_corespi_transfer_one;
|
||||||
|
master->prepare_message = mchp_corespi_prepare_message;
|
||||||
|
master->set_cs = mchp_corespi_set_cs;
|
||||||
|
master->dev.of_node = pdev->dev.of_node;
|
||||||
|
|
||||||
|
spi = spi_master_get_devdata(master);
|
||||||
|
|
||||||
|
spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
||||||
|
if (IS_ERR(spi->regs)) {
|
||||||
|
ret = PTR_ERR(spi->regs);
|
||||||
|
goto error_release_master;
|
||||||
|
}
|
||||||
|
|
||||||
|
spi->irq = platform_get_irq(pdev, 0);
|
||||||
|
if (spi->irq <= 0) {
|
||||||
|
dev_err(&pdev->dev, "invalid IRQ %d for SPI controller\n", spi->irq);
|
||||||
|
ret = spi->irq;
|
||||||
|
goto error_release_master;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,
|
||||||
|
IRQF_SHARED, dev_name(&pdev->dev), master);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "could not request irq: %d\n", ret);
|
||||||
|
goto error_release_master;
|
||||||
|
}
|
||||||
|
|
||||||
|
spi->clk = devm_clk_get(&pdev->dev, NULL);
|
||||||
|
if (!spi->clk || IS_ERR(spi->clk)) {
|
||||||
|
ret = PTR_ERR(spi->clk);
|
||||||
|
dev_err(&pdev->dev, "could not get clk: %d\n", ret);
|
||||||
|
goto error_release_master;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = clk_prepare_enable(spi->clk);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "failed to enable clock\n");
|
||||||
|
goto error_release_master;
|
||||||
|
}
|
||||||
|
|
||||||
|
mchp_corespi_init(master, spi);
|
||||||
|
|
||||||
|
ret = devm_spi_register_master(&pdev->dev, master);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev,
|
||||||
|
"unable to register master for SPI controller\n");
|
||||||
|
goto error_release_hardware;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev_info(&pdev->dev, "Registered SPI controller %d\n", master->bus_num);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
error_release_hardware:
|
||||||
|
mchp_corespi_disable(spi);
|
||||||
|
clk_prepare_enable(spi->clk);
|
||||||
|
error_release_master:
|
||||||
|
spi_master_put(master);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mchp_corespi_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct spi_master *master = platform_get_drvdata(pdev);
|
||||||
|
struct mchp_corespi *spi = spi_master_get_devdata(master);
|
||||||
|
|
||||||
|
mchp_corespi_disable_ints(spi);
|
||||||
|
spi_unregister_master(master);
|
||||||
|
spi_master_put(master);
|
||||||
|
clk_disable_unprepare(spi->clk);
|
||||||
|
mchp_corespi_disable(spi);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define MICROCHIP_SPI_PM_OPS (NULL)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Platform driver data structure
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(CONFIG_OF)
|
||||||
|
static const struct of_device_id mchp_corespi_dt_ids[] = {
|
||||||
|
{ .compatible = "microchip,mpfs-spi" },
|
||||||
|
{ /* sentinel */ }
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, mchp_corespi_dt_ids);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static struct platform_driver mchp_corespi_driver = {
|
||||||
|
.probe = mchp_corespi_probe,
|
||||||
|
.driver = {
|
||||||
|
.name = "microchip-corespi",
|
||||||
|
.pm = MICROCHIP_SPI_PM_OPS,
|
||||||
|
.of_match_table = of_match_ptr(mchp_corespi_dt_ids),
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
},
|
||||||
|
.remove = mchp_corespi_remove,
|
||||||
|
};
|
||||||
|
module_platform_driver(mchp_corespi_driver);
|
||||||
|
MODULE_DESCRIPTION("Microchip coreSPI SPI controller driver");
|
||||||
|
MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
|
||||||
|
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
Loading…
Reference in New Issue
Block a user