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drm/exynos: decon: clean up interface type
This patch cleans up interface type relevant codes. Trigger mode is determinded only by i80 mode, which isn't related to Display types - HDMI or Display controller. So this patch makes the trigger mode to be set only in case of i80 mode - For DECON-TV, HW Trigger mode is flaged mandatorily because HDMI Timing Generator generates VSYNC signal which works as a hardware trigger. Changelog v2. - If interface type is HDMI then set out_type to I80. - fix compile warning. Signed-off-by: Inki Dae <inki.dae@samsung.com>
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a6f75aa161
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@ -28,6 +28,10 @@
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#define WINDOWS_NR 3
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#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
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#define IFTYPE_I80 (1 << 0)
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#define I80_HW_TRG (1 << 1)
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#define IFTYPE_HDMI (1 << 2)
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static const char * const decon_clks_name[] = {
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"pclk",
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"aclk_decon",
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@ -38,12 +42,6 @@ static const char * const decon_clks_name[] = {
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"sclk_decon_eclk",
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};
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enum decon_iftype {
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IFTYPE_RGB,
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IFTYPE_I80,
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IFTYPE_HDMI
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};
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enum decon_flag_bits {
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BIT_CLKS_ENABLED,
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BIT_IRQS_ENABLED,
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@ -61,7 +59,7 @@ struct decon_context {
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struct clk *clks[ARRAY_SIZE(decon_clks_name)];
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int pipe;
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unsigned long flags;
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enum decon_iftype out_type;
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unsigned long out_type;
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int first_win;
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};
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@ -95,7 +93,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
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if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
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val = VIDINTCON0_INTEN;
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if (ctx->out_type == IFTYPE_I80)
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if (ctx->out_type & IFTYPE_I80)
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val |= VIDINTCON0_FRAMEDONE;
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else
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val |= VIDINTCON0_INTFRMEN;
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@ -119,7 +117,7 @@ static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
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static void decon_setup_trigger(struct decon_context *ctx)
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{
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u32 val = (ctx->out_type != IFTYPE_HDMI)
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u32 val = !(ctx->out_type & I80_HW_TRG)
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? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
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TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
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: TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
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@ -136,7 +134,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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if (ctx->out_type == IFTYPE_HDMI) {
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if (ctx->out_type & IFTYPE_HDMI) {
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m->crtc_hsync_start = m->crtc_hdisplay + 10;
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m->crtc_hsync_end = m->crtc_htotal - 92;
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m->crtc_vsync_start = m->crtc_vdisplay + 1;
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@ -151,17 +149,20 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
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/* lcd on and use command if */
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val = VIDOUT_LCD_ON;
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if (ctx->out_type == IFTYPE_I80)
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if (ctx->out_type & IFTYPE_I80) {
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val |= VIDOUT_COMMAND_IF;
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else
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decon_setup_trigger(ctx);
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} else {
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val |= VIDOUT_RGB_IF;
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}
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writel(val, ctx->addr + DECON_VIDOUTCON0);
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val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
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VIDTCON2_HOZVAL(m->hdisplay - 1);
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writel(val, ctx->addr + DECON_VIDTCON2);
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if (ctx->out_type != IFTYPE_I80) {
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if (!(ctx->out_type & IFTYPE_I80)) {
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val = VIDTCON00_VBPD_F(
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m->crtc_vtotal - m->crtc_vsync_end - 1) |
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VIDTCON00_VFPD_F(
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@ -183,8 +184,6 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
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writel(val, ctx->addr + DECON_VIDTCON11);
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}
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decon_setup_trigger(ctx);
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/* enable output and display signal */
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decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
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@ -302,7 +301,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
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val = dma_addr + pitch * state->src.h;
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writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
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if (ctx->out_type != IFTYPE_HDMI)
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if (!(ctx->out_type & IFTYPE_HDMI))
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val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
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| BIT_VAL(state->crtc.w * bpp, 13, 0);
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else
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@ -342,7 +341,7 @@ static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
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/* standalone update */
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decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
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if (ctx->out_type == IFTYPE_I80)
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if (ctx->out_type & IFTYPE_I80)
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set_bit(BIT_WIN_UPDATED, &ctx->flags);
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}
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@ -368,7 +367,7 @@ static void decon_swreset(struct decon_context *ctx)
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WARN(tries == 0, "failed to software reset DECON\n");
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if (ctx->out_type != IFTYPE_HDMI)
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if (!(ctx->out_type & IFTYPE_HDMI))
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return;
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writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
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@ -377,7 +376,9 @@ static void decon_swreset(struct decon_context *ctx)
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writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
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writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
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ctx->addr + DECON_CRCCTRL);
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decon_setup_trigger(ctx);
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if (ctx->out_type & IFTYPE_I80)
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decon_setup_trigger(ctx);
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}
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static void decon_enable(struct exynos_drm_crtc *crtc)
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@ -511,7 +512,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
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}
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exynos_plane = &ctx->planes[ctx->first_win];
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out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
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out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
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: EXYNOS_DISPLAY_TYPE_LCD;
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ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
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ctx->pipe, out_type,
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@ -619,11 +620,11 @@ static const struct dev_pm_ops exynos5433_decon_pm_ops = {
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static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
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{
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.compatible = "samsung,exynos5433-decon",
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.data = (void *)IFTYPE_RGB
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.data = (void *)I80_HW_TRG
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},
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{
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.compatible = "samsung,exynos5433-decon-tv",
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.data = (void *)IFTYPE_HDMI
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.data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
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},
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{},
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};
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@ -643,12 +644,14 @@ static int exynos5433_decon_probe(struct platform_device *pdev)
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__set_bit(BIT_SUSPENDED, &ctx->flags);
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ctx->dev = dev;
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ctx->out_type = (enum decon_iftype)of_device_get_match_data(dev);
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ctx->out_type = (unsigned long)of_device_get_match_data(dev);
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if (ctx->out_type == IFTYPE_HDMI)
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if (ctx->out_type & IFTYPE_HDMI) {
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ctx->first_win = 1;
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else if (of_get_child_by_name(dev->of_node, "i80-if-timings"))
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ctx->out_type = IFTYPE_I80;
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} else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
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ctx->out_type = IFTYPE_I80;
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}
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for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
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struct clk *clk;
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@ -673,7 +676,7 @@ static int exynos5433_decon_probe(struct platform_device *pdev)
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
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(ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync");
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(ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
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if (!res) {
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dev_err(dev, "cannot find IRQ resource\n");
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return -ENXIO;
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