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sh: Drop CPU subtype IRQ headers.
This drops the various IRQ headers that were floating around and primarily providing hardcoded IRQ definitions for the various CPU subtypes. This quickly got to be an unmaintainable mess, made even more evident by the subtle breakage introduced by the SH-2 and SH-2A changes. Now that subtypes are able to register IRQ maps directly, just rip all of the headers out. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
417528a2e3
commit
9a7ef6d59f
@ -10,6 +10,7 @@
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/r7780rp.h>
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@ -22,6 +22,20 @@
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#include <linux/delay.h>
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#include "pci-sh4.h"
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#define INTC_BASE 0xffd00000
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#define INTC_ICR0 (INTC_BASE+0x0)
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#define INTC_ICR1 (INTC_BASE+0x1c)
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#define INTC_INTPRI (INTC_BASE+0x10)
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#define INTC_INTREQ (INTC_BASE+0x24)
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#define INTC_INTMSK0 (INTC_BASE+0x44)
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#define INTC_INTMSK1 (INTC_BASE+0x48)
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#define INTC_INTMSK2 (INTC_BASE+0x40080)
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#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
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#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
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#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
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#define INTC_INT2MSKR (INTC_BASE+0x40038)
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#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
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/*
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* Initialization. Try all known PCI access methods. Note that we support
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* using both PCI BIOS and direct access: in such cases, we use I/O ports
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@ -11,22 +11,29 @@
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* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7760)
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#define INTC2_BASE 0xfe080000
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#define INTC2_INTMSK (INTC2_BASE + 0x40)
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#define INTC2_INTMSKCLR (INTC2_BASE + 0x60)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define INTC2_BASE 0xffd40000
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#define INTC2_INTMSK (INTC2_BASE + 0x38)
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#define INTC2_INTMSKCLR (INTC2_BASE + 0x3c)
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#endif
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static void disable_intc2_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift,
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INTC2_BASE + INTC2_INTMSK_OFFSET + p->msk_offset);
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ctrl_outl(1 << p->msk_shift, INTC2_INTMSK + p->msk_offset);
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}
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static void enable_intc2_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift,
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INTC2_BASE + INTC2_INTMSKCLR_OFFSET + p->msk_offset);
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ctrl_outl(1 << p->msk_shift, INTC2_INTMSKCLR + p->msk_offset);
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}
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static struct irq_chip intc2_irq_chip = {
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@ -61,12 +68,10 @@ void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs)
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/* Set the priority level */
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local_irq_save(flags);
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ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET +
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p->ipr_offset);
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ipr = ctrl_inl(INTC2_BASE + p->ipr_offset);
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ipr &= ~(0xf << p->ipr_shift);
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ipr |= p->priority << p->ipr_shift;
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ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET +
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p->ipr_offset);
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ctrl_outl(ipr, INTC2_BASE + p->ipr_offset);
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local_irq_restore(flags);
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@ -19,10 +19,8 @@
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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static void disable_ipr_irq(unsigned int irq)
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{
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@ -79,25 +79,27 @@ static int __init sh7780_devices_setup(void)
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__initcall(sh7780_devices_setup);
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static struct intc2_data intc2_irq_table[] = {
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{ 28, 0, 24, 0, INTC_TMU0_MSK, 2 },
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{ 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ 28, 0, 24, 0, 0, 2 }, /* TMU0 */
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{ SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ 21, 1, 0, 0, 2, 2 },
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{ 22, 1, 1, 0, 2, 2 },
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{ 23, 1, 2, 0, 2, 2 },
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{ PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
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{ PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
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{ PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
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{ PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
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{ PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
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{ 40, 8, 24, 0, 3, 3 }, /* SCIF0 ERI */
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{ 41, 8, 24, 0, 3, 3 }, /* SCIF0 RXI */
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{ 42, 8, 24, 0, 3, 3 }, /* SCIF0 BRI */
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{ 43, 8, 24, 0, 3, 3 }, /* SCIF0 TXI */
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{ 76, 8, 16, 0, 4, 3 }, /* SCIF1 ERI */
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{ 77, 8, 16, 0, 4, 3 }, /* SCIF1 RXI */
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{ 78, 8, 16, 0, 4, 3 }, /* SCIF1 BRI */
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{ 79, 8, 16, 0, 4, 3 }, /* SCIF1 TXI */
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{ 64, 0x10, 8, 0, 14, 2 }, /* PCIC0 */
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{ 65, 0x10, 0, 0, 15, 2 }, /* PCIC1 */
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{ 66, 0x14, 24, 0, 16, 2 }, /* PCIC2 */
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{ 67, 0x14, 16, 0, 17, 2 }, /* PCIC3 */
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{ 68, 0x14, 8, 0, 18, 2 }, /* PCIC4 */
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};
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void __init init_IRQ_intc2(void)
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@ -1,84 +0,0 @@
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#ifndef __ASM_SH_CPU_SH2_IRQ_H
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#define __ASM_SH_CPU_SH2_IRQ_H
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/*
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*
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* linux/include/asm-sh/cpu-sh2/irq.h
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Paul Mundt
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*
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*/
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#include <linux/config.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7044)
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#define INTC_IPRA 0xffff8348UL
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#define INTC_IPRB 0xffff834aUL
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#define INTC_IPRC 0xffff834cUL
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#define INTC_IPRD 0xffff834eUL
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#define INTC_IPRE 0xffff8350UL
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#define INTC_IPRF 0xffff8352UL
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#define INTC_IPRG 0xffff8354UL
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#define INTC_IPRH 0xffff8356UL
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#define INTC_ICR 0xffff8358UL
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#define INTC_ISR 0xffff835aUL
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#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
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#define INTC_IPRA 0xfffffee2UL
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#define INTC_IPRB 0xfffffe60UL
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#define INTC_VCRA 0xfffffe62UL
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#define INTC_VCRB 0xfffffe64UL
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#define INTC_VCRC 0xfffffe66UL
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#define INTC_VCRD 0xfffffe68UL
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#define INTC_VCRWDT 0xfffffee4UL
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#define INTC_VCRDIV 0xffffff0cUL
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#define INTC_VCRDMA0 0xffffffa0UL
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#define INTC_VCRDMA1 0xffffffa8UL
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#define INTC_ICR 0xfffffee0UL
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define INTC_IPRA 0xf8140006UL
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#define INTC_IPRB 0xf8140008UL
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#define INTC_IPRC 0xf8080000UL
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#define INTC_IPRD 0xf8080002UL
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#define INTC_IPRE 0xf8080004UL
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#define INTC_IPRF 0xf8080006UL
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#define INTC_IPRG 0xf8080008UL
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#define INTC_ICR0 0xf8140000UL
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#define INTC_IRQCR 0xf8140002UL
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#define INTC_IRQSR 0xf8140004UL
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#define CMI0_IRQ 86
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#define CMI1_IRQ 87
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#define SCIF_ERI_IRQ 88
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#define SCIF_RXI_IRQ 89
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#define SCIF_BRI_IRQ 90
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#define SCIF_TXI_IRQ 91
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#define SCIF_IPR_ADDR INTC_IPRD
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#define SCIF_IPR_POS 3
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#define SCIF_PRIORITY 3
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#define SCIF1_ERI_IRQ 92
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#define SCIF1_RXI_IRQ 93
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#define SCIF1_BRI_IRQ 94
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#define SCIF1_TXI_IRQ 95
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#define SCIF1_IPR_ADDR INTC_IPRD
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#define SCIF1_IPR_POS 2
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#define SCIF1_PRIORITY 3
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#define SCIF2_BRI_IRQ 96
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#define SCIF2_RXI_IRQ 97
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#define SCIF2_ERI_IRQ 98
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#define SCIF2_TXI_IRQ 99
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#define SCIF2_IPR_ADDR INTC_IPRD
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#define SCIF2_IPR_POS 1
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#define SCIF2_PRIORITY 3
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#endif
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#endif /* __ASM_SH_CPU_SH2_IRQ_H */
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@ -1,75 +0,0 @@
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#ifndef __ASM_SH_CPU_SH2A_IRQ_H
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#define __ASM_SH_CPU_SH2A_IRQ_H
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#define INTC_IPR01 0xfffe0818UL
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#define INTC_IPR02 0xfffe081aUL
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#define INTC_IPR05 0xfffe0820UL
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#define INTC_IPR06 0xfffe0c00UL
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#define INTC_IPR07 0xfffe0c02UL
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#define INTC_IPR08 0xfffe0c04UL
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#define INTC_IPR09 0xfffe0c06UL
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#define INTC_IPR10 0xfffe0c08UL
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#define INTC_IPR11 0xfffe0c0aUL
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#define INTC_IPR12 0xfffe0c0cUL
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#define INTC_IPR13 0xfffe0c0eUL
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#define INTC_IPR14 0xfffe0c10UL
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#define INTC_ICR0 0xfffe0800UL
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#define INTC_ICR1 0xfffe0802UL
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#define INTC_ICR2 0xfffe0804UL
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#define INTC_ISR 0xfffe0806UL
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#define IRQ0_IRQ 64
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#define IRQ1_IRQ 65
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#define IRQ2_IRQ 66
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#define IRQ3_IRQ 67
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#define IRQ4_IRQ 68
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#define IRQ5_IRQ 69
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#define IRQ6_IRQ 70
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#define IRQ7_IRQ 71
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#define PINT0_IRQ 80
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#define PINT1_IRQ 81
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#define PINT2_IRQ 82
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#define PINT3_IRQ 83
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#define PINT4_IRQ 84
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#define PINT5_IRQ 85
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#define PINT6_IRQ 86
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#define PINT7_IRQ 87
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#define CMI0_IRQ 140
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#define CMI1_IRQ 141
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#define SCIF_BRI_IRQ 240
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#define SCIF_ERI_IRQ 241
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#define SCIF_RXI_IRQ 242
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#define SCIF_TXI_IRQ 243
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#define SCIF_IPR_ADDR INTC_IPR14
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#define SCIF_IPR_POS 3
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#define SCIF_PRIORITY 3
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#define SCIF1_BRI_IRQ 244
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#define SCIF1_ERI_IRQ 245
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#define SCIF1_RXI_IRQ 246
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#define SCIF1_TXI_IRQ 247
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#define SCIF1_IPR_ADDR INTC_IPR14
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#define SCIF1_IPR_POS 2
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#define SCIF1_PRIORITY 3
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#define SCIF2_BRI_IRQ 248
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#define SCIF2_ERI_IRQ 249
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#define SCIF2_RXI_IRQ 250
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#define SCIF2_TXI_IRQ 251
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#define SCIF2_IPR_ADDR INTC_IPR14
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#define SCIF2_IPR_POS 1
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#define SCIF2_PRIORITY 3
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#define SCIF3_BRI_IRQ 252
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#define SCIF3_ERI_IRQ 253
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#define SCIF3_RXI_IRQ 254
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#define SCIF3_TXI_IRQ 255
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#define SCIF3_IPR_ADDR INTC_IPR14
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#define SCIF3_IPR_POS 0
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#define SCIF3_PRIORITY 3
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#endif /* __ASM_SH_CPU_SH2A_IRQ_H */
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@ -1,314 +0,0 @@
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#ifndef __ASM_SH_IRQ_SH73180_H
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#define __ASM_SH_IRQ_SH73180_H
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/*
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* linux/include/asm-sh/irq-sh73180.h
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*
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* Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
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*/
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#undef INTC_IPRA
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#undef INTC_IPRB
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#undef INTC_IPRC
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#undef INTC_IPRD
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#undef DMTE0_IRQ
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#undef DMTE1_IRQ
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#undef DMTE2_IRQ
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#undef DMTE3_IRQ
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#undef DMTE4_IRQ
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#undef DMTE5_IRQ
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#undef DMTE6_IRQ
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#undef DMTE7_IRQ
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#undef DMAE_IRQ
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#undef DMA_IPR_ADDR
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#undef DMA_IPR_POS
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#undef DMA_PRIORITY
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#undef INTC_IMCR0
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#undef INTC_IMCR1
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#undef INTC_IMCR2
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#undef INTC_IMCR3
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#undef INTC_IMCR4
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#undef INTC_IMCR5
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#undef INTC_IMCR6
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#undef INTC_IMCR7
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#undef INTC_IMCR8
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#undef INTC_IMCR9
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#undef INTC_IMCR10
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#define INTC_IPRA 0xA4080000UL
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#define INTC_IPRB 0xA4080004UL
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#define INTC_IPRC 0xA4080008UL
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#define INTC_IPRD 0xA408000CUL
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#define INTC_IPRE 0xA4080010UL
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#define INTC_IPRF 0xA4080014UL
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#define INTC_IPRG 0xA4080018UL
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#define INTC_IPRH 0xA408001CUL
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#define INTC_IPRI 0xA4080020UL
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#define INTC_IPRJ 0xA4080024UL
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#define INTC_IPRK 0xA4080028UL
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#define INTC_IMR0 0xA4080080UL
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#define INTC_IMR1 0xA4080084UL
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#define INTC_IMR2 0xA4080088UL
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#define INTC_IMR3 0xA408008CUL
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#define INTC_IMR4 0xA4080090UL
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#define INTC_IMR5 0xA4080094UL
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#define INTC_IMR6 0xA4080098UL
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#define INTC_IMR7 0xA408009CUL
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#define INTC_IMR8 0xA40800A0UL
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#define INTC_IMR9 0xA40800A4UL
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#define INTC_IMR10 0xA40800A8UL
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#define INTC_IMR11 0xA40800ACUL
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#define INTC_IMCR0 0xA40800C0UL
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#define INTC_IMCR1 0xA40800C4UL
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#define INTC_IMCR2 0xA40800C8UL
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#define INTC_IMCR3 0xA40800CCUL
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#define INTC_IMCR4 0xA40800D0UL
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#define INTC_IMCR5 0xA40800D4UL
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#define INTC_IMCR6 0xA40800D8UL
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#define INTC_IMCR7 0xA40800DCUL
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#define INTC_IMCR8 0xA40800E0UL
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#define INTC_IMCR9 0xA40800E4UL
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#define INTC_IMCR10 0xA40800E8UL
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#define INTC_IMCR11 0xA40800ECUL
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#define INTC_ICR0 0xA4140000UL
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#define INTC_ICR1 0xA414001CUL
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#define INTMSK0 0xa4140044
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#define INTMSKCLR0 0xa4140064
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#define INTC_INTPRI0 0xa4140010
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/*
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NOTE:
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*_IRQ = (INTEVT2 - 0x200)/0x20
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*/
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/* TMU0 */
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#define TMU0_IRQ 16
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#define TMU0_IPR_ADDR INTC_IPRA
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#define TMU0_IPR_POS 3
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#define TMU0_PRIORITY 2
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|
||||
#define TIMER_IRQ 16
|
||||
#define TIMER_IPR_ADDR INTC_IPRA
|
||||
#define TIMER_IPR_POS 3
|
||||
#define TIMER_PRIORITY 2
|
||||
|
||||
/* TMU1 */
|
||||
#define TMU1_IRQ 17
|
||||
#define TMU1_IPR_ADDR INTC_IPRA
|
||||
#define TMU1_IPR_POS 2
|
||||
#define TMU1_PRIORITY 2
|
||||
|
||||
/* TMU2 */
|
||||
#define TMU2_IRQ 18
|
||||
#define TMU2_IPR_ADDR INTC_IPRA
|
||||
#define TMU2_IPR_POS 1
|
||||
#define TMU2_PRIORITY 2
|
||||
|
||||
/* LCDC */
|
||||
#define LCDC_IRQ 28
|
||||
#define LCDC_IPR_ADDR INTC_IPRB
|
||||
#define LCDC_IPR_POS 2
|
||||
#define LCDC_PRIORITY 2
|
||||
|
||||
/* VIO (Video I/O) */
|
||||
#define CEU_IRQ 52
|
||||
#define BEU_IRQ 53
|
||||
#define VEU_IRQ 54
|
||||
#define VOU_IRQ 55
|
||||
#define VIO_IPR_ADDR INTC_IPRE
|
||||
#define VIO_IPR_POS 2
|
||||
#define VIO_PRIORITY 2
|
||||
|
||||
/* MFI (Multi Functional Interface) */
|
||||
#define MFI_IRQ 56
|
||||
#define MFI_IPR_ADDR INTC_IPRE
|
||||
#define MFI_IPR_POS 1
|
||||
#define MFI_PRIORITY 2
|
||||
|
||||
/* VPU (Video Processing Unit) */
|
||||
#define VPU_IRQ 60
|
||||
#define VPU_IPR_ADDR INTC_IPRE
|
||||
#define VPU_IPR_POS 0
|
||||
#define VPU_PRIORITY 2
|
||||
|
||||
/* 3DG */
|
||||
#define TDG_IRQ 63
|
||||
#define TDG_IPR_ADDR INTC_IPRJ
|
||||
#define TDG_IPR_POS 2
|
||||
#define TDG_PRIORITY 2
|
||||
|
||||
/* DMAC(1) */
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE1_IRQ 49
|
||||
#define DMTE2_IRQ 50
|
||||
#define DMTE3_IRQ 51
|
||||
#define DMA1_IPR_ADDR INTC_IPRE
|
||||
#define DMA1_IPR_POS 3
|
||||
#define DMA1_PRIORITY 7
|
||||
|
||||
/* DMAC(2) */
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMTE5_IRQ 77
|
||||
#define DMA2_IPR_ADDR INTC_IPRF
|
||||
#define DMA2_IPR_POS 2
|
||||
#define DMA2_PRIORITY 7
|
||||
|
||||
/* SCIF0 */
|
||||
#define SCIF_ERI_IRQ 80
|
||||
#define SCIF_RXI_IRQ 81
|
||||
#define SCIF_BRI_IRQ 82
|
||||
#define SCIF_TXI_IRQ 83
|
||||
#define SCIF_IPR_ADDR INTC_IPRG
|
||||
#define SCIF_IPR_POS 3
|
||||
#define SCIF_PRIORITY 3
|
||||
|
||||
/* SIOF0 */
|
||||
#define SIOF0_IRQ 84
|
||||
#define SIOF0_IPR_ADDR INTC_IPRH
|
||||
#define SIOF0_IPR_POS 3
|
||||
#define SIOF0_PRIORITY 3
|
||||
|
||||
/* FLCTL (Flash Memory Controller) */
|
||||
#define FLSTE_IRQ 92
|
||||
#define FLTEND_IRQ 93
|
||||
#define FLTRQ0_IRQ 94
|
||||
#define FLTRQ1_IRQ 95
|
||||
#define FLCTL_IPR_ADDR INTC_IPRH
|
||||
#define FLCTL_IPR_POS 1
|
||||
#define FLCTL_PRIORITY 3
|
||||
|
||||
/* IIC(0) (IIC Bus Interface) */
|
||||
#define IIC0_ALI_IRQ 96
|
||||
#define IIC0_TACKI_IRQ 97
|
||||
#define IIC0_WAITI_IRQ 98
|
||||
#define IIC0_DTEI_IRQ 99
|
||||
#define IIC0_IPR_ADDR INTC_IPRH
|
||||
#define IIC0_IPR_POS 0
|
||||
#define IIC0_PRIORITY 3
|
||||
|
||||
/* IIC(1) (IIC Bus Interface) */
|
||||
#define IIC1_ALI_IRQ 44
|
||||
#define IIC1_TACKI_IRQ 45
|
||||
#define IIC1_WAITI_IRQ 46
|
||||
#define IIC1_DTEI_IRQ 47
|
||||
#define IIC1_IPR_ADDR INTC_IPRG
|
||||
#define IIC1_IPR_POS 0
|
||||
#define IIC1_PRIORITY 3
|
||||
|
||||
/* SIO0 */
|
||||
#define SIO0_IRQ 88
|
||||
#define SIO0_IPR_ADDR INTC_IPRI
|
||||
#define SIO0_IPR_POS 3
|
||||
#define SIO0_PRIORITY 3
|
||||
|
||||
/* SDHI */
|
||||
#define SDHI_SDHII0_IRQ 100
|
||||
#define SDHI_SDHII1_IRQ 101
|
||||
#define SDHI_SDHII2_IRQ 102
|
||||
#define SDHI_SDHII3_IRQ 103
|
||||
#define SDHI_IPR_ADDR INTC_IPRK
|
||||
#define SDHI_IPR_POS 0
|
||||
#define SDHI_PRIORITY 3
|
||||
|
||||
/* SIU (Sound Interface Unit) */
|
||||
#define SIU_IRQ 108
|
||||
#define SIU_IPR_ADDR INTC_IPRJ
|
||||
#define SIU_IPR_POS 1
|
||||
#define SIU_PRIORITY 3
|
||||
|
||||
#define PORT_PACR 0xA4050100UL
|
||||
#define PORT_PBCR 0xA4050102UL
|
||||
#define PORT_PCCR 0xA4050104UL
|
||||
#define PORT_PDCR 0xA4050106UL
|
||||
#define PORT_PECR 0xA4050108UL
|
||||
#define PORT_PFCR 0xA405010AUL
|
||||
#define PORT_PGCR 0xA405010CUL
|
||||
#define PORT_PHCR 0xA405010EUL
|
||||
#define PORT_PJCR 0xA4050110UL
|
||||
#define PORT_PKCR 0xA4050112UL
|
||||
#define PORT_PLCR 0xA4050114UL
|
||||
#define PORT_SCPCR 0xA4050116UL
|
||||
#define PORT_PMCR 0xA4050118UL
|
||||
#define PORT_PNCR 0xA405011AUL
|
||||
#define PORT_PQCR 0xA405011CUL
|
||||
#define PORT_PRCR 0xA405011EUL
|
||||
#define PORT_PTCR 0xA405014CUL
|
||||
#define PORT_PUCR 0xA405014EUL
|
||||
#define PORT_PVCR 0xA4050150UL
|
||||
|
||||
#define PORT_PSELA 0xA4050140UL
|
||||
#define PORT_PSELB 0xA4050142UL
|
||||
#define PORT_PSELC 0xA4050144UL
|
||||
#define PORT_PSELE 0xA4050158UL
|
||||
|
||||
#define PORT_HIZCRA 0xA4050146UL
|
||||
#define PORT_HIZCRB 0xA4050148UL
|
||||
#define PORT_DRVCR 0xA405014AUL
|
||||
|
||||
#define PORT_PADR 0xA4050120UL
|
||||
#define PORT_PBDR 0xA4050122UL
|
||||
#define PORT_PCDR 0xA4050124UL
|
||||
#define PORT_PDDR 0xA4050126UL
|
||||
#define PORT_PEDR 0xA4050128UL
|
||||
#define PORT_PFDR 0xA405012AUL
|
||||
#define PORT_PGDR 0xA405012CUL
|
||||
#define PORT_PHDR 0xA405012EUL
|
||||
#define PORT_PJDR 0xA4050130UL
|
||||
#define PORT_PKDR 0xA4050132UL
|
||||
#define PORT_PLDR 0xA4050134UL
|
||||
#define PORT_SCPDR 0xA4050136UL
|
||||
#define PORT_PMDR 0xA4050138UL
|
||||
#define PORT_PNDR 0xA405013AUL
|
||||
#define PORT_PQDR 0xA405013CUL
|
||||
#define PORT_PRDR 0xA405013EUL
|
||||
#define PORT_PTDR 0xA405016CUL
|
||||
#define PORT_PUDR 0xA405016EUL
|
||||
#define PORT_PVDR 0xA4050170UL
|
||||
|
||||
#define IRQ0_IRQ 32
|
||||
#define IRQ1_IRQ 33
|
||||
#define IRQ2_IRQ 34
|
||||
#define IRQ3_IRQ 35
|
||||
#define IRQ4_IRQ 36
|
||||
#define IRQ5_IRQ 37
|
||||
#define IRQ6_IRQ 38
|
||||
#define IRQ7_IRQ 39
|
||||
|
||||
#define INTPRI00 0xA4140010UL
|
||||
|
||||
#define IRQ0_IPR_ADDR INTPRI00
|
||||
#define IRQ1_IPR_ADDR INTPRI00
|
||||
#define IRQ2_IPR_ADDR INTPRI00
|
||||
#define IRQ3_IPR_ADDR INTPRI00
|
||||
#define IRQ4_IPR_ADDR INTPRI00
|
||||
#define IRQ5_IPR_ADDR INTPRI00
|
||||
#define IRQ6_IPR_ADDR INTPRI00
|
||||
#define IRQ7_IPR_ADDR INTPRI00
|
||||
|
||||
#define IRQ0_IPR_POS 7
|
||||
#define IRQ1_IPR_POS 6
|
||||
#define IRQ2_IPR_POS 5
|
||||
#define IRQ3_IPR_POS 4
|
||||
#define IRQ4_IPR_POS 3
|
||||
#define IRQ5_IPR_POS 2
|
||||
#define IRQ6_IPR_POS 1
|
||||
#define IRQ7_IPR_POS 0
|
||||
|
||||
#define IRQ0_PRIORITY 1
|
||||
#define IRQ1_PRIORITY 1
|
||||
#define IRQ2_PRIORITY 1
|
||||
#define IRQ3_PRIORITY 1
|
||||
#define IRQ4_PRIORITY 1
|
||||
#define IRQ5_PRIORITY 1
|
||||
#define IRQ6_PRIORITY 1
|
||||
#define IRQ7_PRIORITY 1
|
||||
|
||||
#endif /* __ASM_SH_IRQ_SH73180_H */
|
||||
@ -1,317 +0,0 @@
|
||||
#ifndef __ASM_SH_IRQ_SH7343_H
|
||||
#define __ASM_SH_IRQ_SH7343_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/irq-sh7343.h
|
||||
*
|
||||
* Copyright (C) 2006 Kenati Technologies Inc.
|
||||
* Andre Mccurdy <andre@kenati.com>
|
||||
* Ranjit Deshpande <ranjit@kenati.com>
|
||||
*/
|
||||
|
||||
#undef INTC_IPRA
|
||||
#undef INTC_IPRB
|
||||
#undef INTC_IPRC
|
||||
#undef INTC_IPRD
|
||||
|
||||
#undef DMTE0_IRQ
|
||||
#undef DMTE1_IRQ
|
||||
#undef DMTE2_IRQ
|
||||
#undef DMTE3_IRQ
|
||||
#undef DMTE4_IRQ
|
||||
#undef DMTE5_IRQ
|
||||
#undef DMTE6_IRQ
|
||||
#undef DMTE7_IRQ
|
||||
#undef DMAE_IRQ
|
||||
#undef DMA_IPR_ADDR
|
||||
#undef DMA_IPR_POS
|
||||
#undef DMA_PRIORITY
|
||||
|
||||
#undef INTC_IMCR0
|
||||
#undef INTC_IMCR1
|
||||
#undef INTC_IMCR2
|
||||
#undef INTC_IMCR3
|
||||
#undef INTC_IMCR4
|
||||
#undef INTC_IMCR5
|
||||
#undef INTC_IMCR6
|
||||
#undef INTC_IMCR7
|
||||
#undef INTC_IMCR8
|
||||
#undef INTC_IMCR9
|
||||
#undef INTC_IMCR10
|
||||
|
||||
|
||||
#define INTC_IPRA 0xA4080000UL
|
||||
#define INTC_IPRB 0xA4080004UL
|
||||
#define INTC_IPRC 0xA4080008UL
|
||||
#define INTC_IPRD 0xA408000CUL
|
||||
#define INTC_IPRE 0xA4080010UL
|
||||
#define INTC_IPRF 0xA4080014UL
|
||||
#define INTC_IPRG 0xA4080018UL
|
||||
#define INTC_IPRH 0xA408001CUL
|
||||
#define INTC_IPRI 0xA4080020UL
|
||||
#define INTC_IPRJ 0xA4080024UL
|
||||
#define INTC_IPRK 0xA4080028UL
|
||||
#define INTC_IPRL 0xA408002CUL
|
||||
|
||||
#define INTC_IMR0 0xA4080080UL
|
||||
#define INTC_IMR1 0xA4080084UL
|
||||
#define INTC_IMR2 0xA4080088UL
|
||||
#define INTC_IMR3 0xA408008CUL
|
||||
#define INTC_IMR4 0xA4080090UL
|
||||
#define INTC_IMR5 0xA4080094UL
|
||||
#define INTC_IMR6 0xA4080098UL
|
||||
#define INTC_IMR7 0xA408009CUL
|
||||
#define INTC_IMR8 0xA40800A0UL
|
||||
#define INTC_IMR9 0xA40800A4UL
|
||||
#define INTC_IMR10 0xA40800A8UL
|
||||
#define INTC_IMR11 0xA40800ACUL
|
||||
|
||||
#define INTC_IMCR0 0xA40800C0UL
|
||||
#define INTC_IMCR1 0xA40800C4UL
|
||||
#define INTC_IMCR2 0xA40800C8UL
|
||||
#define INTC_IMCR3 0xA40800CCUL
|
||||
#define INTC_IMCR4 0xA40800D0UL
|
||||
#define INTC_IMCR5 0xA40800D4UL
|
||||
#define INTC_IMCR6 0xA40800D8UL
|
||||
#define INTC_IMCR7 0xA40800DCUL
|
||||
#define INTC_IMCR8 0xA40800E0UL
|
||||
#define INTC_IMCR9 0xA40800E4UL
|
||||
#define INTC_IMCR10 0xA40800E8UL
|
||||
#define INTC_IMCR11 0xA40800ECUL
|
||||
|
||||
#define INTC_ICR0 0xA4140000UL
|
||||
#define INTC_ICR1 0xA414001CUL
|
||||
|
||||
#define INTMSK0 0xa4140044
|
||||
#define INTMSKCLR0 0xa4140064
|
||||
#define INTC_INTPRI0 0xa4140010
|
||||
|
||||
/*
|
||||
NOTE:
|
||||
|
||||
*_IRQ = (INTEVT2 - 0x200)/0x20
|
||||
*/
|
||||
|
||||
/* TMU0 */
|
||||
#define TMU0_IRQ 16
|
||||
#define TMU0_IPR_ADDR INTC_IPRA
|
||||
#define TMU0_IPR_POS 3
|
||||
#define TMU0_PRIORITY 2
|
||||
|
||||
#define TIMER_IRQ 16
|
||||
#define TIMER_IPR_ADDR INTC_IPRA
|
||||
#define TIMER_IPR_POS 3
|
||||
#define TIMER_PRIORITY 2
|
||||
|
||||
/* TMU1 */
|
||||
#define TMU1_IRQ 17
|
||||
#define TMU1_IPR_ADDR INTC_IPRA
|
||||
#define TMU1_IPR_POS 2
|
||||
#define TMU1_PRIORITY 2
|
||||
|
||||
/* TMU2 */
|
||||
#define TMU2_IRQ 18
|
||||
#define TMU2_IPR_ADDR INTC_IPRA
|
||||
#define TMU2_IPR_POS 1
|
||||
#define TMU2_PRIORITY 2
|
||||
|
||||
/* LCDC */
|
||||
#define LCDC_IRQ 28
|
||||
#define LCDC_IPR_ADDR INTC_IPRB
|
||||
#define LCDC_IPR_POS 2
|
||||
#define LCDC_PRIORITY 2
|
||||
|
||||
/* VIO (Video I/O) */
|
||||
#define CEU_IRQ 52
|
||||
#define BEU_IRQ 53
|
||||
#define VEU_IRQ 54
|
||||
#define VOU_IRQ 55
|
||||
#define VIO_IPR_ADDR INTC_IPRE
|
||||
#define VIO_IPR_POS 2
|
||||
#define VIO_PRIORITY 2
|
||||
|
||||
/* MFI (Multi Functional Interface) */
|
||||
#define MFI_IRQ 56
|
||||
#define MFI_IPR_ADDR INTC_IPRE
|
||||
#define MFI_IPR_POS 1
|
||||
#define MFI_PRIORITY 2
|
||||
|
||||
/* VPU (Video Processing Unit) */
|
||||
#define VPU_IRQ 60
|
||||
#define VPU_IPR_ADDR INTC_IPRE
|
||||
#define VPU_IPR_POS 0
|
||||
#define VPU_PRIORITY 2
|
||||
|
||||
/* 3DG */
|
||||
#define TDG_IRQ 63
|
||||
#define TDG_IPR_ADDR INTC_IPRJ
|
||||
#define TDG_IPR_POS 2
|
||||
#define TDG_PRIORITY 2
|
||||
|
||||
/* DMAC(1) */
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE1_IRQ 49
|
||||
#define DMTE2_IRQ 50
|
||||
#define DMTE3_IRQ 51
|
||||
#define DMA1_IPR_ADDR INTC_IPRE
|
||||
#define DMA1_IPR_POS 3
|
||||
#define DMA1_PRIORITY 7
|
||||
|
||||
/* DMAC(2) */
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMTE5_IRQ 77
|
||||
#define DMA2_IPR_ADDR INTC_IPRF
|
||||
#define DMA2_IPR_POS 2
|
||||
#define DMA2_PRIORITY 7
|
||||
|
||||
/* SCIF0 */
|
||||
#define SCIF_ERI_IRQ 80
|
||||
#define SCIF_RXI_IRQ 81
|
||||
#define SCIF_BRI_IRQ 82
|
||||
#define SCIF_TXI_IRQ 83
|
||||
#define SCIF_IPR_ADDR INTC_IPRG
|
||||
#define SCIF_IPR_POS 3
|
||||
#define SCIF_PRIORITY 3
|
||||
|
||||
/* SIOF0 */
|
||||
#define SIOF0_IRQ 84
|
||||
#define SIOF0_IPR_ADDR INTC_IPRH
|
||||
#define SIOF0_IPR_POS 3
|
||||
#define SIOF0_PRIORITY 3
|
||||
|
||||
/* FLCTL (Flash Memory Controller) */
|
||||
#define FLSTE_IRQ 92
|
||||
#define FLTEND_IRQ 93
|
||||
#define FLTRQ0_IRQ 94
|
||||
#define FLTRQ1_IRQ 95
|
||||
#define FLCTL_IPR_ADDR INTC_IPRH
|
||||
#define FLCTL_IPR_POS 1
|
||||
#define FLCTL_PRIORITY 3
|
||||
|
||||
/* IIC(0) (IIC Bus Interface) */
|
||||
#define IIC0_ALI_IRQ 96
|
||||
#define IIC0_TACKI_IRQ 97
|
||||
#define IIC0_WAITI_IRQ 98
|
||||
#define IIC0_DTEI_IRQ 99
|
||||
#define IIC0_IPR_ADDR INTC_IPRH
|
||||
#define IIC0_IPR_POS 0
|
||||
#define IIC0_PRIORITY 3
|
||||
|
||||
/* IIC(1) (IIC Bus Interface) */
|
||||
#define IIC1_ALI_IRQ 44
|
||||
#define IIC1_TACKI_IRQ 45
|
||||
#define IIC1_WAITI_IRQ 46
|
||||
#define IIC1_DTEI_IRQ 47
|
||||
#define IIC1_IPR_ADDR INTC_IPRI
|
||||
#define IIC1_IPR_POS 0
|
||||
#define IIC1_PRIORITY 3
|
||||
|
||||
/* SIO0 */
|
||||
#define SIO0_IRQ 88
|
||||
#define SIO0_IPR_ADDR INTC_IPRI
|
||||
#define SIO0_IPR_POS 3
|
||||
#define SIO0_PRIORITY 3
|
||||
|
||||
/* SDHI */
|
||||
#define SDHI_SDHII0_IRQ 100
|
||||
#define SDHI_SDHII1_IRQ 101
|
||||
#define SDHI_SDHII2_IRQ 102
|
||||
#define SDHI_SDHII3_IRQ 103
|
||||
#define SDHI_IPR_ADDR INTC_IPRK
|
||||
#define SDHI_IPR_POS 0
|
||||
#define SDHI_PRIORITY 3
|
||||
|
||||
/* SIU (Sound Interface Unit) */
|
||||
#define SIU_IRQ 108
|
||||
#define SIU_IPR_ADDR INTC_IPRJ
|
||||
#define SIU_IPR_POS 1
|
||||
#define SIU_PRIORITY 3
|
||||
|
||||
#define PORT_PACR 0xA4050100UL
|
||||
#define PORT_PBCR 0xA4050102UL
|
||||
#define PORT_PCCR 0xA4050104UL
|
||||
#define PORT_PDCR 0xA4050106UL
|
||||
#define PORT_PECR 0xA4050108UL
|
||||
#define PORT_PFCR 0xA405010AUL
|
||||
#define PORT_PGCR 0xA405010CUL
|
||||
#define PORT_PHCR 0xA405010EUL
|
||||
#define PORT_PJCR 0xA4050110UL
|
||||
#define PORT_PKCR 0xA4050112UL
|
||||
#define PORT_PLCR 0xA4050114UL
|
||||
#define PORT_SCPCR 0xA4050116UL
|
||||
#define PORT_PMCR 0xA4050118UL
|
||||
#define PORT_PNCR 0xA405011AUL
|
||||
#define PORT_PQCR 0xA405011CUL
|
||||
#define PORT_PRCR 0xA405011EUL
|
||||
#define PORT_PTCR 0xA405014CUL
|
||||
#define PORT_PUCR 0xA405014EUL
|
||||
#define PORT_PVCR 0xA4050150UL
|
||||
|
||||
#define PORT_PSELA 0xA4050140UL
|
||||
#define PORT_PSELB 0xA4050142UL
|
||||
#define PORT_PSELC 0xA4050144UL
|
||||
#define PORT_PSELE 0xA4050158UL
|
||||
|
||||
#define PORT_HIZCRA 0xA4050146UL
|
||||
#define PORT_HIZCRB 0xA4050148UL
|
||||
#define PORT_DRVCR 0xA405014AUL
|
||||
|
||||
#define PORT_PADR 0xA4050120UL
|
||||
#define PORT_PBDR 0xA4050122UL
|
||||
#define PORT_PCDR 0xA4050124UL
|
||||
#define PORT_PDDR 0xA4050126UL
|
||||
#define PORT_PEDR 0xA4050128UL
|
||||
#define PORT_PFDR 0xA405012AUL
|
||||
#define PORT_PGDR 0xA405012CUL
|
||||
#define PORT_PHDR 0xA405012EUL
|
||||
#define PORT_PJDR 0xA4050130UL
|
||||
#define PORT_PKDR 0xA4050132UL
|
||||
#define PORT_PLDR 0xA4050134UL
|
||||
#define PORT_SCPDR 0xA4050136UL
|
||||
#define PORT_PMDR 0xA4050138UL
|
||||
#define PORT_PNDR 0xA405013AUL
|
||||
#define PORT_PQDR 0xA405013CUL
|
||||
#define PORT_PRDR 0xA405013EUL
|
||||
#define PORT_PTDR 0xA405016CUL
|
||||
#define PORT_PUDR 0xA405016EUL
|
||||
#define PORT_PVDR 0xA4050170UL
|
||||
|
||||
#define IRQ0_IRQ 32
|
||||
#define IRQ1_IRQ 33
|
||||
#define IRQ2_IRQ 34
|
||||
#define IRQ3_IRQ 35
|
||||
#define IRQ4_IRQ 36
|
||||
#define IRQ5_IRQ 37
|
||||
#define IRQ6_IRQ 38
|
||||
#define IRQ7_IRQ 39
|
||||
|
||||
#define INTPRI00 0xA4140010UL
|
||||
|
||||
#define IRQ0_IPR_ADDR INTPRI00
|
||||
#define IRQ1_IPR_ADDR INTPRI00
|
||||
#define IRQ2_IPR_ADDR INTPRI00
|
||||
#define IRQ3_IPR_ADDR INTPRI00
|
||||
#define IRQ4_IPR_ADDR INTPRI00
|
||||
#define IRQ5_IPR_ADDR INTPRI00
|
||||
#define IRQ6_IPR_ADDR INTPRI00
|
||||
#define IRQ7_IPR_ADDR INTPRI00
|
||||
|
||||
#define IRQ0_IPR_POS 7
|
||||
#define IRQ1_IPR_POS 6
|
||||
#define IRQ2_IPR_POS 5
|
||||
#define IRQ3_IPR_POS 4
|
||||
#define IRQ4_IPR_POS 3
|
||||
#define IRQ5_IPR_POS 2
|
||||
#define IRQ6_IPR_POS 1
|
||||
#define IRQ7_IPR_POS 0
|
||||
|
||||
#define IRQ0_PRIORITY 1
|
||||
#define IRQ1_PRIORITY 1
|
||||
#define IRQ2_PRIORITY 1
|
||||
#define IRQ3_PRIORITY 1
|
||||
#define IRQ4_PRIORITY 1
|
||||
#define IRQ5_PRIORITY 1
|
||||
#define IRQ6_PRIORITY 1
|
||||
#define IRQ7_PRIORITY 1
|
||||
|
||||
#endif /* __ASM_SH_IRQ_SH7343_H */
|
||||
@ -1,311 +0,0 @@
|
||||
#ifndef __ASM_SH_IRQ_SH7780_H
|
||||
#define __ASM_SH_IRQ_SH7780_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/irq-sh7780.h
|
||||
*
|
||||
* Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
|
||||
*/
|
||||
#define INTC_BASE 0xffd00000
|
||||
#define INTC_ICR0 (INTC_BASE+0x0)
|
||||
#define INTC_ICR1 (INTC_BASE+0x1c)
|
||||
#define INTC_INTPRI (INTC_BASE+0x10)
|
||||
#define INTC_INTREQ (INTC_BASE+0x24)
|
||||
#define INTC_INTMSK0 (INTC_BASE+0x44)
|
||||
#define INTC_INTMSK1 (INTC_BASE+0x48)
|
||||
#define INTC_INTMSK2 (INTC_BASE+0x40080)
|
||||
#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
|
||||
#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
|
||||
#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
|
||||
#define INTC_NMIFCR (INTC_BASE+0xc0)
|
||||
#define INTC_USERIMASK (INTC_BASE+0x30000)
|
||||
|
||||
#define INTC_INT2PRI0 (INTC_BASE+0x40000)
|
||||
#define INTC_INT2PRI1 (INTC_BASE+0x40004)
|
||||
#define INTC_INT2PRI2 (INTC_BASE+0x40008)
|
||||
#define INTC_INT2PRI3 (INTC_BASE+0x4000c)
|
||||
#define INTC_INT2PRI4 (INTC_BASE+0x40010)
|
||||
#define INTC_INT2PRI5 (INTC_BASE+0x40014)
|
||||
#define INTC_INT2PRI6 (INTC_BASE+0x40018)
|
||||
#define INTC_INT2PRI7 (INTC_BASE+0x4001c)
|
||||
#define INTC_INT2A0 (INTC_BASE+0x40030)
|
||||
#define INTC_INT2A1 (INTC_BASE+0x40034)
|
||||
#define INTC_INT2MSKR (INTC_BASE+0x40038)
|
||||
#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
|
||||
#define INTC_INT2B0 (INTC_BASE+0x40040)
|
||||
#define INTC_INT2B1 (INTC_BASE+0x40044)
|
||||
#define INTC_INT2B2 (INTC_BASE+0x40048)
|
||||
#define INTC_INT2B3 (INTC_BASE+0x4004c)
|
||||
#define INTC_INT2B4 (INTC_BASE+0x40050)
|
||||
#define INTC_INT2B5 (INTC_BASE+0x40054)
|
||||
#define INTC_INT2B6 (INTC_BASE+0x40058)
|
||||
#define INTC_INT2B7 (INTC_BASE+0x4005c)
|
||||
#define INTC_INT2GPIC (INTC_BASE+0x40090)
|
||||
/*
|
||||
NOTE:
|
||||
*_IRQ = (INTEVT2 - 0x200)/0x20
|
||||
*/
|
||||
/* IRQ 0-7 line external int*/
|
||||
#define IRQ0_IRQ 2
|
||||
#define IRQ0_IPR_ADDR INTC_INTPRI
|
||||
#define IRQ0_IPR_POS 7
|
||||
#define IRQ0_PRIORITY 2
|
||||
|
||||
#define IRQ1_IRQ 4
|
||||
#define IRQ1_IPR_ADDR INTC_INTPRI
|
||||
#define IRQ1_IPR_POS 6
|
||||
#define IRQ1_PRIORITY 2
|
||||
|
||||
#define IRQ2_IRQ 6
|
||||
#define IRQ2_IPR_ADDR INTC_INTPRI
|
||||
#define IRQ2_IPR_POS 5
|
||||
#define IRQ2_PRIORITY 2
|
||||
|
||||
#define IRQ3_IRQ 8
|
||||
#define IRQ3_IPR_ADDR INTC_INTPRI
|
||||
#define IRQ3_IPR_POS 4
|
||||
#define IRQ3_PRIORITY 2
|
||||
|
||||
#define IRQ4_IRQ 10
|
||||
#define IRQ4_IPR_ADDR INTC_INTPRI
|
||||
#define IRQ4_IPR_POS 3
|
||||
#define IRQ4_PRIORITY 2
|
||||
|
||||
#define IRQ5_IRQ 12
|
||||
#define IRQ5_IPR_ADDR INTC_INTPRI
|
||||
#define IRQ5_IPR_POS 2
|
||||
#define IRQ5_PRIORITY 2
|
||||
|
||||
#define IRQ6_IRQ 14
|
||||
#define IRQ6_IPR_ADDR INTC_INTPRI
|
||||
#define IRQ6_IPR_POS 1
|
||||
#define IRQ6_PRIORITY 2
|
||||
|
||||
#define IRQ7_IRQ 0
|
||||
#define IRQ7_IPR_ADDR INTC_INTPRI
|
||||
#define IRQ7_IPR_POS 0
|
||||
#define IRQ7_PRIORITY 2
|
||||
|
||||
/* TMU */
|
||||
/* ch0 */
|
||||
#define TMU_IRQ 28
|
||||
#define TMU_IPR_ADDR INTC_INT2PRI0
|
||||
#define TMU_IPR_POS 3
|
||||
#define TMU_PRIORITY 2
|
||||
|
||||
#define TIMER_IRQ 28
|
||||
#define TIMER_IPR_ADDR INTC_INT2PRI0
|
||||
#define TIMER_IPR_POS 3
|
||||
#define TIMER_PRIORITY 2
|
||||
|
||||
/* ch 1*/
|
||||
#define TMU_CH1_IRQ 29
|
||||
#define TMU_CH1_IPR_ADDR INTC_INT2PRI0
|
||||
#define TMU_CH1_IPR_POS 2
|
||||
#define TMU_CH1_PRIORITY 2
|
||||
|
||||
#define TIMER1_IRQ 29
|
||||
#define TIMER1_IPR_ADDR INTC_INT2PRI0
|
||||
#define TIMER1_IPR_POS 2
|
||||
#define TIMER1_PRIORITY 2
|
||||
|
||||
/* ch 2*/
|
||||
#define TMU_CH2_IRQ 30
|
||||
#define TMU_CH2_IPR_ADDR INTC_INT2PRI0
|
||||
#define TMU_CH2_IPR_POS 1
|
||||
#define TMU_CH2_PRIORITY 2
|
||||
/* ch 2 Input capture */
|
||||
#define TMU_CH2IC_IRQ 31
|
||||
#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0
|
||||
#define TMU_CH2IC_IPR_POS 0
|
||||
#define TMU_CH2IC_PRIORITY 2
|
||||
/* ch 3 */
|
||||
#define TMU_CH3_IRQ 96
|
||||
#define TMU_CH3_IPR_ADDR INTC_INT2PRI1
|
||||
#define TMU_CH3_IPR_POS 3
|
||||
#define TMU_CH3_PRIORITY 2
|
||||
/* ch 4 */
|
||||
#define TMU_CH4_IRQ 97
|
||||
#define TMU_CH4_IPR_ADDR INTC_INT2PRI1
|
||||
#define TMU_CH4_IPR_POS 2
|
||||
#define TMU_CH4_PRIORITY 2
|
||||
/* ch 5*/
|
||||
#define TMU_CH5_IRQ 98
|
||||
#define TMU_CH5_IPR_ADDR INTC_INT2PRI1
|
||||
#define TMU_CH5_IPR_POS 1
|
||||
#define TMU_CH5_PRIORITY 2
|
||||
|
||||
/* SCIF0 */
|
||||
#define SCIF0_ERI_IRQ 40
|
||||
#define SCIF0_RXI_IRQ 41
|
||||
#define SCIF0_BRI_IRQ 42
|
||||
#define SCIF0_TXI_IRQ 43
|
||||
#define SCIF0_IPR_ADDR INTC_INT2PRI2
|
||||
#define SCIF0_IPR_POS 3
|
||||
#define SCIF0_PRIORITY 3
|
||||
|
||||
/* SCIF1 */
|
||||
#define SCIF1_ERI_IRQ 76
|
||||
#define SCIF1_RXI_IRQ 77
|
||||
#define SCIF1_BRI_IRQ 78
|
||||
#define SCIF1_TXI_IRQ 79
|
||||
#define SCIF1_IPR_ADDR INTC_INT2PRI2
|
||||
#define SCIF1_IPR_POS 2
|
||||
#define SCIF1_PRIORITY 3
|
||||
|
||||
#define WDT_IRQ 27
|
||||
#define WDT_IPR_ADDR INTC_INT2PRI2
|
||||
#define WDT_IPR_POS 1
|
||||
#define WDT_PRIORITY 2
|
||||
|
||||
/* DMAC(0) */
|
||||
#define DMINT0_IRQ 34
|
||||
#define DMINT1_IRQ 35
|
||||
#define DMINT2_IRQ 36
|
||||
#define DMINT3_IRQ 37
|
||||
#define DMINT4_IRQ 44
|
||||
#define DMINT5_IRQ 45
|
||||
#define DMINT6_IRQ 46
|
||||
#define DMINT7_IRQ 47
|
||||
#define DMAE_IRQ 38
|
||||
#define DMA0_IPR_ADDR INTC_INT2PRI3
|
||||
#define DMA0_IPR_POS 2
|
||||
#define DMA0_PRIORITY 7
|
||||
|
||||
/* DMAC(1) */
|
||||
#define DMINT8_IRQ 92
|
||||
#define DMINT9_IRQ 93
|
||||
#define DMINT10_IRQ 94
|
||||
#define DMINT11_IRQ 95
|
||||
#define DMA1_IPR_ADDR INTC_INT2PRI3
|
||||
#define DMA1_IPR_POS 1
|
||||
#define DMA1_PRIORITY 7
|
||||
|
||||
#define DMTE0_IRQ DMINT0_IRQ
|
||||
#define DMTE4_IRQ DMINT4_IRQ
|
||||
#define DMA_IPR_ADDR DMA0_IPR_ADDR
|
||||
#define DMA_IPR_POS DMA0_IPR_POS
|
||||
#define DMA_PRIORITY DMA0_PRIORITY
|
||||
|
||||
/* CMT */
|
||||
#define CMT_IRQ 56
|
||||
#define CMT_IPR_ADDR INTC_INT2PRI4
|
||||
#define CMT_IPR_POS 3
|
||||
#define CMT_PRIORITY 0
|
||||
|
||||
/* HAC */
|
||||
#define HAC_IRQ 60
|
||||
#define HAC_IPR_ADDR INTC_INT2PRI4
|
||||
#define HAC_IPR_POS 2
|
||||
#define CMT_PRIORITY 0
|
||||
|
||||
/* PCIC(0) */
|
||||
#define PCIC0_IRQ 64
|
||||
#define PCIC0_IPR_ADDR INTC_INT2PRI4
|
||||
#define PCIC0_IPR_POS 1
|
||||
#define PCIC0_PRIORITY 2
|
||||
|
||||
/* PCIC(1) */
|
||||
#define PCIC1_IRQ 65
|
||||
#define PCIC1_IPR_ADDR INTC_INT2PRI4
|
||||
#define PCIC1_IPR_POS 0
|
||||
#define PCIC1_PRIORITY 2
|
||||
|
||||
/* PCIC(2) */
|
||||
#define PCIC2_IRQ 66
|
||||
#define PCIC2_IPR_ADDR INTC_INT2PRI5
|
||||
#define PCIC2_IPR_POS 3
|
||||
#define PCIC2_PRIORITY 2
|
||||
|
||||
/* PCIC(3) */
|
||||
#define PCIC3_IRQ 67
|
||||
#define PCIC3_IPR_ADDR INTC_INT2PRI5
|
||||
#define PCIC3_IPR_POS 2
|
||||
#define PCIC3_PRIORITY 2
|
||||
|
||||
/* PCIC(4) */
|
||||
#define PCIC4_IRQ 68
|
||||
#define PCIC4_IPR_ADDR INTC_INT2PRI5
|
||||
#define PCIC4_IPR_POS 1
|
||||
#define PCIC4_PRIORITY 2
|
||||
|
||||
/* PCIC(5) */
|
||||
#define PCICERR_IRQ 69
|
||||
#define PCICPWD3_IRQ 70
|
||||
#define PCICPWD2_IRQ 71
|
||||
#define PCICPWD1_IRQ 72
|
||||
#define PCICPWD0_IRQ 73
|
||||
#define PCIC5_IPR_ADDR INTC_INT2PRI5
|
||||
#define PCIC5_IPR_POS 0
|
||||
#define PCIC5_PRIORITY 2
|
||||
|
||||
/* SIOF */
|
||||
#define SIOF_IRQ 80
|
||||
#define SIOF_IPR_ADDR INTC_INT2PRI6
|
||||
#define SIOF_IPR_POS 3
|
||||
#define SIOF_PRIORITY 3
|
||||
|
||||
/* HSPI */
|
||||
#define HSPI_IRQ 84
|
||||
#define HSPI_IPR_ADDR INTC_INT2PRI6
|
||||
#define HSPI_IPR_POS 2
|
||||
#define HSPI_PRIORITY 3
|
||||
|
||||
/* MMCIF */
|
||||
#define MMCIF_FSTAT_IRQ 88
|
||||
#define MMCIF_TRAN_IRQ 89
|
||||
#define MMCIF_ERR_IRQ 90
|
||||
#define MMCIF_FRDY_IRQ 91
|
||||
#define MMCIF_IPR_ADDR INTC_INT2PRI6
|
||||
#define MMCIF_IPR_POS 1
|
||||
#define HSPI_PRIORITY 3
|
||||
|
||||
/* SSI */
|
||||
#define SSI_IRQ 100
|
||||
#define SSI_IPR_ADDR INTC_INT2PRI6
|
||||
#define SSI_IPR_POS 0
|
||||
#define SSI_PRIORITY 3
|
||||
|
||||
/* FLCTL */
|
||||
#define FLCTL_FLSTE_IRQ 104
|
||||
#define FLCTL_FLTEND_IRQ 105
|
||||
#define FLCTL_FLTRQ0_IRQ 106
|
||||
#define FLCTL_FLTRQ1_IRQ 107
|
||||
#define FLCTL_IPR_ADDR INTC_INT2PRI7
|
||||
#define FLCTL_IPR_POS 3
|
||||
#define FLCTL_PRIORITY 3
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO0_IRQ 108
|
||||
#define GPIO1_IRQ 109
|
||||
#define GPIO2_IRQ 110
|
||||
#define GPIO3_IRQ 111
|
||||
#define GPIO_IPR_ADDR INTC_INT2PRI7
|
||||
#define GPIO_IPR_POS 2
|
||||
#define GPIO_PRIORITY 3
|
||||
|
||||
#define INTC_TMU0_MSK 0
|
||||
#define INTC_TMU3_MSK 1
|
||||
#define INTC_RTC_MSK 2
|
||||
#define INTC_SCIF0_MSK 3
|
||||
#define INTC_SCIF1_MSK 4
|
||||
#define INTC_WDT_MSK 5
|
||||
#define INTC_HUID_MSK 7
|
||||
#define INTC_DMAC0_MSK 8
|
||||
#define INTC_DMAC1_MSK 9
|
||||
#define INTC_CMT_MSK 12
|
||||
#define INTC_HAC_MSK 13
|
||||
#define INTC_PCIC0_MSK 14
|
||||
#define INTC_PCIC1_MSK 15
|
||||
#define INTC_PCIC2_MSK 16
|
||||
#define INTC_PCIC3_MSK 17
|
||||
#define INTC_PCIC4_MSK 18
|
||||
#define INTC_PCIC5_MSK 19
|
||||
#define INTC_SIOF_MSK 20
|
||||
#define INTC_HSPI_MSK 21
|
||||
#define INTC_MMCIF_MSK 22
|
||||
#define INTC_SSI_MSK 23
|
||||
#define INTC_FLCTL_MSK 24
|
||||
#define INTC_GPIO_MSK 25
|
||||
|
||||
#endif /* __ASM_SH_IRQ_SH7780_H */
|
||||
@ -1,265 +1,9 @@
|
||||
#ifndef __ASM_SH_IRQ_H
|
||||
#define __ASM_SH_IRQ_H
|
||||
|
||||
/*
|
||||
*
|
||||
* linux/include/asm-sh/irq.h
|
||||
*
|
||||
* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
|
||||
* Copyright (C) 2000 Kazumoto Kojima
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/machvec.h>
|
||||
#include <asm/ptrace.h> /* for pt_regs */
|
||||
|
||||
#if defined(CONFIG_CPU_SH2)
|
||||
#include <asm/cpu/irq.h>
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SH7780
|
||||
|
||||
#define INTC_DMAC0_MSK 0
|
||||
|
||||
#if defined(CONFIG_CPU_SH3)
|
||||
#define INTC_IPRA 0xfffffee2UL
|
||||
#define INTC_IPRB 0xfffffee4UL
|
||||
#elif defined(CONFIG_CPU_SH4)
|
||||
#define INTC_IPRA 0xffd00004UL
|
||||
#define INTC_IPRB 0xffd00008UL
|
||||
#define INTC_IPRC 0xffd0000cUL
|
||||
#define INTC_IPRD 0xffd00010UL
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
#ifdef CONFIG_SH_CMT
|
||||
#define TIMER_IRQ CMI0_IRQ
|
||||
#define TIMER_IPR_ADDR INTC_IPR08
|
||||
#define TIMER_IPR_POS 3
|
||||
#define TIMER_PRIORITY 2
|
||||
|
||||
#define TIMER1_IRQ CMI1_IRQ
|
||||
#define TIMER1_IPR_ADDR INTC_IPR08
|
||||
#define TIMER1_IPR_POS 2
|
||||
#define TIMER1_PRIORITY 2
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
|
||||
#define TIMER_IRQ CMI0_IRQ
|
||||
#define TIMER_IPR_ADDR INTC_IPRC
|
||||
#define TIMER_IPR_POS 1
|
||||
#define TIMER_PRIORITY 2
|
||||
|
||||
#define TIMER1_IRQ CMI1_IRQ
|
||||
#define TIMER1_IPR_ADDR INTC_IPRC
|
||||
#define TIMER1_IPR_POS 0
|
||||
#define TIMER1_PRIORITY 4
|
||||
|
||||
#else
|
||||
#define TIMER_IRQ 16
|
||||
#define TIMER_IPR_ADDR INTC_IPRA
|
||||
#define TIMER_IPR_POS 3
|
||||
#define TIMER_PRIORITY 2
|
||||
|
||||
#define TIMER1_IRQ 17
|
||||
#define TIMER1_IPR_ADDR INTC_IPRA
|
||||
#define TIMER1_IPR_POS 2
|
||||
#define TIMER1_PRIORITY 4
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_CPU_SH2)
|
||||
#define RTC_IRQ 22
|
||||
#define RTC_IPR_ADDR INTC_IPRA
|
||||
#define RTC_IPR_POS 0
|
||||
#define RTC_PRIORITY TIMER_PRIORITY
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SH3)
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE1_IRQ 49
|
||||
#define DMTE2_IRQ 50
|
||||
#define DMTE3_IRQ 51
|
||||
#define DMA_IPR_ADDR INTC_IPRE
|
||||
#define DMA_IPR_POS 3
|
||||
#define DMA_PRIORITY 7
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
/* TMU2 */
|
||||
#define TIMER2_IRQ 18
|
||||
#define TIMER2_IPR_ADDR INTC_IPRA
|
||||
#define TIMER2_IPR_POS 1
|
||||
#define TIMER2_PRIORITY 2
|
||||
|
||||
/* WDT */
|
||||
#define WDT_IRQ 27
|
||||
#define WDT_IPR_ADDR INTC_IPRB
|
||||
#define WDT_IPR_POS 3
|
||||
#define WDT_PRIORITY 2
|
||||
|
||||
/* SIM (SIM Card Module) */
|
||||
#define SIM_ERI_IRQ 23
|
||||
#define SIM_RXI_IRQ 24
|
||||
#define SIM_TXI_IRQ 25
|
||||
#define SIM_TEND_IRQ 26
|
||||
#define SIM_IPR_ADDR INTC_IPRB
|
||||
#define SIM_IPR_POS 1
|
||||
#define SIM_PRIORITY 2
|
||||
|
||||
/* VIO (Video I/O) */
|
||||
#define VIO_IRQ 52
|
||||
#define VIO_IPR_ADDR INTC_IPRE
|
||||
#define VIO_IPR_POS 2
|
||||
#define VIO_PRIORITY 2
|
||||
|
||||
/* MFI (Multi Functional Interface) */
|
||||
#define MFI_IRQ 56
|
||||
#define MFI_IPR_ADDR INTC_IPRE
|
||||
#define MFI_IPR_POS 1
|
||||
#define MFI_PRIORITY 2
|
||||
|
||||
/* VPU (Video Processing Unit) */
|
||||
#define VPU_IRQ 60
|
||||
#define VPU_IPR_ADDR INTC_IPRE
|
||||
#define VPU_IPR_POS 0
|
||||
#define VPU_PRIORITY 2
|
||||
|
||||
/* KEY (Key Scan Interface) */
|
||||
#define KEY_IRQ 79
|
||||
#define KEY_IPR_ADDR INTC_IPRF
|
||||
#define KEY_IPR_POS 3
|
||||
#define KEY_PRIORITY 2
|
||||
|
||||
/* CMT (Compare Match Timer) */
|
||||
#define CMT_IRQ 104
|
||||
#define CMT_IPR_ADDR INTC_IPRF
|
||||
#define CMT_IPR_POS 0
|
||||
#define CMT_PRIORITY 2
|
||||
|
||||
/* DMAC(1) */
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE1_IRQ 49
|
||||
#define DMTE2_IRQ 50
|
||||
#define DMTE3_IRQ 51
|
||||
#define DMA1_IPR_ADDR INTC_IPRE
|
||||
#define DMA1_IPR_POS 3
|
||||
#define DMA1_PRIORITY 7
|
||||
|
||||
/* DMAC(2) */
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMTE5_IRQ 77
|
||||
#define DMA2_IPR_ADDR INTC_IPRF
|
||||
#define DMA2_IPR_POS 2
|
||||
#define DMA2_PRIORITY 7
|
||||
|
||||
/* SIOF0 */
|
||||
#define SIOF0_IRQ 84
|
||||
#define SIOF0_IPR_ADDR INTC_IPRH
|
||||
#define SIOF0_IPR_POS 3
|
||||
#define SIOF0_PRIORITY 3
|
||||
|
||||
/* FLCTL (Flash Memory Controller) */
|
||||
#define FLSTE_IRQ 92
|
||||
#define FLTEND_IRQ 93
|
||||
#define FLTRQ0_IRQ 94
|
||||
#define FLTRQ1_IRQ 95
|
||||
#define FLCTL_IPR_ADDR INTC_IPRH
|
||||
#define FLCTL_IPR_POS 1
|
||||
#define FLCTL_PRIORITY 3
|
||||
|
||||
/* IIC (IIC Bus Interface) */
|
||||
#define IIC_ALI_IRQ 96
|
||||
#define IIC_TACKI_IRQ 97
|
||||
#define IIC_WAITI_IRQ 98
|
||||
#define IIC_DTEI_IRQ 99
|
||||
#define IIC_IPR_ADDR INTC_IPRH
|
||||
#define IIC_IPR_POS 0
|
||||
#define IIC_PRIORITY 3
|
||||
|
||||
/* SIO0 */
|
||||
#define SIO0_IRQ 88
|
||||
#define SIO0_IPR_ADDR INTC_IPRI
|
||||
#define SIO0_IPR_POS 3
|
||||
#define SIO0_PRIORITY 3
|
||||
|
||||
/* SIU (Sound Interface Unit) */
|
||||
#define SIU_IRQ 108
|
||||
#define SIU_IPR_ADDR INTC_IPRJ
|
||||
#define SIU_IPR_POS 1
|
||||
#define SIU_PRIORITY 3
|
||||
|
||||
#endif
|
||||
#elif defined(CONFIG_CPU_SH4)
|
||||
#define DMTE0_IRQ 34
|
||||
#define DMTE1_IRQ 35
|
||||
#define DMTE2_IRQ 36
|
||||
#define DMTE3_IRQ 37
|
||||
#define DMTE4_IRQ 44 /* 7751R only */
|
||||
#define DMTE5_IRQ 45 /* 7751R only */
|
||||
#define DMTE6_IRQ 46 /* 7751R only */
|
||||
#define DMTE7_IRQ 47 /* 7751R only */
|
||||
#define DMAE_IRQ 38
|
||||
#define DMA_IPR_ADDR INTC_IPRC
|
||||
#define DMA_IPR_POS 2
|
||||
#define DMA_PRIORITY 7
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
|
||||
defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
|
||||
defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
|
||||
#define SCI_ERI_IRQ 23
|
||||
#define SCI_RXI_IRQ 24
|
||||
#define SCI_TXI_IRQ 25
|
||||
#define SCI_IPR_ADDR INTC_IPRB
|
||||
#define SCI_IPR_POS 1
|
||||
#define SCI_PRIORITY 3
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
#define SCIF0_IRQ 80
|
||||
#define SCIF0_IPR_ADDR INTC_IPRG
|
||||
#define SCIF0_IPR_POS 3
|
||||
#define SCIF0_PRIORITY 3
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
#define SCIF_ERI_IRQ 56
|
||||
#define SCIF_RXI_IRQ 57
|
||||
#define SCIF_BRI_IRQ 58
|
||||
#define SCIF_TXI_IRQ 59
|
||||
#define SCIF_IPR_ADDR INTC_IPRE
|
||||
#define SCIF_IPR_POS 1
|
||||
#define SCIF_PRIORITY 3
|
||||
|
||||
#define IRDA_ERI_IRQ 52
|
||||
#define IRDA_RXI_IRQ 53
|
||||
#define IRDA_BRI_IRQ 54
|
||||
#define IRDA_TXI_IRQ 55
|
||||
#define IRDA_IPR_ADDR INTC_IPRE
|
||||
#define IRDA_IPR_POS 2
|
||||
#define IRDA_PRIORITY 3
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||
#define SCIF_ERI_IRQ 40
|
||||
#define SCIF_RXI_IRQ 41
|
||||
#define SCIF_BRI_IRQ 42
|
||||
#define SCIF_TXI_IRQ 43
|
||||
#define SCIF_IPR_ADDR INTC_IPRC
|
||||
#define SCIF_IPR_POS 1
|
||||
#define SCIF_PRIORITY 3
|
||||
#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
|
||||
#define SCIF1_ERI_IRQ 23
|
||||
#define SCIF1_RXI_IRQ 24
|
||||
#define SCIF1_BRI_IRQ 25
|
||||
#define SCIF1_TXI_IRQ 26
|
||||
#define SCIF1_IPR_ADDR INTC_IPRB
|
||||
#define SCIF1_IPR_POS 1
|
||||
#define SCIF1_PRIORITY 3
|
||||
#endif /* ST40STB1 */
|
||||
|
||||
#endif /* 775x / SH4-202 / ST40STB1 */
|
||||
#endif /* 7780 */
|
||||
|
||||
/* NR_IRQS is made from three components:
|
||||
* 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
|
||||
* 2. PINT_NR_IRQS - number of PINT interrupts
|
||||
@ -348,50 +92,12 @@
|
||||
/* NR_IRQS. 1+2+3 */
|
||||
#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
|
||||
|
||||
extern void disable_irq(unsigned int);
|
||||
extern void disable_irq_nosync(unsigned int);
|
||||
extern void enable_irq(unsigned int);
|
||||
|
||||
/*
|
||||
* Simple Mask Register Support
|
||||
*/
|
||||
extern void make_maskreg_irq(unsigned int irq);
|
||||
extern unsigned short *irq_mask_register;
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
|
||||
#define IRQ0_IRQ 16
|
||||
#define IRQ1_IRQ 17
|
||||
#define IRQ2_IRQ 18
|
||||
#define IRQ3_IRQ 19
|
||||
#define IRQ4_IRQ 32
|
||||
#define IRQ5_IRQ 33
|
||||
#define IRQ6_IRQ 34
|
||||
#define IRQ7_IRQ 35
|
||||
#elif !defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
#define IRQ0_IRQ 32
|
||||
#define IRQ1_IRQ 33
|
||||
#define IRQ2_IRQ 34
|
||||
#define IRQ3_IRQ 35
|
||||
#define IRQ4_IRQ 36
|
||||
#define IRQ5_IRQ 37
|
||||
#endif
|
||||
|
||||
#define IRQ0_PRIORITY 1
|
||||
#define IRQ1_PRIORITY 1
|
||||
#define IRQ2_PRIORITY 1
|
||||
#define IRQ3_PRIORITY 1
|
||||
#define IRQ4_PRIORITY 1
|
||||
#define IRQ5_PRIORITY 1
|
||||
|
||||
#ifndef IRQ0_IPR_POS
|
||||
#define IRQ0_IPR_POS 0
|
||||
#define IRQ1_IPR_POS 1
|
||||
#define IRQ2_IPR_POS 2
|
||||
#define IRQ3_IPR_POS 3
|
||||
#define IRQ4_IPR_POS 0
|
||||
#define IRQ5_IPR_POS 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PINT IRQs
|
||||
*/
|
||||
@ -410,350 +116,6 @@ struct ipr_data {
|
||||
extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
|
||||
extern void make_imask_irq(unsigned int irq);
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
#undef INTC_IPRA
|
||||
#undef INTC_IPRB
|
||||
#define INTC_IPRA 0xA414FEE2UL
|
||||
#define INTC_IPRB 0xA414FEE4UL
|
||||
#define INTC_IPRC 0xA4140016UL
|
||||
#define INTC_IPRD 0xA4140018UL
|
||||
#define INTC_IPRE 0xA414001AUL
|
||||
#define INTC_IPRF 0xA4080000UL
|
||||
#define INTC_IPRG 0xA4080002UL
|
||||
#define INTC_IPRH 0xA4080004UL
|
||||
#define INTC_IPRI 0xA4080006UL
|
||||
#define INTC_IPRJ 0xA4080008UL
|
||||
|
||||
#define INTC_IMR0 0xA4080040UL
|
||||
#define INTC_IMR1 0xA4080042UL
|
||||
#define INTC_IMR2 0xA4080044UL
|
||||
#define INTC_IMR3 0xA4080046UL
|
||||
#define INTC_IMR4 0xA4080048UL
|
||||
#define INTC_IMR5 0xA408004AUL
|
||||
#define INTC_IMR6 0xA408004CUL
|
||||
#define INTC_IMR7 0xA408004EUL
|
||||
#define INTC_IMR8 0xA4080050UL
|
||||
#define INTC_IMR9 0xA4080052UL
|
||||
#define INTC_IMR10 0xA4080054UL
|
||||
|
||||
#define INTC_IMCR0 0xA4080060UL
|
||||
#define INTC_IMCR1 0xA4080062UL
|
||||
#define INTC_IMCR2 0xA4080064UL
|
||||
#define INTC_IMCR3 0xA4080066UL
|
||||
#define INTC_IMCR4 0xA4080068UL
|
||||
#define INTC_IMCR5 0xA408006AUL
|
||||
#define INTC_IMCR6 0xA408006CUL
|
||||
#define INTC_IMCR7 0xA408006EUL
|
||||
#define INTC_IMCR8 0xA4080070UL
|
||||
#define INTC_IMCR9 0xA4080072UL
|
||||
#define INTC_IMCR10 0xA4080074UL
|
||||
|
||||
#define INTC_ICR0 0xA414FEE0UL
|
||||
#define INTC_ICR1 0xA4140010UL
|
||||
|
||||
#define INTC_IRR0 0xA4140004UL
|
||||
|
||||
#define PORT_PACR 0xA4050100UL
|
||||
#define PORT_PBCR 0xA4050102UL
|
||||
#define PORT_PCCR 0xA4050104UL
|
||||
#define PORT_PDCR 0xA4050106UL
|
||||
#define PORT_PECR 0xA4050108UL
|
||||
#define PORT_PFCR 0xA405010AUL
|
||||
#define PORT_PGCR 0xA405010CUL
|
||||
#define PORT_PHCR 0xA405010EUL
|
||||
#define PORT_PJCR 0xA4050110UL
|
||||
#define PORT_PKCR 0xA4050112UL
|
||||
#define PORT_PLCR 0xA4050114UL
|
||||
#define PORT_SCPCR 0xA4050116UL
|
||||
#define PORT_PMCR 0xA4050118UL
|
||||
#define PORT_PNCR 0xA405011AUL
|
||||
#define PORT_PQCR 0xA405011CUL
|
||||
|
||||
#define PORT_PSELA 0xA4050140UL
|
||||
#define PORT_PSELB 0xA4050142UL
|
||||
#define PORT_PSELC 0xA4050144UL
|
||||
|
||||
#define PORT_HIZCRA 0xA4050146UL
|
||||
#define PORT_HIZCRB 0xA4050148UL
|
||||
#define PORT_DRVCR 0xA4050150UL
|
||||
|
||||
#define PORT_PADR 0xA4050120UL
|
||||
#define PORT_PBDR 0xA4050122UL
|
||||
#define PORT_PCDR 0xA4050124UL
|
||||
#define PORT_PDDR 0xA4050126UL
|
||||
#define PORT_PEDR 0xA4050128UL
|
||||
#define PORT_PFDR 0xA405012AUL
|
||||
#define PORT_PGDR 0xA405012CUL
|
||||
#define PORT_PHDR 0xA405012EUL
|
||||
#define PORT_PJDR 0xA4050130UL
|
||||
#define PORT_PKDR 0xA4050132UL
|
||||
#define PORT_PLDR 0xA4050134UL
|
||||
#define PORT_SCPDR 0xA4050136UL
|
||||
#define PORT_PMDR 0xA4050138UL
|
||||
#define PORT_PNDR 0xA405013AUL
|
||||
#define PORT_PQDR 0xA405013CUL
|
||||
|
||||
#define IRQ0_IRQ 32
|
||||
#define IRQ1_IRQ 33
|
||||
#define IRQ2_IRQ 34
|
||||
#define IRQ3_IRQ 35
|
||||
#define IRQ4_IRQ 36
|
||||
#define IRQ5_IRQ 37
|
||||
|
||||
#define IRQ0_IPR_ADDR INTC_IPRC
|
||||
#define IRQ1_IPR_ADDR INTC_IPRC
|
||||
#define IRQ2_IPR_ADDR INTC_IPRC
|
||||
#define IRQ3_IPR_ADDR INTC_IPRC
|
||||
#define IRQ4_IPR_ADDR INTC_IPRD
|
||||
#define IRQ5_IPR_ADDR INTC_IPRD
|
||||
|
||||
#define IRQ0_IPR_POS 0
|
||||
#define IRQ1_IPR_POS 1
|
||||
#define IRQ2_IPR_POS 2
|
||||
#define IRQ3_IPR_POS 3
|
||||
#define IRQ4_IPR_POS 0
|
||||
#define IRQ5_IPR_POS 1
|
||||
|
||||
#define IRQ0_PRIORITY 1
|
||||
#define IRQ1_PRIORITY 1
|
||||
#define IRQ2_PRIORITY 1
|
||||
#define IRQ3_PRIORITY 1
|
||||
#define IRQ4_PRIORITY 1
|
||||
#define IRQ5_PRIORITY 1
|
||||
|
||||
extern int ipr_irq_demux(int irq);
|
||||
#define __irq_demux(irq) ipr_irq_demux(irq)
|
||||
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
|
||||
#define INTC_IPRA 0xfffffee2UL
|
||||
#define INTC_IPRB 0xfffffe60UL
|
||||
|
||||
#define INTC_VCRA 0xfffffe62UL
|
||||
#define INTC_VCRB 0xfffffe64UL
|
||||
#define INTC_VCRC 0xfffffe66UL
|
||||
#define INTC_VCRD 0xfffffe68UL
|
||||
|
||||
#define INTC_VCRWDT 0xfffffee4UL
|
||||
#define INTC_VCRDIV 0xffffff0cUL
|
||||
#define INTC_VCRDMA0 0xffffffa0UL
|
||||
#define INTC_VCRDMA1 0xffffffa8UL
|
||||
|
||||
#define INTC_ICR 0xfffffee0UL
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#define INTC_IRR0 0xa4000004UL
|
||||
#define INTC_IRR1 0xa4000006UL
|
||||
#define INTC_IRR2 0xa4000008UL
|
||||
|
||||
#define INTC_ICR0 0xfffffee0UL
|
||||
#define INTC_ICR1 0xa4000010UL
|
||||
#define INTC_ICR2 0xa4000012UL
|
||||
#define INTC_INTER 0xa4000014UL
|
||||
|
||||
#define INTC_IPRC 0xa4000016UL
|
||||
#define INTC_IPRD 0xa4000018UL
|
||||
#define INTC_IPRE 0xa400001aUL
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
|
||||
#define INTC_IPRF 0xa400001cUL
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#define INTC_IPRF 0xa4080000UL
|
||||
#define INTC_IPRG 0xa4080002UL
|
||||
#define INTC_IPRH 0xa4080004UL
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
/* Interrupt Controller Registers */
|
||||
#undef INTC_IPRA
|
||||
#undef INTC_IPRB
|
||||
#define INTC_IPRA 0xA414FEE2UL
|
||||
#define INTC_IPRB 0xA414FEE4UL
|
||||
#define INTC_IPRF 0xA4080000UL
|
||||
#define INTC_IPRG 0xA4080002UL
|
||||
#define INTC_IPRH 0xA4080004UL
|
||||
#define INTC_IPRI 0xA4080006UL
|
||||
|
||||
#undef INTC_ICR0
|
||||
#undef INTC_ICR1
|
||||
#define INTC_ICR0 0xA414FEE0UL
|
||||
#define INTC_ICR1 0xA4140010UL
|
||||
|
||||
#define INTC_IRR0 0xa4000004UL
|
||||
#define INTC_IRR1 0xa4000006UL
|
||||
#define INTC_IRR2 0xa4000008UL
|
||||
#define INTC_IRR3 0xa400000AUL
|
||||
#define INTC_IRR4 0xa400000CUL
|
||||
#define INTC_IRR5 0xa4080020UL
|
||||
#define INTC_IRR7 0xa4080024UL
|
||||
#define INTC_IRR8 0xa4080026UL
|
||||
|
||||
/* Interrupt numbers */
|
||||
#define TIMER2_IRQ 18
|
||||
#define TIMER2_IPR_ADDR INTC_IPRA
|
||||
#define TIMER2_IPR_POS 1
|
||||
#define TIMER2_PRIORITY 2
|
||||
|
||||
/* WDT */
|
||||
#define WDT_IRQ 27
|
||||
#define WDT_IPR_ADDR INTC_IPRB
|
||||
#define WDT_IPR_POS 3
|
||||
#define WDT_PRIORITY 2
|
||||
|
||||
#define SCIF0_ERI_IRQ 52
|
||||
#define SCIF0_RXI_IRQ 53
|
||||
#define SCIF0_BRI_IRQ 54
|
||||
#define SCIF0_TXI_IRQ 55
|
||||
#define SCIF0_IPR_ADDR INTC_IPRE
|
||||
#define SCIF0_IPR_POS 2
|
||||
#define SCIF0_PRIORITY 3
|
||||
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMTE5_IRQ 77
|
||||
#define DMA2_IPR_ADDR INTC_IPRF
|
||||
#define DMA2_IPR_POS 2
|
||||
#define DMA2_PRIORITY 7
|
||||
|
||||
#define IPSEC_IRQ 79
|
||||
#define IPSEC_IPR_ADDR INTC_IPRF
|
||||
#define IPSEC_IPR_POS 3
|
||||
#define IPSEC_PRIORITY 3
|
||||
|
||||
/* EDMAC */
|
||||
#define EDMAC0_IRQ 80
|
||||
#define EDMAC0_IPR_ADDR INTC_IPRG
|
||||
#define EDMAC0_IPR_POS 3
|
||||
#define EDMAC0_PRIORITY 3
|
||||
|
||||
#define EDMAC1_IRQ 81
|
||||
#define EDMAC1_IPR_ADDR INTC_IPRG
|
||||
#define EDMAC1_IPR_POS 2
|
||||
#define EDMAC1_PRIORITY 3
|
||||
|
||||
#define EDMAC2_IRQ 82
|
||||
#define EDMAC2_IPR_ADDR INTC_IPRG
|
||||
#define EDMAC2_IPR_POS 1
|
||||
#define EDMAC2_PRIORITY 3
|
||||
|
||||
/* SIOF */
|
||||
#define SIOF0_ERI_IRQ 96
|
||||
#define SIOF0_TXI_IRQ 97
|
||||
#define SIOF0_RXI_IRQ 98
|
||||
#define SIOF0_CCI_IRQ 99
|
||||
#define SIOF0_IPR_ADDR INTC_IPRH
|
||||
#define SIOF0_IPR_POS 0
|
||||
#define SIOF0_PRIORITY 7
|
||||
|
||||
#define SIOF1_ERI_IRQ 100
|
||||
#define SIOF1_TXI_IRQ 101
|
||||
#define SIOF1_RXI_IRQ 102
|
||||
#define SIOF1_CCI_IRQ 103
|
||||
#define SIOF1_IPR_ADDR INTC_IPRI
|
||||
#define SIOF1_IPR_POS 1
|
||||
#define SIOF1_PRIORITY 7
|
||||
#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#define PORT_PACR 0xa4050100UL
|
||||
#define PORT_PBCR 0xa4050102UL
|
||||
#define PORT_PCCR 0xa4050104UL
|
||||
#define PORT_PETCR 0xa4050106UL
|
||||
#define PORT_PADR 0xa4050120UL
|
||||
#define PORT_PBDR 0xa4050122UL
|
||||
#define PORT_PCDR 0xa4050124UL
|
||||
#else
|
||||
#define PORT_PACR 0xa4000100UL
|
||||
#define PORT_PBCR 0xa4000102UL
|
||||
#define PORT_PCCR 0xa4000104UL
|
||||
#define PORT_PFCR 0xa400010aUL
|
||||
#define PORT_PADR 0xa4000120UL
|
||||
#define PORT_PBDR 0xa4000122UL
|
||||
#define PORT_PCDR 0xa4000124UL
|
||||
#define PORT_PFDR 0xa400012aUL
|
||||
#endif
|
||||
|
||||
#define IRQ0_IRQ 32
|
||||
#define IRQ1_IRQ 33
|
||||
#define IRQ2_IRQ 34
|
||||
#define IRQ3_IRQ 35
|
||||
#define IRQ4_IRQ 36
|
||||
#define IRQ5_IRQ 37
|
||||
|
||||
#define IRQ0_IPR_ADDR INTC_IPRC
|
||||
#define IRQ1_IPR_ADDR INTC_IPRC
|
||||
#define IRQ2_IPR_ADDR INTC_IPRC
|
||||
#define IRQ3_IPR_ADDR INTC_IPRC
|
||||
#define IRQ4_IPR_ADDR INTC_IPRD
|
||||
#define IRQ5_IPR_ADDR INTC_IPRD
|
||||
|
||||
#define IRQ0_IPR_POS 0
|
||||
#define IRQ1_IPR_POS 1
|
||||
#define IRQ2_IPR_POS 2
|
||||
#define IRQ3_IPR_POS 3
|
||||
#define IRQ4_IPR_POS 0
|
||||
#define IRQ5_IPR_POS 1
|
||||
|
||||
#define IRQ0_PRIORITY 1
|
||||
#define IRQ1_PRIORITY 1
|
||||
#define IRQ2_PRIORITY 1
|
||||
#define IRQ3_PRIORITY 1
|
||||
#define IRQ4_PRIORITY 1
|
||||
#define IRQ5_PRIORITY 1
|
||||
|
||||
#define PINT0_IRQ 40
|
||||
#define PINT8_IRQ 41
|
||||
|
||||
#define PINT0_IPR_ADDR INTC_IPRD
|
||||
#define PINT8_IPR_ADDR INTC_IPRD
|
||||
|
||||
#define PINT0_IPR_POS 3
|
||||
#define PINT8_IPR_POS 2
|
||||
#define PINT0_PRIORITY 2
|
||||
#define PINT8_PRIORITY 2
|
||||
|
||||
extern int ipr_irq_demux(int irq);
|
||||
#define __irq_demux(irq) ipr_irq_demux(irq)
|
||||
#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||
#define INTC_ICR 0xffd00000
|
||||
#define INTC_ICR_NMIL (1<<15)
|
||||
#define INTC_ICR_MAI (1<<14)
|
||||
#define INTC_ICR_NMIB (1<<9)
|
||||
#define INTC_ICR_NMIE (1<<8)
|
||||
#define INTC_ICR_IRLM (1<<7)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7780
|
||||
#include <asm/irq-sh7780.h>
|
||||
#endif
|
||||
|
||||
/* SH with INTC2-style interrupts */
|
||||
#ifdef CONFIG_CPU_HAS_INTC2_IRQ
|
||||
#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
|
||||
#define INTC2_BASE 0xfe080000
|
||||
#define INTC2_FIRST_IRQ 64
|
||||
#define INTC2_INTREQ_OFFSET 0x20
|
||||
#define INTC2_INTMSK_OFFSET 0x40
|
||||
#define INTC2_INTMSKCLR_OFFSET 0x60
|
||||
#define NR_INTC2_IRQS 25
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
#define INTC2_BASE 0xfe080000
|
||||
#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
|
||||
#define INTC2_INTREQ_OFFSET 0x20
|
||||
#define INTC2_INTMSK_OFFSET 0x40
|
||||
#define INTC2_INTMSKCLR_OFFSET 0x60
|
||||
#define NR_INTC2_IRQS 64
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#define INTC2_BASE 0xffd40000
|
||||
#define INTC2_FIRST_IRQ 21
|
||||
#define INTC2_INTMSK_OFFSET (0x38)
|
||||
#define INTC2_INTMSKCLR_OFFSET (0x3c)
|
||||
#define NR_INTC2_IRQS 60
|
||||
#endif
|
||||
|
||||
#define INTC2_INTPRI_OFFSET 0x00
|
||||
|
||||
struct intc2_data {
|
||||
unsigned short irq;
|
||||
unsigned char ipr_offset, ipr_shift;
|
||||
@ -763,20 +125,14 @@ struct intc2_data {
|
||||
|
||||
void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
|
||||
void init_IRQ_intc2(void);
|
||||
#endif
|
||||
|
||||
extern int shmse_irq_demux(int irq);
|
||||
|
||||
static inline int generic_irq_demux(int irq)
|
||||
{
|
||||
return irq;
|
||||
}
|
||||
|
||||
#ifndef __irq_demux
|
||||
#define __irq_demux(irq) (irq)
|
||||
#endif
|
||||
#define irq_canonicalize(irq) (irq)
|
||||
#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
|
||||
#define irq_demux(irq) sh_mv.mv_irq_demux(irq)
|
||||
|
||||
#ifdef CONFIG_4KSTACKS
|
||||
extern void irq_ctx_init(int cpu);
|
||||
@ -787,12 +143,4 @@ extern void irq_ctx_exit(int cpu);
|
||||
# define irq_ctx_exit(cpu) do { } while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH73180)
|
||||
#include <asm/irq-sh73180.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7343)
|
||||
#include <asm/irq-sh7343.h>
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_IRQ_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user