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net/mlx5: Accel, Add core IPsec support for the Connect-X family
This to set the base for downstream patches to support the new IPsec implementation of the Connect-X family. Following modifications made: - Remove accel layer dependency from MLX5_FPGA_IPSEC. - Introduce accel_ipsec_ops, each IPsec device will have to support these ops. Signed-off-by: Raed Salem <raeds@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Raed Salem
Saeed Mahameed
parent
ea2128fd63
commit
9a6ad1ad71
@ -31,37 +31,83 @@
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*
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*/
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#ifdef CONFIG_MLX5_FPGA_IPSEC
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#include <linux/mlx5/device.h>
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#include "accel/ipsec.h"
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#include "mlx5_core.h"
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#include "fpga/ipsec.h"
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void mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev)
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{
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mlx5_fpga_ipsec_ops(mdev);
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int err = 0;
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if (!ipsec_ops || !ipsec_ops->init) {
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mlx5_core_dbg(mdev, "IPsec ops is not supported\n");
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return;
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}
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err = ipsec_ops->init(mdev);
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if (err) {
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mlx5_core_warn_once(mdev, "Failed to start IPsec device, err = %d\n", err);
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return;
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}
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mdev->ipsec_ops = ipsec_ops;
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}
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void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
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{
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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if (!ipsec_ops || !ipsec_ops->cleanup)
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return;
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ipsec_ops->cleanup(mdev);
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}
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u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev)
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{
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return mlx5_fpga_ipsec_device_caps(mdev);
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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if (!ipsec_ops || !ipsec_ops->device_caps)
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return 0;
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return ipsec_ops->device_caps(mdev);
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}
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EXPORT_SYMBOL_GPL(mlx5_accel_ipsec_device_caps);
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unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev)
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{
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return mlx5_fpga_ipsec_counters_count(mdev);
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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if (!ipsec_ops || !ipsec_ops->counters_count)
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return -EOPNOTSUPP;
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return ipsec_ops->counters_count(mdev);
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}
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int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
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unsigned int count)
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{
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return mlx5_fpga_ipsec_counters_read(mdev, counters, count);
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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if (!ipsec_ops || !ipsec_ops->counters_read)
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return -EOPNOTSUPP;
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return ipsec_ops->counters_read(mdev, counters, count);
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}
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void *mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev,
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struct mlx5_accel_esp_xfrm *xfrm,
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u32 *sa_handle)
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{
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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__be32 saddr[4] = {}, daddr[4] = {};
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if (!ipsec_ops || !ipsec_ops->create_hw_context)
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return ERR_PTR(-EOPNOTSUPP);
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if (!xfrm->attrs.is_ipv6) {
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saddr[3] = xfrm->attrs.saddr.a4;
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daddr[3] = xfrm->attrs.daddr.a4;
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@ -70,29 +116,18 @@ void *mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev,
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memcpy(daddr, xfrm->attrs.daddr.a6, sizeof(daddr));
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}
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return mlx5_fpga_ipsec_create_sa_ctx(mdev, xfrm, saddr,
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daddr, xfrm->attrs.spi,
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xfrm->attrs.is_ipv6, sa_handle);
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return ipsec_ops->create_hw_context(mdev, xfrm, saddr, daddr, xfrm->attrs.spi,
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xfrm->attrs.is_ipv6, sa_handle);
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}
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void mlx5_accel_esp_free_hw_context(void *context)
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void mlx5_accel_esp_free_hw_context(struct mlx5_core_dev *mdev, void *context)
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{
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mlx5_fpga_ipsec_delete_sa_ctx(context);
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}
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev)
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{
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return mlx5_fpga_ipsec_init(mdev);
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}
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if (!ipsec_ops || !ipsec_ops->free_hw_context)
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return;
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void mlx5_accel_ipsec_build_fs_cmds(void)
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{
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mlx5_fpga_ipsec_build_fs_cmds();
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}
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void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
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{
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mlx5_fpga_ipsec_cleanup(mdev);
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ipsec_ops->free_hw_context(context);
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}
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struct mlx5_accel_esp_xfrm *
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@ -100,9 +135,13 @@ mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
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const struct mlx5_accel_esp_xfrm_attrs *attrs,
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u32 flags)
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{
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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struct mlx5_accel_esp_xfrm *xfrm;
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xfrm = mlx5_fpga_esp_create_xfrm(mdev, attrs, flags);
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if (!ipsec_ops || !ipsec_ops->esp_create_xfrm)
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return ERR_PTR(-EOPNOTSUPP);
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xfrm = ipsec_ops->esp_create_xfrm(mdev, attrs, flags);
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if (IS_ERR(xfrm))
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return xfrm;
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@ -113,15 +152,23 @@ EXPORT_SYMBOL_GPL(mlx5_accel_esp_create_xfrm);
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void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
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{
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mlx5_fpga_esp_destroy_xfrm(xfrm);
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const struct mlx5_accel_ipsec_ops *ipsec_ops = xfrm->mdev->ipsec_ops;
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if (!ipsec_ops || !ipsec_ops->esp_destroy_xfrm)
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return;
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ipsec_ops->esp_destroy_xfrm(xfrm);
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}
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EXPORT_SYMBOL_GPL(mlx5_accel_esp_destroy_xfrm);
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int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
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const struct mlx5_accel_esp_xfrm_attrs *attrs)
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{
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return mlx5_fpga_esp_modify_xfrm(xfrm, attrs);
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const struct mlx5_accel_ipsec_ops *ipsec_ops = xfrm->mdev->ipsec_ops;
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if (!ipsec_ops || !ipsec_ops->esp_modify_xfrm)
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return -EOPNOTSUPP;
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return ipsec_ops->esp_modify_xfrm(xfrm, attrs);
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}
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EXPORT_SYMBOL_GPL(mlx5_accel_esp_modify_xfrm);
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#endif
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@ -37,7 +37,7 @@
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/accel.h>
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#ifdef CONFIG_MLX5_FPGA_IPSEC
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#ifdef CONFIG_MLX5_ACCEL
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#define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \
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MLX5_ACCEL_IPSEC_CAP_DEVICE)
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@ -49,12 +49,30 @@ int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
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void *mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev,
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struct mlx5_accel_esp_xfrm *xfrm,
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u32 *sa_handle);
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void mlx5_accel_esp_free_hw_context(void *context);
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void mlx5_accel_esp_free_hw_context(struct mlx5_core_dev *mdev, void *context);
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int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev);
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void mlx5_accel_ipsec_build_fs_cmds(void);
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void mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev);
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void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev);
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struct mlx5_accel_ipsec_ops {
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u32 (*device_caps)(struct mlx5_core_dev *mdev);
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unsigned int (*counters_count)(struct mlx5_core_dev *mdev);
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int (*counters_read)(struct mlx5_core_dev *mdev, u64 *counters, unsigned int count);
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void* (*create_hw_context)(struct mlx5_core_dev *mdev,
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struct mlx5_accel_esp_xfrm *xfrm,
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const __be32 saddr[4], const __be32 daddr[4],
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const __be32 spi, bool is_ipv6, u32 *sa_handle);
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void (*free_hw_context)(void *context);
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int (*init)(struct mlx5_core_dev *mdev);
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void (*cleanup)(struct mlx5_core_dev *mdev);
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struct mlx5_accel_esp_xfrm* (*esp_create_xfrm)(struct mlx5_core_dev *mdev,
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const struct mlx5_accel_esp_xfrm_attrs *attrs,
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u32 flags);
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int (*esp_modify_xfrm)(struct mlx5_accel_esp_xfrm *xfrm,
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const struct mlx5_accel_esp_xfrm_attrs *attrs);
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void (*esp_destroy_xfrm)(struct mlx5_accel_esp_xfrm *xfrm);
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};
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#else
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#define MLX5_IPSEC_DEV(mdev) false
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@ -67,23 +85,12 @@ mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev,
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return NULL;
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}
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static inline void mlx5_accel_esp_free_hw_context(void *context)
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{
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}
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static inline void mlx5_accel_esp_free_hw_context(struct mlx5_core_dev *mdev, void *context) {}
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static inline int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev)
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{
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return 0;
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}
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static inline void mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev) {}
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static inline void mlx5_accel_ipsec_build_fs_cmds(void)
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{
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}
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static inline void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev) {}
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static inline void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
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{
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}
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#endif
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#endif /* CONFIG_MLX5_ACCEL */
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#endif /* __MLX5_ACCEL_IPSEC_H__ */
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@ -342,7 +342,7 @@ static int mlx5e_xfrm_add_state(struct xfrm_state *x)
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goto out;
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err_hw_ctx:
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mlx5_accel_esp_free_hw_context(sa_entry->hw_context);
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mlx5_accel_esp_free_hw_context(priv->mdev, sa_entry->hw_context);
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err_xfrm:
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mlx5_accel_esp_destroy_xfrm(sa_entry->xfrm);
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err_sa_entry:
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@ -372,7 +372,7 @@ static void mlx5e_xfrm_free_state(struct xfrm_state *x)
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if (sa_entry->hw_context) {
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flush_workqueue(sa_entry->ipsec->wq);
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mlx5_accel_esp_free_hw_context(sa_entry->hw_context);
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mlx5_accel_esp_free_hw_context(sa_entry->xfrm->mdev, sa_entry->hw_context);
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mlx5_accel_esp_destroy_xfrm(sa_entry->xfrm);
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}
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@ -359,7 +359,7 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
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return ret;
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}
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unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev)
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static unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev)
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{
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struct mlx5_fpga_device *fdev = mdev->fpga;
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@ -370,8 +370,8 @@ unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev)
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number_of_ipsec_counters);
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}
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int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
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unsigned int counters_count)
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static int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
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unsigned int counters_count)
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{
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struct mlx5_fpga_device *fdev = mdev->fpga;
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unsigned int i;
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@ -665,12 +665,10 @@ static bool mlx5_is_fpga_egress_ipsec_rule(struct mlx5_core_dev *dev,
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return true;
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}
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void *mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev,
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struct mlx5_accel_esp_xfrm *accel_xfrm,
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const __be32 saddr[4],
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const __be32 daddr[4],
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const __be32 spi, bool is_ipv6,
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u32 *sa_handle)
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static void *mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev,
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struct mlx5_accel_esp_xfrm *accel_xfrm,
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const __be32 saddr[4], const __be32 daddr[4],
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const __be32 spi, bool is_ipv6, u32 *sa_handle)
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{
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struct mlx5_fpga_ipsec_sa_ctx *sa_ctx;
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struct mlx5_fpga_esp_xfrm *fpga_xfrm =
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@ -862,7 +860,7 @@ mlx5_fpga_ipsec_release_sa_ctx(struct mlx5_fpga_ipsec_sa_ctx *sa_ctx)
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mutex_unlock(&fipsec->sa_hash_lock);
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}
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void mlx5_fpga_ipsec_delete_sa_ctx(void *context)
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static void mlx5_fpga_ipsec_delete_sa_ctx(void *context)
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{
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struct mlx5_fpga_esp_xfrm *fpga_xfrm =
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((struct mlx5_fpga_ipsec_sa_ctx *)context)->fpga_xfrm;
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@ -1264,7 +1262,7 @@ const struct mlx5_flow_cmds *mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flo
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}
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}
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int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev)
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static int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev)
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{
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struct mlx5_fpga_conn_attr init_attr = {0};
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struct mlx5_fpga_device *fdev = mdev->fpga;
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@ -1346,7 +1344,7 @@ static void destroy_rules_rb(struct rb_root *root)
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}
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}
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void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev)
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static void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev)
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{
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struct mlx5_fpga_device *fdev = mdev->fpga;
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@ -1451,7 +1449,7 @@ mlx5_fpga_esp_validate_xfrm_attrs(struct mlx5_core_dev *mdev,
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return 0;
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}
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struct mlx5_accel_esp_xfrm *
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static struct mlx5_accel_esp_xfrm *
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mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev,
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const struct mlx5_accel_esp_xfrm_attrs *attrs,
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u32 flags)
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@ -1479,7 +1477,7 @@ mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev,
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return &fpga_xfrm->accel_xfrm;
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}
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void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
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static void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
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{
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struct mlx5_fpga_esp_xfrm *fpga_xfrm =
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container_of(xfrm, struct mlx5_fpga_esp_xfrm,
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@ -1488,8 +1486,8 @@ void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
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kfree(fpga_xfrm);
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}
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int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
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const struct mlx5_accel_esp_xfrm_attrs *attrs)
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static int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
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const struct mlx5_accel_esp_xfrm_attrs *attrs)
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{
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struct mlx5_core_dev *mdev = xfrm->mdev;
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struct mlx5_fpga_device *fdev = mdev->fpga;
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@ -1560,3 +1558,24 @@ change_sw_xfrm_attrs:
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mutex_unlock(&fpga_xfrm->lock);
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return err;
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}
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static const struct mlx5_accel_ipsec_ops fpga_ipsec_ops = {
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.device_caps = mlx5_fpga_ipsec_device_caps,
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.counters_count = mlx5_fpga_ipsec_counters_count,
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.counters_read = mlx5_fpga_ipsec_counters_read,
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.create_hw_context = mlx5_fpga_ipsec_create_sa_ctx,
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.free_hw_context = mlx5_fpga_ipsec_delete_sa_ctx,
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.init = mlx5_fpga_ipsec_init,
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.cleanup = mlx5_fpga_ipsec_cleanup,
|
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.esp_create_xfrm = mlx5_fpga_esp_create_xfrm,
|
||||
.esp_modify_xfrm = mlx5_fpga_esp_modify_xfrm,
|
||||
.esp_destroy_xfrm = mlx5_fpga_esp_destroy_xfrm,
|
||||
};
|
||||
|
||||
const struct mlx5_accel_ipsec_ops *mlx5_fpga_ipsec_ops(struct mlx5_core_dev *mdev)
|
||||
{
|
||||
if (!mlx5_fpga_is_ipsec_device(mdev))
|
||||
return NULL;
|
||||
|
||||
return &fpga_ipsec_ops;
|
||||
}
|
||||
|
||||
@ -38,44 +38,23 @@
|
||||
#include "fs_cmd.h"
|
||||
|
||||
#ifdef CONFIG_MLX5_FPGA_IPSEC
|
||||
const struct mlx5_accel_ipsec_ops *mlx5_fpga_ipsec_ops(struct mlx5_core_dev *mdev);
|
||||
u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev);
|
||||
unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev);
|
||||
int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
|
||||
unsigned int counters_count);
|
||||
|
||||
void *mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev,
|
||||
struct mlx5_accel_esp_xfrm *accel_xfrm,
|
||||
const __be32 saddr[4],
|
||||
const __be32 daddr[4],
|
||||
const __be32 spi, bool is_ipv6,
|
||||
u32 *sa_handle);
|
||||
void mlx5_fpga_ipsec_delete_sa_ctx(void *context);
|
||||
|
||||
int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev);
|
||||
void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev);
|
||||
void mlx5_fpga_ipsec_build_fs_cmds(void);
|
||||
|
||||
struct mlx5_accel_esp_xfrm *
|
||||
mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev,
|
||||
const struct mlx5_accel_esp_xfrm_attrs *attrs,
|
||||
u32 flags);
|
||||
void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm);
|
||||
int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
|
||||
const struct mlx5_accel_esp_xfrm_attrs *attrs);
|
||||
|
||||
const struct mlx5_flow_cmds *
|
||||
mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type);
|
||||
void mlx5_fpga_ipsec_build_fs_cmds(void);
|
||||
#else
|
||||
static inline u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline
|
||||
const struct mlx5_accel_ipsec_ops *mlx5_fpga_ipsec_ops(struct mlx5_core_dev *mdev)
|
||||
{ return NULL; }
|
||||
static inline u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
|
||||
static inline const struct mlx5_flow_cmds *
|
||||
mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type)
|
||||
{
|
||||
return mlx5_fs_cmd_get_default(type);
|
||||
}
|
||||
|
||||
static inline void mlx5_fpga_ipsec_build_fs_cmds(void) {};
|
||||
|
||||
#endif /* CONFIG_MLX5_FPGA_IPSEC */
|
||||
#endif /* __MLX5_FPGA_IPSEC_H__ */
|
||||
|
||||
@ -1089,11 +1089,7 @@ static int mlx5_load(struct mlx5_core_dev *dev)
|
||||
goto err_fpga_start;
|
||||
}
|
||||
|
||||
err = mlx5_accel_ipsec_init(dev);
|
||||
if (err) {
|
||||
mlx5_core_err(dev, "IPSec device start failed %d\n", err);
|
||||
goto err_ipsec_start;
|
||||
}
|
||||
mlx5_accel_ipsec_init(dev);
|
||||
|
||||
err = mlx5_accel_tls_init(dev);
|
||||
if (err) {
|
||||
@ -1135,7 +1131,6 @@ err_fs:
|
||||
mlx5_accel_tls_cleanup(dev);
|
||||
err_tls_start:
|
||||
mlx5_accel_ipsec_cleanup(dev);
|
||||
err_ipsec_start:
|
||||
mlx5_fpga_device_stop(dev);
|
||||
err_fpga_start:
|
||||
mlx5_rsc_dump_cleanup(dev);
|
||||
@ -1628,7 +1623,7 @@ static int __init init(void)
|
||||
get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
|
||||
|
||||
mlx5_core_verify_params();
|
||||
mlx5_accel_ipsec_build_fs_cmds();
|
||||
mlx5_fpga_ipsec_build_fs_cmds();
|
||||
mlx5_register_debugfs();
|
||||
|
||||
err = pci_register_driver(&mlx5_core_driver);
|
||||
|
||||
@ -126,7 +126,7 @@ enum mlx5_accel_ipsec_cap {
|
||||
MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN = 1 << 7,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MLX5_FPGA_IPSEC
|
||||
#ifdef CONFIG_MLX5_ACCEL
|
||||
|
||||
u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
|
||||
|
||||
@ -152,5 +152,5 @@ static inline int
|
||||
mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
|
||||
const struct mlx5_accel_esp_xfrm_attrs *attrs) { return -EOPNOTSUPP; }
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_MLX5_ACCEL */
|
||||
#endif /* __MLX5_ACCEL_H__ */
|
||||
|
||||
@ -707,6 +707,9 @@ struct mlx5_core_dev {
|
||||
} roce;
|
||||
#ifdef CONFIG_MLX5_FPGA
|
||||
struct mlx5_fpga_device *fpga;
|
||||
#endif
|
||||
#ifdef CONFIG_MLX5_ACCEL
|
||||
const struct mlx5_accel_ipsec_ops *ipsec_ops;
|
||||
#endif
|
||||
struct mlx5_clock clock;
|
||||
struct mlx5_ib_clock_info *clock_info;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user