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drm/amdgpu:impl gfx9 cond_exec (v2)
it is needed for virtualization v2: squash in wptr value fix Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3224,6 +3224,31 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
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amdgpu_ring_write(ring, 0);
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}
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static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
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{
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unsigned ret;
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amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
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amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
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amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
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ret = ring->wptr & ring->buf_mask;
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amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
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return ret;
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}
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static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
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{
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unsigned cur;
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BUG_ON(offset > ring->buf_mask);
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BUG_ON(ring->ring[offset] != 0x55aa55aa);
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cur = (ring->wptr & ring->buf_mask) - 1;
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if (likely(cur > offset))
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ring->ring[offset] = cur - offset;
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else
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ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
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}
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static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
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{
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struct amdgpu_device *adev = ring->adev;
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@ -3575,6 +3600,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.emit_switch_buffer = gfx_v9_ring_emit_sb,
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.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
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.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
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.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
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};
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static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
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