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Merge tag 'amd-drm-fixes-5.6-2020-02-19' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
amd-drm-fixes-5.6-2020-02-19: amdgpu: - HDCP fixes - xclk fix for raven - GFXOFF fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200219173954.3847-1-alexander.deucher@amd.com
This commit is contained in:
commit
99edb18b86
drivers/gpu/drm/amd
amdgpu
display
powerplay
@ -1013,6 +1013,30 @@ static int psp_dtm_initialize(struct psp_context *psp)
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return 0;
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}
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static int psp_dtm_unload(struct psp_context *psp)
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{
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int ret;
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struct psp_gfx_cmd_resp *cmd;
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/*
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* TODO: bypass the unloading in sriov for now
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*/
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if (amdgpu_sriov_vf(psp->adev))
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return 0;
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cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
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if (!cmd)
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return -ENOMEM;
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psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
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ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
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kfree(cmd);
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return ret;
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}
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int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
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{
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/*
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@ -1037,7 +1061,7 @@ static int psp_dtm_terminate(struct psp_context *psp)
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if (!psp->dtm_context.dtm_initialized)
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return 0;
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ret = psp_hdcp_unload(psp);
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ret = psp_dtm_unload(psp);
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if (ret)
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return ret;
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@ -3923,11 +3923,13 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
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{
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uint64_t clock;
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amdgpu_gfx_off_ctrl(adev, false);
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mutex_lock(&adev->gfx.gpu_clock_mutex);
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WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
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clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
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((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
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mutex_unlock(&adev->gfx.gpu_clock_mutex);
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amdgpu_gfx_off_ctrl(adev, true);
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return clock;
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}
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@ -1193,6 +1193,14 @@ static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev)
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return false;
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}
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static bool is_raven_kicker(struct amdgpu_device *adev)
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{
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if (adev->pm.fw_version >= 0x41e2b)
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return true;
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else
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return false;
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}
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static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
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{
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if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
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@ -1205,9 +1213,8 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
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break;
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case CHIP_RAVEN:
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if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) &&
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((adev->gfx.rlc_fw_version != 106 &&
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((!is_raven_kicker(adev) &&
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adev->gfx.rlc_fw_version < 531) ||
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(adev->gfx.rlc_fw_version == 53815) ||
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(adev->gfx.rlc_feature_version < 1) ||
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!adev->gfx.rlc.is_rlc_v2_1))
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adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
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@ -3959,6 +3966,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
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{
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uint64_t clock;
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amdgpu_gfx_off_ctrl(adev, false);
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mutex_lock(&adev->gfx.gpu_clock_mutex);
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if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
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uint32_t tmp, lsb, msb, i = 0;
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@ -3977,6 +3985,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
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((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
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}
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mutex_unlock(&adev->gfx.gpu_clock_mutex);
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amdgpu_gfx_off_ctrl(adev, true);
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return clock;
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}
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@ -272,7 +272,12 @@ static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
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static u32 soc15_get_xclk(struct amdgpu_device *adev)
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{
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return adev->clock.spll.reference_freq;
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u32 reference_clock = adev->clock.spll.reference_freq;
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if (adev->asic_type == CHIP_RAVEN)
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return reference_clock / 4;
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return reference_clock;
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}
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@ -1911,7 +1911,7 @@ static void handle_hpd_irq(void *param)
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mutex_lock(&aconnector->hpd_lock);
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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if (adev->asic_type >= CHIP_RAVEN)
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if (adev->dm.hdcp_workqueue)
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hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
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#endif
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if (aconnector->fake_enable)
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@ -2088,8 +2088,10 @@ static void handle_hpd_rx_irq(void *param)
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}
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}
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
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if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
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if (adev->dm.hdcp_workqueue)
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hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
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}
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#endif
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if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
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(dc_link->type == dc_connection_mst_branch))
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@ -5702,7 +5704,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
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drm_connector_attach_vrr_capable_property(
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&aconnector->base);
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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if (adev->asic_type >= CHIP_RAVEN)
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if (adev->dm.hdcp_workqueue)
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drm_connector_attach_content_protection_property(&aconnector->base, true);
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#endif
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}
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@ -46,8 +46,8 @@ static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp)
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enum mod_hdcp_status status;
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if (is_dp_hdcp(hdcp))
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status = (hdcp->auth.msg.hdcp2.rxcaps_dp[2] & HDCP_2_2_RX_CAPS_VERSION_VAL) &&
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HDCP_2_2_DP_HDCP_CAPABLE(hdcp->auth.msg.hdcp2.rxcaps_dp[0]) ?
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status = (hdcp->auth.msg.hdcp2.rxcaps_dp[0] == HDCP_2_2_RX_CAPS_VERSION_VAL) &&
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HDCP_2_2_DP_HDCP_CAPABLE(hdcp->auth.msg.hdcp2.rxcaps_dp[2]) ?
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MOD_HDCP_STATUS_SUCCESS :
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MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
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else
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@ -898,6 +898,9 @@ int smu_v11_0_system_features_control(struct smu_context *smu,
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if (ret)
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return ret;
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bitmap_zero(feature->enabled, feature->feature_num);
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bitmap_zero(feature->supported, feature->feature_num);
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if (en) {
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ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
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if (ret)
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@ -907,9 +910,6 @@ int smu_v11_0_system_features_control(struct smu_context *smu,
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feature->feature_num);
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bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
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feature->feature_num);
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} else {
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bitmap_zero(feature->enabled, feature->feature_num);
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bitmap_zero(feature->supported, feature->feature_num);
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}
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return ret;
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