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iwlwifi: add ucode init flow handling for iwl5000
This patch adds all the handlers and functions needed for ucode initialization flow. Signed-off-by: Ron Rindjunsky <ron.rindjunsky@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Ron Rindjunsky
John W. Linville
parent
dbb983b70a
commit
99da1b48fc
@ -46,6 +46,16 @@
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#define IWL5000_UCODE_API "-1"
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static const u16 iwl5000_default_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_AC3,
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IWL_TX_FIFO_AC2,
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IWL_TX_FIFO_AC1,
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IWL_TX_FIFO_AC0,
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IWL50_CMD_FIFO_NUM,
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IWL_TX_FIFO_HCCA_1,
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IWL_TX_FIFO_HCCA_2
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};
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static int iwl5000_apm_init(struct iwl_priv *priv)
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{
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int ret = 0;
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@ -420,6 +430,151 @@ static int iwl5000_load_ucode(struct iwl_priv *priv)
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return ret;
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}
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static void iwl5000_init_alive_start(struct iwl_priv *priv)
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{
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int ret = 0;
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/* Check alive response for "valid" sign from uCode */
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if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
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/* We had an error bringing up the hardware, so take it
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* all the way back down so we can try again */
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IWL_DEBUG_INFO("Initialize Alive failed.\n");
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goto restart;
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}
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/* initialize uCode was loaded... verify inst image.
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* This is a paranoid check, because we would not have gotten the
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* "initialize" alive if code weren't properly loaded. */
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if (iwl_verify_ucode(priv)) {
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/* Runtime instruction load was bad;
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* take it all the way back down so we can try again */
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IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
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goto restart;
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}
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iwlcore_clear_stations_table(priv);
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ret = priv->cfg->ops->lib->alive_notify(priv);
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if (ret) {
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IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
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goto restart;
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}
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return;
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restart:
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/* real restart (first load init_ucode) */
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queue_work(priv->workqueue, &priv->restart);
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}
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static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
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int txq_id, u32 index)
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{
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iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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(index & 0xff) | (txq_id << 8));
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iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
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}
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static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
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struct iwl_tx_queue *txq,
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int tx_fifo_id, int scd_retry)
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{
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int txq_id = txq->q.id;
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int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
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iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
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(active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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(tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
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(1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
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IWL50_SCD_QUEUE_STTS_REG_MSK);
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txq->sched_retry = scd_retry;
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IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
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active ? "Activate" : "Deactivate",
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scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
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}
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static int iwl5000_alive_notify(struct iwl_priv *priv)
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{
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u32 a;
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int i = 0;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&priv->lock, flags);
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ret = iwl_grab_nic_access(priv);
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if (ret) {
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spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
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a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
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for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
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a += 4)
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iwl_write_targ_mem(priv, a, 0);
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for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
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a += 4)
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iwl_write_targ_mem(priv, a, 0);
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for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
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iwl_write_targ_mem(priv, a, 0);
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iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
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(priv->shared_phys +
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offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
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iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
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IWL50_SCD_QUEUECHAIN_SEL_ALL(
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priv->hw_params.max_txq_num));
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iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
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/* initiate the queues */
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for (i = 0; i < priv->hw_params.max_txq_num; i++) {
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iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
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iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
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sizeof(u32),
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((SCD_WIN_SIZE <<
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IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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((SCD_FRAME_LIMIT <<
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IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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}
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iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
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(1 << priv->hw_params.max_txq_num) - 1);
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iwl_write_prph(priv, IWL50_SCD_TXFACT,
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SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
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iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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/* map qos queues to fifos one-to-one */
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for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
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int ac = iwl5000_default_queue_to_tx_fifo[i];
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iwl_txq_ctx_activate(priv, i);
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iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
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}
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/* TODO - need to initialize those FIFOs inside the loop above,
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* not only mark them as active */
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iwl_txq_ctx_activate(priv, 4);
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iwl_txq_ctx_activate(priv, 7);
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iwl_txq_ctx_activate(priv, 8);
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iwl_txq_ctx_activate(priv, 9);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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/* Ask for statistics now, the uCode will send notification
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* periodically after association */
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iwl_send_statistics_request(priv, CMD_ASYNC);
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return 0;
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}
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static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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{
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if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
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@ -622,6 +777,8 @@ static struct iwl_lib_ops iwl5000_lib = {
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.disable_tx_fifo = iwl5000_disable_tx_fifo,
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.rx_handler_setup = iwl5000_rx_handler_setup,
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.load_ucode = iwl5000_load_ucode,
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.init_alive_start = iwl5000_init_alive_start,
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.alive_notify = iwl5000_alive_notify,
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.apm_ops = {
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.init = iwl5000_apm_init,
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.config = iwl5000_nic_config,
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@ -517,6 +517,34 @@
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#define IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
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/* 5000 SCD */
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#define IWL50_SCD_QUEUE_STTS_REG_POS_TXF (0)
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#define IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
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#define IWL50_SCD_QUEUE_STTS_REG_POS_WSL (4)
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#define IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
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#define IWL50_SCD_QUEUE_STTS_REG_MSK (0x00FF0000)
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#define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
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#define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
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#define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
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#define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
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#define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
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#define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
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#define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
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#define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
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#define IWL50_SCD_CONTEXT_DATA_OFFSET (0x600)
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#define IWL50_SCD_TX_STTS_BITMAP_OFFSET (0x7B1)
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#define IWL50_SCD_TRANSLATE_TBL_OFFSET (0x7E0)
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#define IWL50_SCD_CONTEXT_QUEUE_OFFSET(x)\
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(IWL50_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
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#define IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
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((IWL50_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffc)
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#define IWL50_SCD_QUEUECHAIN_SEL_ALL(x) (((1<<(x)) - 1) &\
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(~(1<<IWL_CMD_QUEUE_NUM)))
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#define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0)
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