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iwlwifi: Clean up unused definitions in iwl-3945-hw.h
Clean up unused definitions in iwl-3945-hw.h Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -102,10 +102,6 @@
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#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
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#define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
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/* EEPROM field values */
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#define ANTENNA_SWITCH_NORMAL 0
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#define ANTENNA_SWITCH_INVERSE 1
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/*
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* Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags.
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*
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@ -127,31 +123,10 @@ enum {
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EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
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EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
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EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
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EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel, not used */
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EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */
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EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
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};
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/* EEPROM field lengths */
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#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
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/* EEPROM field lengths */
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#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
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#define EEPROM_REGULATORY_SKU_ID_LENGTH 4
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#define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14
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#define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13
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#define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12
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#define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11
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#define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6
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#define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
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EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
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EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
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EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
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EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
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EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH)
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#define EEPROM_REGULATORY_NUMBER_OF_BANDS 5
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/* SKU Capabilities */
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#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
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#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
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@ -646,15 +621,7 @@ struct iwl3945_eeprom {
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/* spectrum and channel data structures */
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#define IWL_NUM_SCAN_RATES (2)
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#define IWL_SCAN_FLAG_24GHZ (1<<0)
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#define IWL_SCAN_FLAG_52GHZ (1<<1)
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#define IWL_SCAN_FLAG_ACTIVE (1<<2)
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#define IWL_SCAN_FLAG_DIRECT (1<<3)
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#define IWL_MAX_CMD_SIZE 1024
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#define IWL_DEFAULT_TX_RETRY 15
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#define IWL_MAX_TX_RETRY 16
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/*********************************************/
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@ -665,101 +632,6 @@ struct iwl3945_eeprom {
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#define RX_QUEUE_MASK 255
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#define RX_QUEUE_SIZE_LOG 8
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/* QoS definitions */
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#define CW_MIN_OFDM 15
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#define CW_MAX_OFDM 1023
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#define CW_MIN_CCK 31
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#define CW_MAX_CCK 1023
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#define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
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#define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
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#define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
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#define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
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#define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
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#define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
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#define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
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#define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
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#define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
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#define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
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#define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
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#define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
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#define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
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#define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
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#define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
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#define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
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#define QOS_TX0_AIFS 3
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#define QOS_TX1_AIFS 7
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#define QOS_TX2_AIFS 2
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#define QOS_TX3_AIFS 2
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#define QOS_TX0_ACM 0
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#define QOS_TX1_ACM 0
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#define QOS_TX2_ACM 0
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#define QOS_TX3_ACM 0
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#define QOS_TX0_TXOP_LIMIT_CCK 0
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#define QOS_TX1_TXOP_LIMIT_CCK 0
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#define QOS_TX2_TXOP_LIMIT_CCK 6016
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#define QOS_TX3_TXOP_LIMIT_CCK 3264
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#define QOS_TX0_TXOP_LIMIT_OFDM 0
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#define QOS_TX1_TXOP_LIMIT_OFDM 0
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#define QOS_TX2_TXOP_LIMIT_OFDM 3008
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#define QOS_TX3_TXOP_LIMIT_OFDM 1504
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#define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
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#define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
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#define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
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#define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
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#define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
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#define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
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#define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
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#define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
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#define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
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#define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
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#define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
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#define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
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#define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
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#define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
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#define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
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#define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
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#define DEF_TX0_AIFS (2)
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#define DEF_TX1_AIFS (2)
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#define DEF_TX2_AIFS (2)
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#define DEF_TX3_AIFS (2)
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#define DEF_TX0_ACM 0
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#define DEF_TX1_ACM 0
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#define DEF_TX2_ACM 0
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#define DEF_TX3_ACM 0
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#define DEF_TX0_TXOP_LIMIT_CCK 0
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#define DEF_TX1_TXOP_LIMIT_CCK 0
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#define DEF_TX2_TXOP_LIMIT_CCK 0
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#define DEF_TX3_TXOP_LIMIT_CCK 0
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#define DEF_TX0_TXOP_LIMIT_OFDM 0
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#define DEF_TX1_TXOP_LIMIT_OFDM 0
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#define DEF_TX2_TXOP_LIMIT_OFDM 0
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#define DEF_TX3_TXOP_LIMIT_OFDM 0
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#define QOS_QOS_SETS 3
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#define QOS_PARAM_SET_ACTIVE 0
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#define QOS_PARAM_SET_DEF_CCK 1
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#define QOS_PARAM_SET_DEF_OFDM 2
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#define CTRL_QOS_NO_ACK (0x0020)
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#define DCT_FLAG_EXT_QOS_ENABLED (0x10)
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#define U32_PAD(n) ((4-(n))&0x3)
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/*
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